This document provides instructions for creating and simulating a counter design using the Xilinx ISE design suite. It describes how to start ISE, create a new project, add a VHDL source file to define the counter module, generate a testbench waveform to simulate the design, and view the simulation results. Key steps include using language templates to add behavioral code to the counter, initializing timing settings for the testbench, and generating expected output values to create a self-checking testbench.
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
Cis 170 c Enhance teaching / snaptutorial.comHarrisGeorg51
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
In general, this lab will instruct you on:
1. how to create a project;
2. how to enter and save a program;
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++.
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
Howto implement a boolean logic function into hardware silicon? The hardware silicon used in this presentation is an FPGA (Xilinx Spartan3E starter kit). The software used is LabVIEW with the LabVIEW FPGA module and the SPARTAN3E driver.
Cis 170 Effective Communication / snaptutorial.comBaileyao
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
In general, this lab will instruct you on:
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
Cis 170 c Enhance teaching / snaptutorial.comHarrisGeorg51
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
In general, this lab will instruct you on:
1. how to create a project;
2. how to enter and save a program;
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++.
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
Howto implement a boolean logic function into hardware silicon? The hardware silicon used in this presentation is an FPGA (Xilinx Spartan3E starter kit). The software used is LabVIEW with the LabVIEW FPGA module and the SPARTAN3E driver.
Cis 170 Effective Communication / snaptutorial.comBaileyao
For more classes visit
www.snaptutorial.com
Lab 1 of 7: Getting Started (Your First C++ Programs)
Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
In general, this lab will instruct you on:
El silicio es el elemento electropositivo más abundante de la corteza terrestre. Es un metaloide con marcado lustre metálico y sumamente quebradizo. Por lo regular, es tetravalente en sus compuestos
Leading Manufacturer and Exporter from Jaipur, our product range includes Semi Precious Gemstones such as Peridot Cube Beads, Green Onyx Gemstone, Lapis Gemstone Tumbles, Lapis Lazuli Beads, Pyrope Garnet Gems, Tourmaline Beads and many more items.
En este número de la Revista Carta de España, editada por el Ministerio de Trabajo e Inmigración lo más destacado es Maria Pilar Pin en Chile y Perú, Padrón de españoles en el exterior, Convenio con la FEAER
Dossier Senssai Energy Festival Alicante ColaboradoresSenssaiWellness
Si eres una empresa, marca o profesional del sector fitness/wellness y te gustaría participar en Senssai Energy Open Festival (edición de Alicante) donde presentar tus productos, servicios y/o actividades, puedes contactar con nuestro departamento comercial y te indicamos como formar parte.
Tel. 635230672 / info@senssai.com
Presented by Jay Gary, Lane Jennings, Kate McCallum, and Alex McManus
Whether it is Teihard de Chardin's "omega point," Barbara Marx Hubbard's "conscious evolution," Ken Wilber's "integral theory," Ziauddin Sardar's "Islamic science" or Pope Francis' exhortation to simplicity, the religious imagination continues to reframe our quest toward transformation and tomorrow. This panel will share how the spiritual quest for "terra nova" is expressed in their own futures work ranging from transmedia in Hollywood entertainment, to a "Voxtropolis" mashup in Motown with rap and social entrepreneurs, to a journal that ponders how the spirituality of science fiction is creating a post-terrestrial age.
ABC Consolidated Financial InfoABC Companys current financial inf.docxransayo
ABC Consolidated Financial InfoABC Company's current financial information (before/without expansion)Dec. 31,20X2Dec. 31,20X1Cash$ 50,000$ 70,000Accounts receivable (net)$ 120,000$ 180,000Merchandise inventory$ 350,000$ 280,000Property plant, & equipment$ 400,000$ 300,000Less: Accumulated depreciation$ (170,000)$ (100,000)Total assets$ 750,000$ 730,000Accounts payable$ 250,000$ 210,000Income taxes payable$ 40,000$ 10,000Common stock$ 240,000$ 240,000Retained earnings$ 220,000$ 270,000Total liabilities & stock, equity$ 750,000$ 730,000The firm's accrual-basis income statement revealed the following data:Sales$ 1,200,000Cost of goods sold$ 800,000selling and administrative expenses$ 250,000Depreciation expense$ 70,000Income taxes$ 30,000Dividends declared and paid during 20X2$ 100,000ABC purchased $100,000 of equipment for cash on August 14, 20X2(There was no interest expense.)
ABC Product informationBased on Chapter 5's exercise 5ABC's Product informationCurrent ProductExpansion Product (estimate)Selling Price$14.50?Units produced and expected to be sold80,0005,000Machine Hours40,0005,000Direct Materials$1.30 per unit$5.60 per unitDirect labor dollars needed per product$2.80 per unit$4.00 per unitVariable Factory Overhead$1.00 per Machine Hour$1.00 per Machine HourVariable Selling Expense$0.20 per unit$0.20 per unitTotal Fixed Costs:Fixed Factory Overhead$ 198,000Fixed Selling expenses$ 191,250
UNIVERSITY OF CALIFORNIA, SANTA CRUZ
BOARD OF STUDIES IN COMPUTER ENGINEERING
CMPE13/L: INTRODUCTION TO PROGRAMMING IN C
Lab 1: Compiling, Running, and Debugging
Introduction
This is the first lab in CMPE13. Here we will demonstrate the basics of compiling and running C
programs in the simulator and on the Uno32 hardware. We will also explore the tools we will
use and some of their features for debugging problems you might encounter.
Reading
• Document on compiler errors
• Document on Unix and Git
• Document on software installation (if you want to run everything on your own computer)
• Document on style guidelines
• Document on MPLAB X
• Document on serial communications
• K&R Preface and Introduction
• K&R Sections 1.0-1.2, 4.5, 4.11
Provided Files
• part1.c: This file contains code that performs a simple sorting algorithm on five randomly
generated numbers. Follow the setup procedures listed below, add the requested
documentation, and format the code to follow the provided style guidelines.
• part2.c: This file contains an empty main() to be filled with the exercises from section 1.2 of
K&R. In addition, you will be asked to modify these exercises to add some additional
functionality. Detailed steps are listed below.
• BOARD.c/h - Contains initialization code for the UNO32 along with standard #defines and
system libraries used. Also includes the standard fixed-width datatypes and error return values.
You will not be modifying these fi.
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
CIS 170 Imagine Your Future/newtonhelp.com bellflower42
For more course tutorials visit
www.newtonhelp.com
Lab 1 of 7: Getting Started (Your First C++ Programs) Lab Overview - Scenario/Summary
Welcome to Programming with C++. The purpose of this three-part lab is to walk you through the following tutorial to become familiar with the actions of compiling and executing a C++ program.
15LLP108_Demo4_LedBlinking.pdf1. Introduction In D.docxfelicidaddinwoodie
15LLP108_Demo4_LedBlinking.pdf
1. Introduction
In Demo3, we have learned how to read sensor values of light, temperature and humidity of a node
and output these values to the console. In this demonstration, we will use the code from Demo3 and
learn how to turn on/off the LEDs and make them blinking regularly on the sensor node XM1000,
meanwhile to count how many times the LED has blinked and output the count to the console.
2. Timer
In order to make the blue LED on the XM1000 sensor node to blink in every half second (i.e. On 0.5S
and Off 0.5S), we also need a timer. Follow the instructions in Demo3 for configure and reset a timer.
We aslo need to create an infinite while() loop so that it runs our functions repeatedly, such as
counting the times the LED has blinked, output the counter’s value and actually turn on or off the
LEDs to make it blinking.
Please follow timer and while() loop structure in Demo3.
3. LED Blinking
To get access to the LED functionalities in Contiki, we need to include the LED header file in the
source code:
#include "leds.h" // file is in directory /home/user/contiki/core/dev
After the process begin, we have to initialise the LEDs on the sensor node by calling the following
function:
leds_init(); // Initialise the LEDs
And finally we can turn on, off, or blink the LEDs by the following functions:
void leds_on(unsigned char leds);
void leds_off(unsigned char leds);
void leds_toggle(unsigned char leds);
void leds_invert(unsigned char leds);
For example, if you want to blink the Blue LED, yon need to call the toggle function as:
void leds_toggle(LEDS_BLUE); // Toggle the blue LED
4. Exercise
Modify the program from Demo3 with periodic timer to make the BLUE led blinking in every half
second, also to count the blinking times and output the counted number to the console.
Can your change the code so that the BLUE LED is lighted for 1 second and off for 0.5 second
periodically?
15LLP108 – Internet of Things and Applications
Lab Session 2: Demo 4 – LED Blinking
Prepared by Xiyu Shi
5. Source code
Here is the source code for reference
#include "contiki.h"
#include "leds.h"
#include <stdio.h> /* for printf() */
static struct etimer timer;
/*____________________________________________________*/
PROCESS(led_blinking_process, "LED Blinking Process");
PROCESS(LED_process, "LED process");
AUTOSTART_PROCESSES(&LED_process);
/*____________________________________________________*/
PROCESS_THREAD(LED_process, ev, data)
{
static int count = 0;
PROCESS_BEGIN();
etimer_set(&timer, CLOCK_CONF_SECOND/2); // 0.5S timer
leds_init(); // intialise the LEDs
while(1) {
PROCESS_WAIT_EVENT_UNTIL(ev==PROCESS_EVENT_TIMER); // wait for timer event
count++; // count the blinking times
process_start(&led_blinking_process, NULL); // to blink the BLUE Led
printf("Count: %d\n", count); // output the counte ...
Francesca Gottschalk - How can education support child empowerment.pptxEduSkills OECD
Francesca Gottschalk from the OECD’s Centre for Educational Research and Innovation presents at the Ask an Expert Webinar: How can education support child empowerment?
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
A Strategic Approach: GenAI in EducationPeter Windle
Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
Operation “Blue Star” is the only event in the history of Independent India where the state went into war with its own people. Even after about 40 years it is not clear if it was culmination of states anger over people of the region, a political game of power or start of dictatorial chapter in the democratic setup.
The people of Punjab felt alienated from main stream due to denial of their just demands during a long democratic struggle since independence. As it happen all over the word, it led to militant struggle with great loss of lives of military, police and civilian personnel. Killing of Indira Gandhi and massacre of innocent Sikhs in Delhi and other India cities was also associated with this movement.
Introduction to AI for Nonprofits with Tapp NetworkTechSoup
Dive into the world of AI! Experts Jon Hill and Tareq Monaur will guide you through AI's role in enhancing nonprofit websites and basic marketing strategies, making it easy to understand and apply.
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
Objective:
Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
Welcome to TechSoup New Member Orientation and Q&A (May 2024).pdfTechSoup
In this webinar you will learn how your organization can access TechSoup's wide variety of product discount and donation programs. From hardware to software, we'll give you a tour of the tools available to help your nonprofit with productivity, collaboration, financial management, donor tracking, security, and more.
Honest Reviews of Tim Han LMA Course Program.pptxtimhan337
Personal development courses are widely available today, with each one promising life-changing outcomes. Tim Han’s Life Mastery Achievers (LMA) Course has drawn a lot of interest. In addition to offering my frank assessment of Success Insider’s LMA Course, this piece examines the course’s effects via a variety of Tim Han LMA course reviews and Success Insider comments.
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
Unit 8 - Information and Communication Technology (Paper I).pdf
Ecad final
1. INTRODUCTION TO XILINX
Starting the ISE Software:
To start ISE, double-click the desktop icon,or start ISE from the Start menu by
selecting:
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
Note: Your start-up path is set during the installation process and may differ from the
one above.
Accessing Help
At any time during the tutorial, you can access online help for additional information
about the ISE software and related tools.
To open Help, do either of the following:
Press F1 to view Help for the specific tool or function that you have selected or
highlighted. Launch the ISE Help Contents from the Help menu. It contains
information about creating and maintaining your complete design flow in ISE.
Create a New Project:
Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is
created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
2. 6. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Module Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Verify that Enable Enhanced Design Summary is selected.
7.Leave the default values in the remaining fields.
8. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
9.When the table is complete, your project properties will look like the following:
Create an HDL Source:
In this section, you will create the top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the “Creating a VHDL
Source” section below, or skip to the “Creating a Verilog Source” section.
Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.
3. 4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:
7. Click Next, then Finish in the New Source Information dialog box to complete the new
source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below:
4. Using Language Templates (VHDL):
The next step in creating the new source is to add the behavioral description for the counter.
To do this you will use a simple counter code example from the ISE Language
Templates and customize it for the program design.
1. Place the cursor just below the begin statement within the counter architecture.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window →
Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
VHDL → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
5. 4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file.
5. Close the Language Templates.
Final Editing of the VHDL Source:
1. Add the following signal declaration to handle the feedback of the counter output below
the architecture declaration and above the first begin statement:
signal count_int : std_logic_vector(3 downto 0) := "0000";
2. Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of <clock> with CLOCK
♦ replace all occurrences of <count_direction> with DIRECTION
♦ replace all occurrences of <count> with count_int
3. Add the following line below the end process; statement:
COUNT_OUT <= count_int;
4. Save the file by selecting File → Save.
When you are finished, the counter source file will look like the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
6. signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
if count_int < ”1111” then
count_int <= count_int + 1;
else
count_int<=”0000”;
end if;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
Checking the Syntax of the New Counter Module:
When the source files are complete, check the syntax of the design to find errors and typos.
1. Verify that Synthesis/Implementation is selected from the drop-down list in the
Sources window.
2. Select the counter design source in the Sources window to display the related
processes in the Processes window.
3. Click the “+” next to the Synthesize-XST process to expand the process group.
Double-click the Check Syntax process.
4. Note: You must correct any errors found in your source files. You can check for
errors in the Console tab of the Transcript window. If you continue without valid
syntax, you will not be able to simulate or synthesize your design.
7. 5. Close the HDL file.
Design Simulation:
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a
test bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type, and
type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench
waveform
with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it
displays
the source directory, type and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the
Initialize
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
♦ The counter must operate correctly with an input clock frequency = 25 MHz.
♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.
The design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
8. ♦ Clock Time High: 20 ns.
♦ Clock Time Low: 20 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
♦ Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value
automatically.
♦ Initial Length of Test Bench: 1500 ns.
Leave the default values in the remaining fields.
8. Click Finish to complete the timing initialization.
9. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input
Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the
input stimulus for the counter design as follows:
♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the
counter will count up.
♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION high so that the
counter will count down.
Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar
buttons.
10. Save the waveform.
11. In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project.
12. Close the test bench waveform.
Create a Self-Checking Test Bench Waveform:
10. Add the expected output values to finish creating the test bench waveform. This transforms
the test bench waveform into a self-checking test bench waveform. The key benefit to a self-
checking test bench waveform is that it compares the desired and actual output values and
flags errors in your design as it goes through the various transformations, from behavioral
HDL to the device specific representation.
To create a self-checking test bench, edit output values manually, or run the Generate
Expected Results process to create them automatically. If you run the Generate Expected
Results process, visually inspect the output values to see if they are the ones you expected
for the given set of input values.
To create the self-checking test bench waveform automatically, do the following:
1. Verify that Behavioral Simulation is selected from the drop-down list in the Sources
window.
2. Select the counter_tbw file in the Sources window.
3. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-
click the Generate Expected Simulation Results process. This process simulates the design
in a background process.
4. The Expected Results dialog box opens. Select Yes to annotate the results to the test
bench.
5. Click the “+” to expand the COUNT_OUT bus and view the transitions that correspond to
the Output Delay value (yellow cells) specified in the Initialize Timing dialog box.
6. Save the test bench waveform and close it. You have now created a self-checking test
bench waveform. Simulating Design Functionality
Verify that the counter design functions as you expect by performing behavior simulation as
follows:
11. 1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window.
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-
click the Simulate Behavioral Model process. The ISE Simulator opens and runs the
simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the transitions.
The simulation waveform results will look like the following:
12. Experiment No: 1
REALIZATION OF LOGIC GATES
AIM:
To write a VHDL programs for Logic gates and simulate them by using XILINX 8.2i Soft
ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
AND GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
c<=a and b;
end Behavioral;
OR GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or1 is
13. Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or1;
architecture Behavioral of or1 is
begin
c<=a or b;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM FOR AND GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION):
RTL SCHEMATIC DIAGRAM OR GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION):
14. NOT GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in STD_LOGIC;
anot : out STD_LOGIC);
end not1;
architecture Behavioral of not1 is
begin
anot<= not a;
end Behavioral;
16. NAND GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nand1;
architecture Behavioral of nand1 is
begin
c<=a nand b;
end Behavioral;
NOR GATE:
PROGRAM:
17. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end nor1;
architecture Behavioral of nor1 is
begin
c<=a nor b;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM FOR NAND GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION):
18. RTL SCHEMATIC DIAGRAM FOR NOR GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION):
EX-OR GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end exor1;
architecture Behavioral of exor1 is
begin
c<=a xor b;
end Behavioral;
EX-NOR GATE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exnor1 is
Port ( a : in STD_LOGIC;
19. b : in STD_LOGIC;
c : out STD_LOGIC);
end exnor1;
architecture Behavioral of exnor1 is
begin
c<=a xnor b;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM EX-OR GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION) :
20. RTL SCHEMATIC DIAGRAM FOR EX-NOR GATE:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
21. The VHDL programs for Logic gates are written and simulated by using XLINX8.2i version and the
Outputs are verified.
Experiment No: 2
3 TO 8 DECODER
AIM:
To write a VHDL program for 3 to 8 Decoder and simulate it by using XILINX8.2i Soft
ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
22. entity dc1 is
Port ( en : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end dc1;
architecture Behavioral of dc1 is
begin
process(en,x)
begin
if en='0' then y<="00000000";
else
case x is
when "000"=>y<="00000001";
when "001"=>y<="00000010";
when "010"=>y<="00000100";
when "011"=>y<="00001000";
when "100"=>y<="00010000";
when "101"=>y<="00100000";
when "110"=>y<="01000000";
when "111"=>y<="10000000";
when others=>null;
end case;
end if;
end process;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
23. OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
24. 7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for 3 to 8 Decoder is written and simulated by using XLINX8.2i version and the
Output is verified.
Experiment No: 3
8X1 MULTIPLEXER AND 2X4 DE-MULTIPLEXER
AIM:
To write a VHDL program for 8X1 Multiplexer and simulate it by using XILINX8.2i Soft ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
25. use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mul1 is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end mul1;
architecture Behavioral of mul1 is
begin
process(sel,x)
begin
case sel is
when "000"=>y<=x(0);
when "001"=>y<=x(1);
when "010"=>y<=x(2);
when "011"=>y<=x(3);
when "100"=>y<=x(4);
when "101"=>y<=x(5);
when "110"=>y<=x(6);
when "111"=>y<=x(7);
when others=>null;
end case;
end process;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
26. OUTPUT WAVEFORMS (AFTER SIMULATION):
2X4 DE-MULTIPLEXER
AIM:
To write a VHDL program for 2X4 De-Multiplexer and simulate it by using XILINX8.2i Soft ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
27. entity dem1 is
Port ( sel : in STD_LOGIC_VECTOR (1 downto 0);
x : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end dem1;
architecture Behavioral of dem1 is
begin
process(x,sel)
begin
y<="0000";
case sel is
when "00"=>y(0)<=x;
when "01"=>y(1)<=x;
when "10"=>y(2)<=x;
when "11"=>y(3)<=x;
when others=>null;
end case;
end process;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
28. OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
29. 5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL programs for 8X1 Multiplexer and 2X4 De-multiplexer are written and simulated by
using XLINX8.2i version and the Output is verified.
Experiment No: 5
D-FLIPFLOP
AIM:
To write a VHDL program for D-FLIP FLOP and simulate it by using XILINX8.2i Software.
SOFTWARE:
1.XILINX 8.2i
30. 2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff1 is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
q1 : out STD_LOGIC;
q2 : out STD_LOGIC);
end dff1;
architecture Behavioral of dff1 is
begin
process(d,clk)
begin
if(d='0'and clk='1') then
q1<='0';
q2<='1';
else if(d='1' and clk='1') then
q1<='1';
q2<='0';
end if;
end if;
end process;
end Behavioral;
BLOCK DIAGRAM:
32. PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for D-FLIPFLOP is written and simulated by using XLINX8.2i version and the
Output is verified.
33. Experiment No: 4
4-BIT COMPARATOR
AIM:
To write a VHDL program for 4-Bit Comparator and simulate it by using XILINX8.2i
Software.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity compare is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
EQ,NE,GT,GE,LT,LE : out STD_LOGIC);
end compare;
architecture Behavioral of compare is
begin
process(A,B)
begin
EQ<='0';NE<='0';GT<='0';GE<='0';LT<='0';LE<='0';
if A = B then EQ<='1';end if;
if A /= B then NE<='1';end if;
if A > B then GT<='1';end if;
if A >= B then GE<='1';end if;
if A < B then LT<='1';end if;
if A <= B then LE<='1';end if;
end process;
end Behavioral;
35. OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
36. The VHDL program for 4-Bit comparator is written and simulated by using XLINX8.2i version and
the Output is verified.
Experiment No: 6
DECADE COUNTER
AIM:
To write a VHDL program for Decade Counter and simulate it by using XILINX8.2i
Soft ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
port (clk: in STD_LOGIC;
reset: in STD_LOGIC;
q: out STD_LOGIC _VECTOR(3 downto 0) );
end Counter;
architecture Behavioural of Counter is
begin
37. process(clk,reset)
variable qtemp: std_logic_vector(3 downto 0);
begin
if reset='1' then
qtemp:="0000";
else
if clk='1' then
if qtemp<9 then
qtemp:=qtemp+1;
else
qtemp:="0000";
end if;
end if;
q<=qtemp;
end if;
end process;
end Behavioural;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
38. OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source”
section below.
4. The next step in creating the new source is to add the behavioral description for the
program.
39. 5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the
functionality of the program module.
10. Save the waveform.
RESULT:
The VHDL program for Decade Counter is written and simulated by using XLINX8.2i
version and the Output is verified.
Experiment No: 7
SHIFT REGISTERS
AIM:
To write a VHDL program for Shift Register and simulate it by using XILINX 8.2i Soft ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
40. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift is
Port ( C,SI : in STD_LOGIC;
SO : out STD_LOGIC);
end shift;
architecture Behavioral of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end Behavioral;
BLOCK DIAGRAM:
41. RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
42. 6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for Shift Register is written and simulated by using XLINX8.2i version and the
Output is verified.
Experiment No: 8
UNIVERSAL SHIFT REGISTERS
AIM:
To write a VHDL program for Universal Shift Register and simulate it by using XILINX 8.2i Soft
ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
43. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity univ1 is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
CLK,RST : in STD_LOGIC;
SIR,SIL : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end univ1;
architecture Behavioral of univ1 is
begin
process(CLK, RST) is
variable REG : std_logic_vector(3 downto 0);
begin
if (RST = '0') then
REG := (others => '0');
elsif rising_edge(clk) then
case S is
when "11" =>
REG := D;
when "01" =>
REG := SIR & REG(3 downto 1);
when "10" =>
REG := REG(2 downto 0) & SIL;
when others =>null;
end case;
end if;
Q <= REG;
end process;
end Behavioral;
BLOCK DIAGRAM:
RTL SCHEMATIC DIAGRAM:
44. OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
45. 4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for Universal Shift Register is written and simulated by using XLINX8.2i
version and the Output is verified.
Experiment No: 9
4-BIT COUNTER
AIM:
To write a VHDL program for 4-Bit Counter and simulate it by using XILINX 8.2i Soft ware.
SOFTWARE:
46. 1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count1 is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (3 downto 0));
end count1;
architecture Behavioral of count1 is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if count_int < "1111" then
count_int <= count_int + 1;
else
count_int<="0000";
end if;
end if;
end process;
COUNT <= count_int;
end Behavioral;
BLOCK DIAGRAM:
47. RTL SCHEMATIC DIAGRAM:
OUTPUT WAVEFORMS (AFTER SIMULATION):
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
48. 6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for 4-Bit Counter is written and simulated by using XLINX8.2i version and the
Output is verified.
Experiment No: 10
ALU DESIGN
AIM:
To write a VHDL program for Arithmetic and Logic Unit and simulate it by using XILINX
8.2i Soft ware.
SOFTWARE:
49. 1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
port
(
Input1, Input2 : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Flag : out std_logic;
Result : out std_logic_vector(3 downto 0)
);
end entity alu;
architecture Behavioral of alu is
signal Temp: std_logic_vector(4 downto 0);
begin
process(Input1, Input2, Operation, temp) is
begin
Flag <= '0';
case Operation is
when "000" => -- res = in1 + in2, flag = carry = overflow
Temp <= (unsigned("0" & Input1) + unsigned(Input2));
Result <= temp(3 downto 0);
Flag <= temp(4);
when "001" => -- res = |in1 - in2|, flag = 1 if in2 > in1
if (Input1 >= Input2) then
Result <= (unsigned(Input1) - unsigned(Input2));
Flag <= '0';
else
Result <= (unsigned(Input2) - unsigned(Input1));
Flag <= '1';
end if;
when "010" =>
Result <= Input1 and Input2;
when "011" =>
Result <= Input1 or Input2;
when "100" =>
Result <= Input1 xor Input2;
when "101" =>
Result <= not Input1;
when "110" =>
Result <= not Input2;
when others => -- res = in1 + in2 + 1, flag = 0
Temp <= (unsigned("0" & Input1)) + (unsigned(not Input2) + 1);
50. Result <= temp(3 downto 0);
Flag <= temp(4);
end case;
end process;
end architecture Behavioral;
PROCEDURE:
1.Start the Xilinx ISE software by Double clicking on the Icon or
Start → All Programs → Xilinx ISE 8.2i → Project Navigator
2.Create a new project by Selecting File > New Project...
3. Create a VHDL source file, then, continue either to the “Creating a VHDL Source” section below.
4. The next step in creating the new source is to add the behavioral description for the program.
5.Place the cursor just below the begin statement within the program architecture.
6. Save the file by selecting File → Save.
7.When the source files are complete, check the syntax of the design to find errors and types.
8.Verify the Functionality using Behavioral Simulation.
9.Create a test bench waveform containing input stimulus you can use to verify the functionality of
the program module.
10. Save the waveform.
RESULT:
The VHDL program for Arithmetic and Logic Unit is written and simulated by using XLINX8.2i
version and the Output is verified.
BLOCK DIAGRAM:
53. AIM:
To write a VHDL program for Random Access Memory and simulate it by using XILINX
8.2i Soft ware.
SOFTWARE:
1.XILINX 8.2i
2.ISE Simulator
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram16to4 is
Port ( clk,en,rwbar : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (3 downto 0);
datain : in STD_LOGIC_VECTOR (3 downto 0);
dataout : out STD_LOGIC_VECTOR (3 downto 0));
end ram16to4;
architecture Behavioral of ram16to4 is
type ram_type is array (0 to 15) of std_logic_vector(3 downto 0);
signal tmp_ram:ram_type;
begin
process(clk,rwbar)
begin
if(clk='1' and clk'event) then
if(en='1') then
if(rwbar='1') then
dataout<= tmp_ram(conv_integer(addr));
elsif(rwbar='0')then
tmp_ram(conv_integer(addr))<=datain;
else
dataout<=(dataout'range=>'Z');
end if;
else
dataout<=(dataout'range=>'Z');
end if;
end if;
end process;
end Behavioral;