This document is a detailed tutorial for using Cadence tools to design and simulate amplifiers with the gpdk180 process design kit. It covers aspects such as schematic simulation, layout creation, and verification, providing step-by-step instructions and essential parameters for successful implementation. The tutorial emphasizes the importance of following specific procedures and offers troubleshooting for common errors during design and simulation.

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Amplifier Simulation Tutorial
Design Kit: Cadence 0.18μm CMOS PDK (gpdk180)
(Cadence Version 6.1.5)
Yongsuk Choi, Marvin Onabajo
This tutorial provides a quick introduction to the use of Cadence tools for schematic simulation, layout
creation, layout verification, and post-layout simulation of amplifiers. A common-source amplifier is used as
example circuit (FYI: This design is not optimized). Screenshots for the main steps are given instead of
lengthy explanations. Please make sure to use exactly the same options as shown in the screenshots. It is
advisable to go through one of the general Cadence tutorials first, and then use this one as a more specific
guide for the gpdk180 design kit.
1) Opening Cadence 6.1.5
- Follow the instructions in the “Cadence 1 - Access Instructions” document to open the gpdk180
process design kit (PDK)
- Example command sequence when opening the PDK for the second time:
…
# source cadence_05142014.csh [or the latest file version]
# cd cadence_gpdk180/ [or any other name that you used as personal PDK directory]
# virtuoso &
The following command interface window (CIW) will open:
2) Library creation
- Create a library with an arbitrary name. You can create several circuits and simulation testbenches in this
library later: tools => library manager will open the following window:

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- Sequence of windows/options:
=> =>
3) Schematic Simulation
a) Schematic creation
- Select the newly created library (e.g., tutorial_library) in the library manager
- Create a new schematic cellview:
=> =>

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- The last window in the above sequence is the schematic window. As explained in general Cadence tutorials,
you can add schematic components from existing general libraries (e.g., analogLib, basic) or from the PDK
library (i.e., gpdk180 in this case)
- For example, let us begin by making the schematic for a cellview with the common-source amplifier and the
bias circuit as shown below. (One could also create a single cellview for all amplifier devices, but designers
often chose to split circuits to simplify layout. In this tutorial, only a few devices in the amplifier are laid out
to also show how simulations can be performed with some schematic components and some layout
components.)
- To add the components above, choose “Create => instance” form the cellview menu (or shortcut:
“i”), then click on Browse in the new window. Select the gpdk library and pick the component to be
placed in the schematic. Example for the standard NMOS transistor:
=>

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- You can enter the desired transistor dimensions in the second window (above) or just place the
transistor in the schematic cellview (left mouse click). After placing the transistor in the schematic, it
can be editing by selecting it with a left mouse click and choosing “Edit => Properties => Objects”
(shortcut: “q”) from the menu.
- The two windows below list the complete properties for the NMOS transistor. Make sure that all
fields are matched, which will be critical for layout purposes. Some comments on important
parameters are below.
o Multiplier: specified the number of devices that will be modeled in parallel. (When using the
Layout XL tool later, the tool will place this number of devices [here: 1] in the layout cell view.
o Fingers: number of fingers of the transistor layout
o Gate connection: “Top” => the gate will be formed at the top of the transistor
o S/D connection: “both” => the source and drain terminals will be formed automatically (with
contacts)
o Bodytie type: “detached” means that the bulk will be generated separately from the source in
the layout. (other options: “intergrated” => bulk and source will automatically be merged in
the layout, “none” => no bulk connection will be generated, and you will have to place M1-
to_subtrate contacts manually)
o Left Tap (selected) the body tap will be placed on the left side of the transistor
- The other devices can be placed following the same steps as for the NMOS transistor. Their
properties are shown in the screenshots below.

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polysilicon resistors:

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metal-insulator-metal capacitor:
- You can connect components with wires by selecting “create => wire” from the menu (shortcut: “w”).
- To add pins, select “Create => pins” from the cellview menu. Use the input-output designation in the
“Direction” field as shown below for all pins.
- After finishing the component placements and connections, select “File => check & and save” from
the menu.

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b) Creating a symbol for a schematic
- Choose “create => cellview => from cellview” in the menu. Next, follow the following sequence:
=>
=> =>
- “Check and save” the symbol, then close the last window above.
- You can now insert this symbol as a component in other schematic cellviews. Notice that the symbol
cellview now also appears in the library manager:

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- Within the tutorial library, create a new schematic cellview named AMPexample_TB (same steps as
before) in which the remaining amplifier and testbench components will be placed:
- To insert the subcircuit with the cascode and load devices, choose“Create => instance => browse” in
the cellveiw menu, select the newly created library (here: tutorial_library), and then pick the
subcircuit (AMPexample) symbol to be placed in the new cellview:
- The other components (in the schematic below) can be placed using the same procedure as before,
but choosing them from the appropriate libraries.

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- The properties of all components are listed below. Notice some relevant ones that are helpful to
identify the devices:
o Library Name: the library in which the component can be found
o Cell name: the name of the component
o Instant name: the specific designation of the component in a given cellview. The numbers
are automatically changed when components are placed to avoid duplicate designations
(e.g., V0 and V1 for the voltage sources)
o Parameters can specified as variables (ex.: amp_in, which is the amplitude for the input
signal source). Enter the same variable names, for which values will be specified prior to
simulation.

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Sources and global connectors:

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Input source:
Input capacitor: Output:

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- Labels can be added with “Create => wire name => enter name (ex.: “Out”) => click on the wire in
the schematic
- “Check and save” the schematic
- FYI: You can always edit the cellviews in your schematic that are consisting of subcircuits. For
example, select the AMPexample cellview with a left mouse click and select “Edit => hierarchy =>
descend edit…” in the schematic window. Next, click “ok” to decent into the cell, which can be
edited. Note, if the cellview is reused in other circuits, the edits will take effect in those circuits as
well. Furthermore, you have to “check and save” after editing in order to be able to run a simulation.
To go back to the higher-level hierarchy, choose “Edit => Hierarchy => return” from the menu.
c) Schematic simulation
- Launch the Analog Design Environment (ADE) by selecting “Launch => ADE L” from the schematic
cellview (AMPexample_TB), which will open the following ADE window:
- Select “Variables => Copy from cellview” to enter the previously defined variables in the table on the
left of the window. Use the following values:
- Analysis can be setup through the ADE window as follows: “Analysis => choose” => enter an
analysis of interest => click apply => enter the parameters for the next analysis => apply => … => ok
As an example, setup all the simulations below with the same settings as in the screenshots.

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DC: Transient :
AC: Noise:

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ADE window after entering all analyses above:
- In the ADE window, select: simulation => options => analog. Enter the following settings to improve
the accuracy of the simulation (compared to the default settings):
You can save the simulation setting as a state for the cellview “Session => save state => check the cellview
option” (and reopen it later with “Session => load state => cellview option”):

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- Notice the following menu in the ADE: “Setup => simulator/directory/host”
=> by default, the simulation data is stored in a subdirectory called “simulation” within your home
directory. Within the simulation directory, the data is stored in subdirectories for each testbench.
From time to time you might want to delete old simulation data to avoid reaching the data quota for
your account (Simulations will abort in such a case.). For example, after finishing the work related to
this testbench (AMPexample_TB), you can delete the data from a terminal window:
# cd ~/simulation
# ls [=> check that the AMPexample_TB folder is in this directory]
# rm –r AMPexample_TB
When running long transient simulations, you can also save the data in the shared (public)
temporary directory(“/tmp”). To do so, go into the /tmp directory and use the “mkdir” command to
create a subdirectory with your username. (Using your username as subdirectory will avoid that two
users accidently use the same file names such as AMPexample_TB, which can cause Cadence to
crash while running simulations.) Afterwards, change the project directory name to the newly created

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directory as shown in the screenshot below.
- Start the simulations by selection “Simulation => Netlist and run” from the ADE menu.
- On ADE window, click “Annotate => DC Operation Points”. To see inside circuit of AMPexample,
right click the AMPexample symbol and select “Descend Read” to open its schematic view.
- One method to plot results is with the Cadence calculator (tools => calculator in the ADE window).
For example, to plot the transient output, click on “vt”, click on the net labeled “Out” in the schematic,
and then select “Tools => plot” from the calculator menu (as shown below)

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Outputs can be added in the ADE (to be saved with states). In the ADE window, select “Output =>
setup”. Click on “get expression”, which will transfer the current formula in the calculator.
=> The transient output voltage will now be automatically plotted after a simulation.
- One way to plot ac simulation results is with “Results => Direct Plot => AC Gain & Phase …” in the
ADE window. Then, select “Out” net in schematic window and the “In” net. Afterwards, press the
ESC key.

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- An alternative way for plotting results is with “Results => direct plot => main form …” in the ADE
window. Select the “noise” menu to plot noise as displayed below. Click on “Plot”. When “Add to
Outputs” is selected, then the plot will also be saved in the ADE and automatically plotted after
running another simulation”. Use this window to plot input-referred noise and output-referred noise.

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Results:
- You can print noise summary in ADE with “Results => Print => Noise Summary”
Select integrated noise range from lower 3dB frequency to upper 3dB frequency values from ac
simulation.

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ADE window after the simulation:
(You can refresh the outputs with “Results => Plot outputs => Expressions”)

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4) Layout creation and verification
a) Layout generation
- Open the previously created “AMPexample” cellview from the library manager.
- Select “Launch => Layout XL” from the menu
=> => => click “ok”, then “yes” at the next window

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- The layout XL window below will be opened:
- Select “Connectivity => Generate => All from Source…” in the menu of the above layout window and
use the following options:

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- Click “shift + f” to refresh the view and make all layers visible. Alternatively, you can update the
displayed layers (“Options => Display”) by changing “Stop” under “Display Levels” from 0 to 32:
Also note in the above window that the X and Y Snap Spacing under Grid Controls are set to 0.005.
- You should not be able to see all components in the layout as below. Notice that the devices have
the same dimensions (and parameter options) as in the schematic.

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- Since the schematic window remains open (and linked) to the layout window when using Layout XL,
you can select a device in the schematic and it will be heighted in the layout:
- If you change device parameters in the schematic, you can use “Connectivity => Update =>
Components and Nets” in the layout window to automatically update the layout:
- Zoom into the transistor (as below). Another Layout XL feature is that it highlights schematic
elements to help manual routing when the path option is used.
o Select metal 1 in the layer subwindow:
o Use “Create => Shape => path” (shortcut: “p”) in the main layout window to make a path.
Click (left mouse button) on the drain. As can be seen in the screenshot below, the
corresponding net in the schematic is highlighted to assist the routing. In addition, the line in
the top right corner of the layout window leads to the next point where the drain should be
connected in the layout.

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o Creating the path: move the mouse to stretch the path, left-click to make a corner, enter to
end the path (at the other component to be connected).
o You can follow the other general Cadence tutorials on the Blackboard site for the course to
complete the layout by moving and connecting components. The finished layout is displayed
below as an example. Notice that it only serves for instructional purposes since it is not
optimized according to the analog layout practices and recommendations discussed in the
lecture/references.
Some general and PDK-specific layout information and recommendations is included in the remainder of
this subsection.
- The capacitor connections have to be made on the metal 3 (top plate) and metal 2 (bottom plate)
layers
- To make connections between layers, you can use “Create => Via”. For example, to create vias
between metals, one way is to use the “single” mode:

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=> creates a 2 x 2 via (2 rows and 2 columns) between metal 2 and metal 3.
Alternatively, the “stack” mode can be used to place vias between multiple layers:
=> creates a 3 x 3 via stack between metal 1, 2, and 3 (connecting all of them)

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You can use the same menu to place a row or column of substrate contacts:
=> Creates a row of 10 contacts between the p-type substrate and metal 1 (to be connected to VSS)
[To place contacts to N-wells (for connection to Vdd), you can use the M1_NWELL option instead]
- To place pins, select the appropriate pin layer in the layout window:
(example Metal3_pin to place a pin on a metal 3 area)
Next, choose “Create => Pin” from the menu, and enter the following options:
(example for VDD – in the “Terminal Name” field)

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You can now make a rectangle using the left mouse button in the layout, and finally place the label
within the pin with another left-click:
Note: All pin names in the layout and schematic must match exactly to pass LVS.

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b) Layout verification
Note, it is good practice to create a folder (example name: verification) within the subdirectory of the PDK
folder. The data for DRC, LVS, and QRC should all be in the same folder, which can be ensured by
specifying the correct path before running each tool (as shown in the “run directory” fields of the
screenshots in this section). You can create a dedicated directory by entereing the following commands in a
terminal window:
# cd ~/cadence_gpdk180
[cadence_gpdk180 is the personal directory for the PDK, which you might have named differenctly]
# mkdir verification
=> When running verification tools, specify the “verification” directory with its full path in the “Run
Directory” field (as in the relevant figures below). You can click on “…” to browse within your home
directory.
DRC (design rule check)
In the layout window, select “Assura => Run DRC”. Specify the follwowing options, where the Run Directory
should be the “verification” subdirectory within your home directory:
You should receive a result without DRC errors:
If some DRC rules are not satisified (see gpdk180_DRM.pdf on the Blackboard site), then you will receive
the following window:

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=> You can select the type of error (here [1] from the list), and lick on the circled button to zoom into the
next error occurance (the position and zoom in the layout window will be updated automatically). Fix all
error an rerun the DRC until it is error-free.
LVS (layout vs. schematic check)
Select “Assura => Run LVS“ in the layout window, and choose the same options as in the window below.
The LVS result should be as follows:

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If the layout and schematic have compenent or net mismatches, then you can use the following pop-up
windows to find the errors:
=>
=> click on “Open Tool…” =>
Resolve the problems and rerun LVS until the layout and schematic match.

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Extraction (QRC)
* Before executing extraction, make sure that you always complete the full DRC => LVS sequence. Even
after small chagnes, you should run DRC and LVS before QRC.
Select “QRC => Setup QRC” in the layout window. Go through the tabs and match all sections as shown in
the screenshots below.

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Notes:
- Use the default options for settigns that are not displayed above.
- Extraction type: RC => With this option, parasitc resistances and capacitances will be extracted and
added to the netlist for post-layout simulations
- RefNode: VSS [The name of the ground pin in the schematic/layout (used for substrate biasing)
should be specified as reference)
- When done, click “ok” to finish the first setup step.
As a second setup step, select “Assura => Run QRC” from the layout window, and match all settings as
shown below.

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- Click “ok” to run the QRC tool. The following message should be displayed afterward:

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- Your library manager will now include an av_extracted cellview for the AMPexample cell:
- Open the extracted cell view, click “shift + f” to display all layers, and zoom in to see parasitic
resistors/capacitors that have been added:

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- You can also check the values of the extracted devices. For example, after zooming into the top-left
corner of the capacitor, you can use “q” to check its properties, including the value (912fF):
- Notice that the resistor (schematic: 195Ω / 6 segments = 32.5Ω per segment) is modelled with six
series segments of 22.5Ω (poly) and 10Ω (interconnect) resistances in the extraced cellview.

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5) Post-layout simulation
a) Configuration file setup
- In the library manager, highlight the testbench for the circuit (e.g., AMPexample_TB) as shown
below and create a configuration file (“File => New => Cellview).
- Select the appropriate options in the following sequence of windows:
=>
(The second window initially contains only blank fields. Click on “Use Template” and then select
“spectre” to automatically populate the fields as shown above. Then, change the View [under
TopCell] to schematic.)

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- The following window should appear:
Note: After creating and editing new cells, you should always update the config file using the button
circled above.
- Click “File => save”.
- Right-click on the schematic field of the AMPexample cell, and select the av_extracted view:

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- The window should now appear as below. Now, the av_extracted cellview will be used for the
AMPexample cell when the AMPexample_TB schematic is simulated. Thus, the effect of the
extracted layout parasitics will become evident in the simulation results. Save the config file and
close it.
- The config file view can be found in the library manager. Select it, and then choose “File => open”
with the options displayed below, which will open the config and schematic window.

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- In the schematic cellview (AMPexample_TB), notice that when you select the AMPexample cell, and
use “Edit => Hierarchy => Descend Edit; then the av_extracted cellview will appear as default in the
top of the list:
If you want to, you can descend into the extracted view and later return with “Edit => Hierarchy =>
Return”
b) Running the post-layout simulation
- From the AMPexample_TB schematic, select “Launch => ADE L”.
- From the ADE menu, load the previously saved state (“Session => load state => cellview tab“):

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- Start the post-layout simulation with “Simulation => Netlist and Run”
o When running post-layout simulations, you can also save the data in the temporary directory:
- in ADE: “Setup => simulator/directory/host”
(If your disk quota in the simulation directory within your home directory exceeds the limit,
then Cadence might crash. You can use the /tmp/[your_account] directory to avoid that.)
- Check your plots and saved outputs. Notice that the results with the av_extracted view (below) are
different compared to the previous results from simulation of the schematic view. If the post-layout
simulation performance degradation is not acceptable, then layout has to be optimized.
- Note: You can use the config file to switch back to a simulation using the schematic cellview of
AMPexample. To do so, simple change (right-click on av_extracted view) to the schematic view in
the config file and save it afterwards: