The document describes an op-amp sample and hold circuit. The circuit uses an op-amp, FET switch, and capacitor to sample the instantaneous voltage of an input signal and hold it constant. The FET switch is turned on and off by a control voltage, charging the capacitor to the input voltage when on and holding it when off. This allows the circuit to sample the input signal at discrete time intervals and output a held voltage between samples, functioning as both a sampler and a signal holder.

1. OP-AMP SAMPLE AND
HOLD CIRCUIT

2. SAMPLE AND HOLD CIRCUITS :
 A sample-and-hold circuit samples instantaneous
amplitude of a signal voltage at any point in its
waveform and holds the voltage level constant
until the next sample is acquired.
 The sampled and hold circuit which is a modified
version of peak detector circuit , modifications are
that FET switch (Q1) is included to alternately
connect and disconnect the capacitor at the
output of amp A1.

3. SAMPLE AND HOLD CIRCUIT
+Vcc +VCC
LF353
LF353
VEE
D1 D2
V1
A1
A2
Vi
R1
1 MΩ
R1
1 MΩ
C1
Q1
2N4391
VO-VEE

4.  The waveforms illustrate the sample and hold
circuit operation.
 The FET is repeatedly switched ON and OFF
by the pulse waveform(control voltage Va )
applied to its gate terminal.
 If VC is initially greater than Vi ,C1 is
discharged to the level of Vi when FET is ON.
 When Q1 is OFF, only the input bias current
are effective in discharging the capacitor.
 So C1 holds the sampled voltage constant
until the next sampling instant.
Vi
Va
VC /V0

5. Capacitor Voltage
 During the sampling rate ,or acquisition
time,C1 is charged via the FET channel
resistance.
 If the sampling time is
t1=5 C RD(on)
the capacitor is charged to 0.993 of the
input voltage ,resulting in a 0.7% error in
the sample amplitude.
 If t1=7 C RD(on)
is used , the error will be 0.1%.
 During the holding time ,the capacitor is
partially discharged , exactly as the peak
detector circuit.
VC
∆V
t
1
t
2
Acquisition
time
Holding
time

6. IC LH0053:

7. Adavantages:
 The primary use of the sample and hold circuit to hold the sampled analog input
voltage constant during conversion time of A/D converter.
 In case of multichannel ADCs, synchronization can be achieved by sampling signals
from all channels at the same time.
 It also reduces the crosstalk in the multiplexer.
Application:
 Analog to Digital Converter Circuits (ADC)
 Digital Interface Circuits
 Operational Amplifiers
 Analog De-multiplexers
 Data distribution systems
 Storage of outputs of multiplexers
 Pulse Modulation Systems

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