This book i need fo the VLSI technology for my m.tech study

1. September 2, 2020
Vladimir Gromov
Nikhef, Amsterdam, the Netherlands
MLR1 submission (fall 2020)

2. ALPIDE65 V.Gromov 2
02/09/2020
Status : Nikhef contributions to the MLR1 submission in TJ 65nm technology (fall 2020)
Block / Requirements - System requirements
- Specification
- Topology selection
- Pre-design
Electrical
Design
(schematic)
Physical Design
(layout)
Integration
( in the test chip)
Manpower
required
Manpower
available
Bandgap Reference Circuit (BGR)
- delivers 2 reference currents with a pre-
set temperature gradient
- 3x flavours of the reference elements
(diode, PNP , DTMOST)
done
3 wks
done
3 wks
done
3 wks
in progress
9 wks FTE 9 wks FTE
( July-September)
V.Gromov
Power-Supply-Cleaning LDO for the Data
Serializer block
- should have lower sensitivity to the input
voltage fluctuation even at high
frequencies (above 1GHz)
- should NOT include external capacitance
(output-capacitorless = OCL- LDO )
done 2 wks 2 wks 2 wks 6 wks FTE
1 FTE
(September-
December)
Deepak Gajanana
Phase-locked Loop circuit
- generic block used to multiply the
frequency (40MHz → 320MHz) or
- clean (remove time jitter) in the clock
signal (320MHz → 320MHz)
done 6 wks 6 wks 2 wks 14 wks
FTE
Voltage-controlled oscillator (VCO) circuit
- generic block used in the PLL
( Fosc=640MHz )
done 2 wks
in progress
2 wks 2 wks

3. Bandgap reference circuit (BGR) with adjustable temperature gradient
ALPIDE65 V.Gromov 3
02/09/2020
 the Bandgap reference circuit consists of two independent circuits :
 Voltage bandgap reference circuit delivers currents with a pre-set temperature gradient. These currents will be converted into PVT-immune
reference voltages (LDO applications)
 Current Bandgap Reference circuit deliver currents with zero-temperature gradient. These currents can be directly used as PVT-immune
references
 the output currents are easy to distribute across the chip with no need to have a control of the voltage drop on the reference (ground) node

4. Topology of the BGR circuit
ALPIDE65 V.Gromov 4
02/09/2020
Current-summing (Banba) circuit
reference elements : EL diode / DTMOST / npn / pnp
the BGR circuit is based on previously-implemented radiation-hard designs in various technologies

5. ALPIDE65 V.Gromov 5
02/09/2020
 the value of the I_out_ref : 7.1uA ± 0.25% in the temperature range -40°C … +80°C
: ~ 0.3% deviation in the output voltage range 0V …. 0.8V
: < 0.1% deviation in the power supply voltage range 1.1V … 1.32V
lib: /icwork /vgromov/ALICE_ITS3/ITS3 cell: tb_7.sch DUT:, … , view: schematic, simulation : tt, -40C … +80C, 1.2V , transient : conservative 10us , startup pulse width : 40ns, load output voltage : 0V …800mV
TJ65nm-components-based diode-BGR
Output reference current vs output voltage Output reference current vs power supply voltage

6. ALPIDE65 V.Gromov 6
02/09/2020
Nikhef contributions to the MLR1 submission in TJ 65nm technology (fall 2020)
Bandgap Reference Circuit (BGR) : 75um x 104um
- delivers 2 reference currents with a pre-set temperature gradient
- 3x flavours of the reference elements (diode, PNP , gated-diode, DTMOST)
diode BJT_VPNP
Gated-diode DTMOST
temperature gradient adjustment block (resistors, analog switches, switch control logic)
OPAMP

7. Spare slides

8. ALPIDE65 V.Gromov 8
14/07/20
 the value of the ∆ Iload/ ∆Vdd : 4 •10-4 / mV ( AC) → worst case
10-6 /mV (DC) → best case
 significant thermal noise in the output load current: 146nA p-p → 2% p-p
lib: /icwork /vgromov/ALICE_ITS3/ITS3 cell: tb_7.sch DUT: … , view: schematic, simulation : tt, +27C, 1.2V , transient : conservative 10us , startup pulse width : 40ns, load output voltage : 500mV
TJ65nm-components-based diode-BGR
Dynamic power-supply ripple rejection Thermal noise
146nA p-p @ Inom = 7140nA

9. lib: /icwork /vgromov/ALICE_ITS3/ITS3 cell: tb_7.sch DUT: … , view: schematic, simulation : tt, +27C, 1.2V , transient : conservative 10us , startup pulse width : 40ns, load output voltage : 500mV
ALPIDE65 V.Gromov 9
13/08/20
 unity gain frequency : 12MHz
 DC loop gain : 51dB
 phase margin : 58 deg
TJ65nm-components-based diode-BGR
Analysis of the stability analysis of the loop

10. ALPIDE65 V.Gromov 10
13/08/2020
Bandgap startup situation
TRUE lock region
FALSE lock region
target operation points
DTMOST lock region
 the startup circuit provides very high currents to the reference elements to avoid the circuit operation in the NO-lock region
startup
Lock operation regions Conventional startup circuit for the BGR
reset pulse

11. Adjustability of the temperature gradient
ALPIDE65 V.Gromov 11
13/08/2020
The BGR circuit Resistor switch block
analog
switches
resistors
Switch control block

12. ALPIDE65 V.Gromov 12
13/08/2020
lib: /icwork /vgromov/ALICE_ITS3/ITS3 cell: tb_15.sch DUT: Res_2_VG.sch, view: schematic, simulation : tt, +27C, 1.2V , transient : conservative 10us , vdc voltage : 0V …1.2V
Analog switch for the resistor switch block
RON of the analog switch
 the resistance of the analog switch Ron : ~15Ω @ vdc ≈ 0V, 95Ω @ vdc ≈ 0.8V (worst case)
Roff : ~16MΩ @ vdc ≈ 0V (worst case), 4.8GΩ @ vdc ≈ 0.45V
Schematic of the analog switch

13. ALPIDE65 V.Gromov 13
13/08/2020
Top-level integration of one BGR circuit (out of four)
Schematic view
switch
control
blocks
Resistor
switch
blocks
Resistor
switch
blocks
Resistor
switch
blocks
Reference
elements
OPAMP
Symbol view
Input digital pads: 9
Output analog pad : 1
Analog input/output pads: 7
Power supply: 2
Total : 19 per one BGR circuit
 one BGR circuit requires 19 pads on the die

14. ALPIDE65 V.Gromov 14
13/08/2020
DIODE-like reference elements in TJ 65nm technology
I-V characteristics @ tt, 25°C
target operation region
diode :
3.3V P+ @ NWELL
VPNP Bipolar
transistor :
3.3V P+ @ NWELL
Gated diode (radiation torerant topology)
- NO thick FOX between N+ / P+ contacts
- the gate is connected to VDD
GOX
GOX
Gated diode :
1.2V P+ @ NWELL (PMOS)
 all the three device have exponential I-V characterictic in the operation region (0.65V / 0.3uA … 0.73V / 3uA)

15. ALPIDE65 V.Gromov 15
13/08/2020
Dynamic Threshold MOS device (DTMOST) as reference elements in TJ 65nm technology
 the DTMOST device has exponential I-V characterictic in the operation region (0.125V / 0.3uA … 0.29V / 3uA)
I-V characteristic @ tt, 25C
DTMOS device:
1.2V P+ @ NWELL (PMOS)
DTMOST (radiation torerant topology)
- NO thick FOX between N+ / P+ contacts
- the gate is connected to GND
target operation region
GOX
GOX