This document summarizes research on a dual-channel ferroelectric-gate field-effect transistor fabricated with gallium indium zinc oxide and poly[(vinylidenefluoride-co-trifluoroethylene]. The transistor has top and bottom gates that allow control of two channels. Experiments showed the bottom gate bias could dynamically modulate the onset voltage, enabling enhancement mode operation. This has benefits for memory retention and reducing dipole switching speeds. Dual-gate operation also allowed arbitrary control of the onset voltage location, aiding longer retention times.

1. IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE)
e-ISSN: 2278-1676,p-ISSN: 2320-3331, Volume 7, Issue 5 (Sep. - Oct. 2013), PP 44-47
www.iosrjournals.org
www.iosrjournals.org 44 | Page
GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate field-
effect transistor: influence on memory retention and switching
mechanisms
Ali Nawaz, Tayyab Rasul
(Department of Information Technology, Faculty of Electronics/ Mid Sweden University, Sundsvall, Sweden)
Abstract: A non-volatile memory ferroelectric-gate field-effect transistor (FeFET), fabricated with à dual (top
and bottom) channel is demonstrated. This transistor consists entirely of the following thin films: Heavily doped
Silicon (Si n++) substrate with thermally grown silicon dioxide (SiO2) (bottom gate electrode);
poly[(vinylidenefluoride-co-trifluoroethylene] (P(VDF-TrFE)) (ferroelectric) and gallium indium zinc oxide
(GIZO) (semiconductor). The channel conductance of the transistor was controlled by varying the bottom gate
bias, while keeping the top gate bias constant. In both cases (positive & negative bottom gate bias), memory
device acted as an n-type transistor. After the appliance of a sufficiently positive bias to the bottom gate, a
channel is formed on the bottom of gallium indium zinc oxide (GIZO) and an additional channel is also formed
on the top of gallium indium zinc oxide (GIZO), controlled by the top gate, hence creating a dual channel
ferroelectric-gate field-effect transistor (FeFET) operation. Experiments using dual (top & bottom) gates were
performed essentially to investigate the chances of enhancing 1) the dipole switching/programming speed to a
practical level, and 2) the retention behavior of the memory transistor by controlling the onset voltage.
Keywords : Dual-gate, Ferroelectric, field-effect, GIZO, memory, non-volatile, P(VDF-TrFE), semiconductor,
thin film, transistor
I. Introduction
Concerning non-volatile memory applications, a ferroelectric-gate field-effect transistor (FeFET)
comprising of dielectric layer being a ferroelectric material, is considered to be of great interest, since only with
low power consumption, its channel conductance can be memorized and switched at a considerably high speed
[1, 2]. For a memory transistor to perform at its best and provide optimal results, enhancement mode (positive
onset voltage (VON)) operations have to be achieved, as in depletion mode (negative VON) operations, unwanted
current components at VGS = 0 V from unselected cell cause difficulties in designing peripheral driving circuitry
for a memory device. The two most critical downsides associated with using an oxide semiconducting layer
combined with an organic ferroelectric layer include the depletion mode (negative VON) operations and a slow
programming speed. This paper deals solely with the possibilities of enhancing the programming speeds and
retention times using VON controllability of P(VDF-TrFE)/GIZO based dual-gate (DG) organic memory
transistors.
II. Device Structure and Experimental Procedure
Fig. 1 shows a schematic cross section of DG FeFET. The transistor was fabricated by spin coating
Poly[(vinylidenefluoride-co-trifluoroethylene] (P(VDF-TrFE)) on top of Gallium Indium Zinc Oxide (GIZO)
semiconductor at a speed of 2000 rpm. It was later soft baked at 65ºC for 5 min. To improve crystallinity,
P(VDF-TrFE) was annealed for 3 min at 135°C in air. Thickness measurements for P(VDF-TrFE) were
performed using Dektak Profilometer. GIZO deposition was conducted by means of sputter deposition using the
Radio Frequency (RF) Sputtering Technique. GIZO was also annealed at 150ºC in air, for 2 min. GIZO layer
thickness was measured as 20 nm, whereas the ferroelectric layer’s thickness was measured as 190 nm. Bottom
contact was fabricated on a heavily doped Si substrate (Si n++), with thermally grown silicon dioxide (SiO2)
(140 nm). The source, drain and top-gate electrodes (30 nm), were patterned using photolithography. The source
and drain electrodes were made of gold (Au), whereas a gold (Au) top-gate electrode was thermally evaporated
at 0.5 nm/s in a vacuum of 10-6
torr through a shadow mask using an Edward Evaporator E306. Length and
width of the channel were measured as 20µm and 5mm respectively.

2. GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate field-effect transistor: influence on
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Fig. 1: schematic of dual (top & bottom) gate FeFET.
Sufficiently large positive bias to the bottom gate results in the formation of a channel at the bottom of
GIZO. Similarly, an additional channel is also formed on top of GIZO, controlled by the top gate, hence creating
a dual channel FeFET operation. FeFET memory transistor was observed to act as an n-type transistor, and
especially in case of negative bottom gate bias, the device displays a somewhat more traditional transistor (with
no bottom gate bias) like behavior providing an On-Off current ratio of ~105
, which is sufficient for memory
operations [3].
Measurements were performed on the transistor by sweeping the top gate bias (VGSt) from -17V to 17V
while first varying the bottom gate bias (VGSb) from -15V to -90V, and then from +15V to +90V. Drain-current
top-gate voltage (IDS-VGSt) characteristics were subsequently observed in both cases. Drain-source bias (VDS)
and Source-drain bias (VSD) were kept constant at 0.05 V and 0 V respectively.
Above mentioned experiments were performed inside a glove box with nitrogen (N2) environment
using Cascade Microtech M150 Probe station, Agilent 4155C Semiconductor Parameter Analyzer and Keithley
2612 Source meter.
III. Results and Discussion
Fig. 2 shows drain-current top-gate voltage (IDS-VGSt) characteristics when bottom gate bias (VGSb) is
varied using positive and negative voltages.
With the appliance of positive VGSb to bottom gate electrode, high conductivity was exhibited because
of electron accumulation due to upward polarization at interface between GIZO and P(VDF-TrFE). On the other
hand, low conductivity (because of electron depletion from GIZO) was exhibited when a negative VGSb was
applied owing downward ferroelectric polarization. Correspondingly, with the removal of bottom gate voltage,
conductance was retained, owing to the non-volatile nature of ferroelectric polarization. It was observed that
saturated ON current for VGSb = +90 V is higher than that for VGSb = -90 V (Fig. 3) [3]. Increase in conductance
as a result of positive VGSb is very beneficial as it can be used to obtain reduced programming speeds [4].
In case of negative bottom gate bias (VGSb), the bottom gate is in an OFF state and hence no current
flows through the bottom channel. The IDS-VGSt curve in Fig. 2(a) shows top-gate FeFET characteristics and a
polarization caused by the ferroelectric layer is observed. When a positive VGSb is applied, the bottom gate is in
the ON state and even when the VGSt is negative, high drain currents are observed because of the positive bottom
gate bias. In Fig. 2(b), it can be observed that with the appliance of VGSb of +90 V, the drain current retains the
same value of the current flowing through the bottom channel, regardless of the top gate bias. An interesting
characteristic to be noted in this case is that the width of memory window and the threshold voltage (VTH) of
VGSb = +90 V and VGSb = -90 V are almost the same, which means that while retaining the ON or OFF state of
the bottom channel, the top channel conductance can be switched with no VTH shift. In other words, the bottom
gate bias caused no effect to the ferroelectric polarization.
(a)

3. GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate field-effect transistor: influence on
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Fig. 2: IDS-VGSt characteristics of FeFET when VGSt was swept from -20V to 20V and the fixed bias VGSb was
changed (a) from -15V to -90V and (b) from +15V to +90V.
The most interesting and expected behavior of DG transistor noted here is the arbitrary control of VON
location. Fig. 2(a) and (b) show the variations in IDS-VGSt characteristics when the fixed bias condition of VGSb
was changed from -15 V to -90 V and from 15 V to 90 V respectively. VON of FeFET was dynamically
modulated to -4.24, -2.23, -0.23, 1.72, 2.97 and 3.72 V when the fixed VGSb was set to -15, -30, -45, -60, -75 and
-90 V. It is noticeable that positive VON values obtained at negative VGSb of less than -60 V are expectedly
favorable for the FeFET because the retention and readout operations can then easily be carried out at a VGSt of
0 V, and the FeFET does not possess a current flow in its stand-by state.
Fig. 3: Drain current-top gate voltage (IDS-VGSt) characteristics when bottom gate bias (VGSb) is -90V and +90V.
This situation holds much significance since it is desirable for memory window of DG FeFET to be
positioned with its center around VGSt of 0 V, which in turn is very beneficial for attaining longer retention times
for the programmed data [5].
The width of the memory window for all the bottom gate biases was noted to be the same [6]. A sub
threshold swing was also observed (Fig. 2(a)), when VGSb was changed from -15 V to -90 V. It is known as the
back-gate effect, which corresponds to the control of VTH shift value using dual gates. In order to develop a
better understanding of how this mechanism is affecting memory functionality, further experiments such as
simulations and temperature-dependent measurements are required [3].
A shift in VON with a decrease in VGSb is illustrated in Fig. 4 and Table 1.
Fig. 4: Bottom Gate Bias (VGSb) vs. Turn-on Voltage (VON).
(b)

4. GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate field-effect transistor: influence on
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Table 1: Values of VON for VGSb ranging from -15 V to -90 V.
VGSb (V) - 15 - 30 - 45 - 60 - 75 - 90
VON (V) - 4.24 - 2.23 - 0.23 1.72 2.97 3.72
IV. Conclusion
A non-volatile P(VDF-TrFE)/GIZO based organic memory device has been demonstrated to solve
some technical issues including the dynamic control of VON effecting dipole switching speeds and retention
times. With the increase of VGSb, an onset voltage shift was observed and the device was witnessed to enter
enhancement mode (positive VON) from the depletion mode (negative VON). It can be concluded that dual-gate
FeFET operations can be helpful in controlling the onset voltage and hence operate memory device in
enhancement mode (positive VON), therefore ensuring a low-power, stable retention behavior and longer
retention times.
Similarly, these measurements also open the possibilities of reducing dipole switching speeds of
FeFET. An increase in conductance as a result of dual-gate usage contributes to a reduction of switching events.
This feature can hence be beneficial in achieving low power and high performance for organic FeFETs.
Acknowledgments
Funding for the research work came from the European Community’s Seventh Framework Programme
(FP7/2007-2013) of the MOMA project.
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