This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Application of Variable Inductors in a DC/DC Converter to Increase the Operat...theijes
Maximum power transfer in solar micro-grid applications is achieved by impedance matching with a dc–dc converter with maximum power point tracking by the incremental conductance method. Cuk dc to dc converters because of the increase and decrease voltage capability is an important and two inductors in the input and output decrease current ripple significantly. This paper describes how to use non-linear inductors in Cuk converter and designs values of capacitors properly. Because of the Cuk converter uses two inductors, use of variable inductors has great value and reduce the size and cost of inductors and increases the operating range of the tracker to recover solar energy at low solar levels. In other words, the range of operation is extended for low light levels or partially shaded solar panels. The MPPT controller with a variable inductance is robust and reliable over the full operating range. The validity of the proposed converter is verified with computer simulations using PSCAD/EMTDC.a
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Application of Variable Inductors in a DC/DC Converter to Increase the Operat...theijes
Maximum power transfer in solar micro-grid applications is achieved by impedance matching with a dc–dc converter with maximum power point tracking by the incremental conductance method. Cuk dc to dc converters because of the increase and decrease voltage capability is an important and two inductors in the input and output decrease current ripple significantly. This paper describes how to use non-linear inductors in Cuk converter and designs values of capacitors properly. Because of the Cuk converter uses two inductors, use of variable inductors has great value and reduce the size and cost of inductors and increases the operating range of the tracker to recover solar energy at low solar levels. In other words, the range of operation is extended for low light levels or partially shaded solar panels. The MPPT controller with a variable inductance is robust and reliable over the full operating range. The validity of the proposed converter is verified with computer simulations using PSCAD/EMTDC.a
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Modeling and Simulation of a Carrier-based PWM Voltage Source Inverter for a ...IAES-IJPEDS
The analysis of a carrier-based PWM two level voltage source inverter for a nine phase induction machine drive system is presented in this paper. Methods for generating zero-sequence signals during balanced and unbalanced condition are established. Simulation results for the analysis are presented. Two fault conditions involving the voltage source inverter and the nine-phase squirrel cage induction machine load are investigated. For the two fault scenarios considered, the effects on the performance characteristics of the induction machine load are highlighted. The simulation results obtained show that the two imbalance conditions considered result in substantial oscillations on the electromagnetic torque of the machine with attendant reduction in the torque rating. There is also large slip in the rotor speed.
A Novel Topology of Multilevel Inverter with Reduced Number of Switches and D...IAES-IJPEDS
This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Simulation and dSPACE Based Implementation of Various PWM Strategies for a Ne...IJPEDS-IAES
Depending on the number of levels in output voltage, inverters can be
divided into two categories: two level inverter and Multi Level Inverters
(MLIs). An inverter topology for high voltage and high power applications
that seems to be gaining interest is the MLI. In high power and high voltage
applications, the two level inverters have some limitations in operating at
high frequency mainly due to switching losses and constraints of device
rating.In this paper, a three phase H + type FCMLI (Flying Capacitor MLI)
using sinusoidal reference, third harmonic injection reference, 60 degree
reference and stepped wave reference are initially developed using
SIMULINK and then implemented in real time environment using dSPACE.
In H-type FCMLI with R-load it is inferred that bipolar COPWM-C
provides output with relatively low distortion for 60 degree reference
and bipolar COPWM-C strategy is found to perform better since it
provides relatively higher fundamental RMS output voltage for THI
reference. The five level output voltages of the chosen MLIs obtained using
the MATLAB and dSPACE based PWM (Pulse Width Modulation)
strategies and the corresponding %THD (Total Harmonic Distortion), VRMS
(fundamental), CF (Crest Factor) and FF (Form Factor) are presented and
analyzed.
Modelling and Simulation of a Sensorless Control of a True Asymmetric Cascade...IJPEDS-IAES
This paper introduces a new method to track the saliency of an AC motor fed
by a multilevel converter through measuring the dynamic current response of
the motor line currents due the IGBT switching actions. The method uses
only the fundamental PWM waveform (i.e there is no modification to the
operation of the multilevel converter) similar to the fundamental PWM
method proposed for a 2-level converter. Simulation results are provided to
demonstrate the performance of the complete sensorless speed control of a
PM motor driven by such a converter over a wide speed range. Finally the
paper introduces a comparison between the 2-level converter and the
multilevel converter in terms of the reduction of the total harmonic distortion
(THD) using the fundamental PWM method in both cases.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Soft Computing Technique for the Control of Triple-Lift Luo ConverterIJERA Editor
Positive output Luo converters are a series of new DC-DC step-up (boost) converters, which were developed from prototypes using voltage lift technique. These converters perform positive to positive DC-DC voltage increasing conversion with high power density, high efficiency and cheap topology in simple structure. They are different from other existing DC-DC step-up converters with a high output voltage and small ripples. Triple lift LUO circuit is derived from positive output elementary Luo converter by adding the lift circuit three times. Due to the time varying and switching nature of the Luo converters, their dynamic behaviour becomes highly nonlinear. The classical control methods employed to design the controllers for Luo converters depend on the operating point so that it is very difficult to select control parameters because of the presence of parasitic elements, time varying loads and variable supply voltages. Conventional controllers require a good knowledge of the system and accurate tuning in order to obtain the desired performances. A fuzzy logic controller is a soft computing technique which neither requires a precise mathematical model of the system nor complex computations. The performances of the Triple-lift Luo converter with fuzzy logic controller are evaluated under line and load disturbances using Matlab-Simulink based simulation. The results are presented and analyzed.
Design of matched filter for radar applicationselelijjournal
The aim of this paper is to present the details of signal processing techniques in Military RADARS . These
techniques are strongly based on mathematics and specially on stochastic processes. Detecting a target in
a noisy environment is a many folds sequential process. The signal processing chain only provides to the
overall system boolean indicators stating the presence (or not) of targets inside the coverage area. It is
part of the strategical operation of the radar. This paper mainly focuses on Design of Matched filter and
generation of chirp Signal.
OPTIMAL TORQUE RIPPLE CONTROL OF ASYNCHRONOUS DRIVE USING INTELLIGENT CONTROL...elelijjournal
The dynamic performance of an asynchronous machine when operated with cascaded Voltage Source Inverter using Space Vector Modulation (SVM) technique is presented in this paper. A classical model of Induction Motor Drive based on Direct Torque Control (DTC) method is considered which displays
appreciable run-time operation with very simple hysteresis control scheme. Direct control of the torque and flux variables is achieved by choosing suitable inverter voltage space vector from a lookup table. Under varying torque conditions the performance of the drive system is verified using MATLAB/Simulink software tool. The ripple content in the torque parameter is significant when traditional PI controller and Fuzzy approach are configured in the proposed system. Finally, by replacing the PI-Fuzzy controller with Hybrid Controller the torque ripple minimization can be achieved during no-load and loaded conditions.
Modeling and Simulation of a Carrier-based PWM Voltage Source Inverter for a ...IAES-IJPEDS
The analysis of a carrier-based PWM two level voltage source inverter for a nine phase induction machine drive system is presented in this paper. Methods for generating zero-sequence signals during balanced and unbalanced condition are established. Simulation results for the analysis are presented. Two fault conditions involving the voltage source inverter and the nine-phase squirrel cage induction machine load are investigated. For the two fault scenarios considered, the effects on the performance characteristics of the induction machine load are highlighted. The simulation results obtained show that the two imbalance conditions considered result in substantial oscillations on the electromagnetic torque of the machine with attendant reduction in the torque rating. There is also large slip in the rotor speed.
A Novel Topology of Multilevel Inverter with Reduced Number of Switches and D...IAES-IJPEDS
This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Simulation and dSPACE Based Implementation of Various PWM Strategies for a Ne...IJPEDS-IAES
Depending on the number of levels in output voltage, inverters can be
divided into two categories: two level inverter and Multi Level Inverters
(MLIs). An inverter topology for high voltage and high power applications
that seems to be gaining interest is the MLI. In high power and high voltage
applications, the two level inverters have some limitations in operating at
high frequency mainly due to switching losses and constraints of device
rating.In this paper, a three phase H + type FCMLI (Flying Capacitor MLI)
using sinusoidal reference, third harmonic injection reference, 60 degree
reference and stepped wave reference are initially developed using
SIMULINK and then implemented in real time environment using dSPACE.
In H-type FCMLI with R-load it is inferred that bipolar COPWM-C
provides output with relatively low distortion for 60 degree reference
and bipolar COPWM-C strategy is found to perform better since it
provides relatively higher fundamental RMS output voltage for THI
reference. The five level output voltages of the chosen MLIs obtained using
the MATLAB and dSPACE based PWM (Pulse Width Modulation)
strategies and the corresponding %THD (Total Harmonic Distortion), VRMS
(fundamental), CF (Crest Factor) and FF (Form Factor) are presented and
analyzed.
Modelling and Simulation of a Sensorless Control of a True Asymmetric Cascade...IJPEDS-IAES
This paper introduces a new method to track the saliency of an AC motor fed
by a multilevel converter through measuring the dynamic current response of
the motor line currents due the IGBT switching actions. The method uses
only the fundamental PWM waveform (i.e there is no modification to the
operation of the multilevel converter) similar to the fundamental PWM
method proposed for a 2-level converter. Simulation results are provided to
demonstrate the performance of the complete sensorless speed control of a
PM motor driven by such a converter over a wide speed range. Finally the
paper introduces a comparison between the 2-level converter and the
multilevel converter in terms of the reduction of the total harmonic distortion
(THD) using the fundamental PWM method in both cases.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Soft Computing Technique for the Control of Triple-Lift Luo ConverterIJERA Editor
Positive output Luo converters are a series of new DC-DC step-up (boost) converters, which were developed from prototypes using voltage lift technique. These converters perform positive to positive DC-DC voltage increasing conversion with high power density, high efficiency and cheap topology in simple structure. They are different from other existing DC-DC step-up converters with a high output voltage and small ripples. Triple lift LUO circuit is derived from positive output elementary Luo converter by adding the lift circuit three times. Due to the time varying and switching nature of the Luo converters, their dynamic behaviour becomes highly nonlinear. The classical control methods employed to design the controllers for Luo converters depend on the operating point so that it is very difficult to select control parameters because of the presence of parasitic elements, time varying loads and variable supply voltages. Conventional controllers require a good knowledge of the system and accurate tuning in order to obtain the desired performances. A fuzzy logic controller is a soft computing technique which neither requires a precise mathematical model of the system nor complex computations. The performances of the Triple-lift Luo converter with fuzzy logic controller are evaluated under line and load disturbances using Matlab-Simulink based simulation. The results are presented and analyzed.
Design of matched filter for radar applicationselelijjournal
The aim of this paper is to present the details of signal processing techniques in Military RADARS . These
techniques are strongly based on mathematics and specially on stochastic processes. Detecting a target in
a noisy environment is a many folds sequential process. The signal processing chain only provides to the
overall system boolean indicators stating the presence (or not) of targets inside the coverage area. It is
part of the strategical operation of the radar. This paper mainly focuses on Design of Matched filter and
generation of chirp Signal.
OPTIMAL TORQUE RIPPLE CONTROL OF ASYNCHRONOUS DRIVE USING INTELLIGENT CONTROL...elelijjournal
The dynamic performance of an asynchronous machine when operated with cascaded Voltage Source Inverter using Space Vector Modulation (SVM) technique is presented in this paper. A classical model of Induction Motor Drive based on Direct Torque Control (DTC) method is considered which displays
appreciable run-time operation with very simple hysteresis control scheme. Direct control of the torque and flux variables is achieved by choosing suitable inverter voltage space vector from a lookup table. Under varying torque conditions the performance of the drive system is verified using MATLAB/Simulink software tool. The ripple content in the torque parameter is significant when traditional PI controller and Fuzzy approach are configured in the proposed system. Finally, by replacing the PI-Fuzzy controller with Hybrid Controller the torque ripple minimization can be achieved during no-load and loaded conditions.
Under voltage load shedding for contingency analysis to optimize power loss ...elelijjournal
Power system contingency is a condition of operation which may be caused due to line outage in a system
and could lead to entire system voltage instability. This may further result in voltage collapse leading to total blackout of the system. Therefore, voltage collapse prediction and estimating voltage stability margin
is an important task in power system operation and planning. In this paper Line Stability Index Lij utilizing
the concept of power flow in a single line is adopted to determine the condition of voltage instability. The
purpose of Lij is to determine the point of voltage instability, the weakest bus in the system and the critical
line referred to a bus. Analytical approach based technique for load shedding has been developed as a solution for secured operation of power system under various contingency conditions to optimize the power
flow in order to minimize the system losses within acceptable limit. To validate the effectiveness of the
proposed method simulation has been carried out on IEEE 14 bus system.
EFFICIENT MULTIPLIERS FOR 1-OUT-OF-3 BINARY SIGNED-DIGIT NUMBER SYSTEMelelijjournal
This paper proposes new multipliers based on Binary Signed-Digit (BSD) operands. BSD number system has carry free capability in addition operation which causes high speed multiplication. In order to use the numbering system, BSD operand needs to be encoded into binary bits. 1-out-of-3 BSD encoding has been proposed as a subset of m-out-of-n codes which can be used for error detection and correction. However, a multiplier for 1-out-of-3 encoding has not yet been reported in the literature. In this paper, we propose
three different structures for 1-out-of-3 BSD multiplication for the first time to achieve an appropriate trade-off between area, delay, and power parameters. Our target implementation platform is Application Specific Circuits (ASIC).
NOVEL PSO STRATEGY FOR TRANSMISSION CONGESTION MANAGEMENTelelijjournal
In post deregulated era of power system load characteristics become more erratic. Unplanned transactions
of electrical power through transmission lines of particular path may occur due to low cost offered by
generating companies. As a consequence those lines driven close to their operating limits and becomes
congested as the lines are originally designed for traditional vertically integrated structure of power
system. This congestion in transmission lines is unpredictable with deterministic load flow strategy.
Rescheduling active and reactive power output of generators is the promising way to manage congestion.
In this paper Particle Swarm Optimization (PSO) with varying inertia weight strategy, with two variants
e1-PSO and e-2 PSO is applied for optimal solution of active and reactive power rescheduling for
managing congestion. The generators sensitivity technique is opted for identifying participating generators
for managing congestion. Proposed algorithm is tested on IEEE 30 bus system. Comparison is made
between results obtained from proposed techniques to that of results reported in previous literature.
Electro-Mechanical Batteries for low earth orbit satellite with hallow cylind...elelijjournal
Electromechanical batteries overcome many problems that may occur when chemical batteries in low orbit satellites (LEO) , In such a configuration of motor generator mode coupling with flywheel is used to store kinetic energy in motor mode through the flywheel during sunlight and supply electrical power from the stored kinetic energy by generator mode.In this paper design of design of Permanent magnet synchronous machine (PMSM) using hollow cylindrical flywheel for motor generator mode have been done.Flywheel dimensions and material selection are presented in the paper to achieve optimum weight with the required supplied power.
Fea of pcb multilayer stack up high voltage planar transformer for aerospace...elelijjournal
High voltage planar transformer is a technology which can replace conventional transformer with its distinct advantages of saturation and cost efficiency. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer
stack up of PCB Cu-tracks, producing High voltage power supply for aerospace application.With finite element analysis (FEA) simulations, different simulation outcomes are discussed for inspecting flux intensity and current density distribution with computing Electric field strength
and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines for
multilayer PCB stack up are discussed in this paper.
MATHEMATICAL MODELING OF MAHESHWAR HYDRO-ELECTRIC PLANT AT NARMADA RIVERelelijjournal
Economic hydropower plant generation scheduling is an important feature from the utility point of view,
this scheduling is more important in that case when the plants are at the same river stream & owned by the
different utilities. Various Conventional & Artificial intelligence methods have been used earlier for the
hydro generation scheduling reported through researches and more, all are of them required the
mathematical modeling of each & every hydro power plant.
Theoretical account of problem solving in general and especially methodology to develop the mathematical
models of the hydroelectric power plants has been described in this paper. Reservoir elevation model, tail
race elevation model and hydro turbine model have been developed for Rani Avanti Bai Sagar river bed
hydroelectric power plants by collating actual plant data from competent authorities. Modeling of canal
head hydroelectric power plants have been also included in this paper. This hydro power project is a part
of cascade scheme at Narmada River in Madhya Pradesh, India.
techTransmission usage and cost allocation using shapley value and tracing me...elelijjournal
In the deregulated power system, transmission pricing has become a very important task because it is necessary to develop an efficient, feasible and reliable pricing scheme that can generate the useful economic signals to network users such as generating companies, transmission companies, distribution companies and customers. The objective of this paper is to compare transmission usage and cost allocation scheme to loads (and/or generators) based on Shapley value method and power flow tracing method.Modified Kirchhoff matrix is used for power flow tracing. A comparison is done between the both methods.
A case study based on sample 6 bus power system is applied to check the feasibility and reliability of the proposed usage and cost allocation methodology.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Design and implementation of pll frequency synthesizer using pe3336 ic for ir...elelijjournal
The design and experimental verification of a low phase noise phase locked loop (PLL) frequency synthesizer using Peregrine’s PE83336 IC is presented. This PLL is used as frequency synthesizer which generates stable and low phase noise signal for space applications. A stable reference frequency of 22.8MHz is provided to the PLL through a temperature compensated crystal oscillator (TCXO). Experimental results of the PLL frequency synthesizer shows the excellent performance achieved at Xband. The PLL model implemented with frequency resolution of 5.8MHz, and phase noise better than -
81dBc/Hz @ 1 kHz offset at X-band. The complete model is fabricated on RT-duroid 6010 substrate
Design of up converter at 2.4GHz using Analog VLSI with 22nm Technologyijsrd.com
Up converter has been designed in 0.18μm technology at 2.4GHz Frequency. I am trying to design up converter with 22nm technology. The problems related to Up converter is often difficult to solve, and may allow different solutions, so the choice is not always simple for those engineers and professionals who are not trained in Analog VLSI. The optimal solution of Problem of Power dissipation is usually a mix of solutions for a specific situation. In such a situation, it is necessary to identify that problem and propose different solutions. Initially the thesis gives a basic idea of up converter and also about CMOS. Later on it tries to simulate the basic gates. And a detailed insight is provided with the help of a simulation using Tspice Simulator. Power Dissipation in 0.18μm Technology using current mirror gilbert mixer is 4.5 mW and in 0.25μm Technology using current mirror gilbert mixer is 3.5mW and Power Dissipation in 0.18μm Technology is 8.1mW using Gilbert mixer. Now I am trying to design mixer with low power dissipation with 22nm technology which is recent technology.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
energy conversion systems and electric drives. Both these systems are based
on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs)
and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
makes the PWM inverter more efficient.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCILLATOR
1. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
DOI : 10.14810/elelij.2016.5204 37
APPLICATIONS OF FLOATING-GATE MOSFET IN
THE DESIGN OF INVERTER AND RING OSCILLATOR
Roshani Gupta, Rockey Gupta and Susheel Sharma
Department of Physics and Electronics, University of Jammu, Jammu-180006, India
ABSTRACT
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
KEYWORDS
Floating-gate MOSFET, inverter, voltage transfer characteristics, propagation delay, energy delay product,
ring oscillator
1. INTRODUCTION
The design of digital integrated circuits with very low power consumption and without much
degradation in speed has always been the focal point of researchers particularly in sub-micron
regime [1-3]. Since there is always a trade-off between power dissipation and time delay,
therefore, reducing the power dissipation and still maintaining the appreciable performance in
terms of operating speed is much desirable. With the immense demand of portable and battery
driven applications, there is a need for new and alternative circuit design techniques to implement
high performance and low power digital circuits. Further, with reducing feature size of devices,
the lowering of operating supply voltage is obvious but at the expense of speed. Hence, for
optimum performance of digital circuits, alternative design techniques should be explored [4-6].
CMOS inverter forms a basic building block of digital sub-circuits in mixed mode circuits with
limitation of high switching threshold voltage resulting in degraded performance. Floating-gate
MOSFET (FGMOS) has been widely used in the design of low voltage analog and digital circuits
due to its unique characteristic of threshold voltage tuning with a bias voltage, thus imparting
enhancement in performance. In this paper, we have employed floating-gate MOSFET (FGMOS)
to design an inverter which has been further used to implement a ring oscillator. The paper has
been divided in various sections briefly introducing FGMOS, its application in the design of
inverter and ring oscillator. The performance of the designed circuits has been found to be
enhanced vis-à-vis their conventional CMOS versions. The workability of these circuits has been
2. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
38
verified through PSpice simulations carried out using level 7 parameters in 0.13 µm CMOS
technology with a supply voltage of 1 V.
2. FLOATING-GATE MOS TRANSISTOR
The Floating-Gate MOS transistor (FGMOS) is basically a modified form of simple MOSFET
where extra capacitances have been introduced between the conventional gate and the multi-input
signal gates. By applying a bias voltage on one of the input gates, the threshold voltage of
FGMOS can be reduced. A number of secondary gates or input terminals are deposited above the
floating-gate (FG) which are electrically isolated from it but capacitively connected to it. Since
FG is completely surrounded by highly resistive material, so for dc operation, FG acts as floating
node. Programming of the FGMOS introduces a charge on its floating-gate that shifts the
threshold voltage and thus, provides a control over the device functionality [7-10]. The equivalent
schematic for an N-input and n-channel FGMOS is shown in Fig. 1 [11].
Figure 1. Floating-gate MOSFET
In a two-input n-channel FGMOS, input voltage (Vin) is applied through C1 and bias voltage
(Vbias) is applied through C2 which provides tunability to the conventional threshold voltage (VT)
of the FGMOS and VT adjusts to a new value VT,eff given as [12]:
1
2
,
k
kVV
V biasT
effT
−
= (1)
where
TC
C
k 1
1 = and
TC
C
k 2
2 = and C1 and C2 are the capacitances between floating-gate and
control gates and GBGDGST CCCCCC ++++= 21 . We observe that VT,eff will be less than VT if we
select Vbias > VT and k2 >k1, implying C2>C1. Thus, in FGMOS we can select VT,eff lower than
normal VT.
Now, by selecting W/L of FGMOS as 1.3µm/0.13µm and with supply voltage of 1V, the drain
and transfer characteristics are shown in Figs. 2 and 3 respectively.
3. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
39
Figure 2. Drain characteristics of n-channel FGMOS
Figure 3. Transfer characteristics of n-channel FGMOS
It has been observed that as we increase Vbias from 0.3V to 0.6V, effective threshold voltage
(VT,eff) of n-channel FGMOS decreases from 0.8V to 0.2V at a reference drain current of 20 µA.
Similarly, the drain and transfer characteristics for p-channel FGMOS show bias dependent
behaviour. Thus, the performance of n-channel and p-channel FGMOS can be varied by
optimum selection of their respective Vbias and making FGMOS based digital circuits suitable
for low voltage and low power applications.
3. FGMOS INVERTER
The architecture of the FGMOS inverter has been obtained from the conventional CMOS inverter
as shown in Fig. 4 [13]. The bias voltages Vbp and Vbn provide tunability to the threshold voltages
of M1 and M2 respectively. It is, therefore, expected that by varying the bias voltages, the
threshold voltage of the FGMOS inverter can be changed.
0
20
40
60
80
100
120
0 0.2 0.4 0.6 0.8 1
IDS(µA)
VDS (Volts)
Vin = 0V Vin = 0.2V
Vin = 0.4V Vin = 0.6V
Vin = 0.8V Vin = 1V
0
25
50
75
100
125
150
175
200
0 0.2 0.4 0.6 0.8 1
IDS(µA)
Vin (Volts)
Vbias= 0.3V
Vbias= 0.4V
Vbias= 0.5V
Vbias= 0.6V
4. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
40
Figure 4. FGMOS inverter
The performance of FGMOS inverter can be characterized through its voltage transfer
characteristics (VTC) which is a plot of Vout as a function of Vin. From these characteristics we can
calculate parameters like switching threshold voltage and noise margins to ascertain the dc
performance of these circuits. The switching threshold voltage (VS) is defined as the input voltage
that gives an identical output voltage and it can be obtained from the intersection of the VTC
curve and the plot of Vout = Vin [13, 14]. The voltage noise margins can be obtained as NMH = VOH
- VS and NML = VS - VOL, where VOH and VOL are logic-high and logic-low output voltages of
inverter respectively. Since noise margins NMH and NML account for the sensitivity of a gate to
noise, therefore large value of this parameter is desired that makes the gate less sensitive to noisy
environment [15].
The switching threshold voltage for FGMOS inverter is given by [14]:
p
n
1
2
p
n
1
2
1
β
β
β
β
+
−
+
−
−
=
k
kVV
k
kVV
V
V
bnTnbpTp
DD
S
(2)
where
=
L
W
Cn
n
oxµβn
and
=
L
W
Cp
p
oxµβ p
are transconductance parameters of n and p-
channel FGMOS.
Now, the circuit of FGMOS inverter has been simulated to obtain the voltage transfer
characteristics (VTC) at different values of Vbp and Vbn by selecting W/L of M1 as 26 µm/0.13 µm
and M2 as 13 µm/0.13 µm with a supply voltage of 1 V as shown in Figs. 5 and 6 respectively.
5. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
41
Figure 5. VTC of FGMOS inverter at different Vbp
Figure 6. VTC of FGMOS inverter at different Vbn
From Figs. 5 and 6, the calculated values of the switching threshold voltage (VS) and
noise margins NMH and NML at different values of Vbp and Vbn are given in table 1.
Table 1. Noise margins at different Vbp and Vbn
As observed in table 1, when bias voltage of p-channel FGMOS (Vbp) is varied from 0 V to 1 V at
constant bias voltage of n-channel FGMOS (Vbn = 1V), the switching threshold voltage (VS) and
low noise margin (NML) of FGMOS inverter decreases from 0.40 V to 0.21 V but high noise
Vbn = 1 V fixed Vbp = 0 V fixed
Vbp
(Volts)
VS
(Volts)
NMH
(Volts)
NML
(Volts)
Vbn
(Volts)
VS
(Volts)
NMH
(Volts)
NML
(Volts)
0 0.40 0.60 0.40 0 0.68 0.32 0.68
0.2 0.37 0.63 0.37 0.2 0.63 0.37 0.63
0.4 0.33 0.67 0.33 0.4 0.57 0.43 0.57
0.6 0.29 0.71 0.29 0.6 0.52 0.48 0.52
0.8 0.25 0.75 0.25 0.8 0.46 0.54 0.46
1 0.21 0.79 0.21 1 0.40 0.60 0.40
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1
Vout(Volts)
Vin (Volts)
Vbp = 0V
Vbp = 0.2V
Vbp = 0.4V
Vbp = 0.6V
Vbp = 0.8V
Vbp = 1V
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1
Vout(Volts)
Vin (Volts)
Vbn = 0V
Vbn = 0.2V
Vbn = 0.4V
Vbn = 0.6V
Vbn = 0.8V
Vbn = 1V
6. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
42
margin (NMH) increases from 0.60 V to 0.79 V. Similarly, when bias voltage of n-channel
FGMOS (Vbn) is increased from 0 V to 1 V, while keeping Vbp fixed at 0 V, NML decreases from
0.68 V to 0.40 V. Now, in the circuit of FGMOS inverter, M2 (n-channel) determines NML and
M1 (p-channel) determines NMH and both noise margins are desired to be high for better noise
immunity. From table 1, we observe that NMH and NML are maximum when Vbp = 0 V & Vbn = 1
V which is the condition of low voltage operation for FGMOS because for Vbp = 0 V & Vbn = 1 V,
M1 and M2 exhibits minimum value of threshold voltage. Therefore, better noise margins can be
optimized by appropriate selection of Vbp and Vbn at 0V and 1V respectively.
The transient behaviour of the FGMOS inverter can be characterized by propagation delay (tp)
which is defined as the average of the time delay from low-to-high transition (tplh) and from high-
to-low transition (tphl) of the input and output waveforms in an inverter. It specifies the operating
speed and is given as [15, 16]:
2
)( tt
t
phlplh
p
+
= (3)
The propagation delay for FGMOS inverter can be given as [14]:
−
−+
−
−=
−− 1
1
2
p
1
1
2
n
)()(
35.0
k
kVV
V
k
kVV
VCt
bpTp
DD
bnTn
DDLp ββ (4)
Since tp depends on threshold voltage of n and p-channel MOSFETs, therefore it is expected that
it can be optimized using FGMOS where threshold voltage tunability is feasible [12].
The transient characteristics of FGMOS inverter at different values of Vbp and Vbn are shown in
Figs. 7 and 8 respectively.
Figure 7. Transient response of FGMOS inverter at different Vbp
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5
Vout(Volts)
Time (ns)
Vin
Vbp = 0V
Vbp = 0.4V
Vbp = 0.8V
Vbp = 1V
7. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
43
Figure 8. Transient response of FGMOS inverter at different Vbn
It is seen that the pulse response of FGMOS inverter can be varied with bias voltage resulting in
different values of propagation delay as shown in Fig. 9.
Figure 9. Propagation delay at different bias voltage
It has been observed in Fig. 9 that if the bias voltage of p-channel FGMOS is increased from 0V
to 1V while keeping bias voltage of n-channel FGMOS fixed at 1 V, the propagation delay
increases from 0.19 ns to 0.66 ns. Similarly, if bias voltage of n-channel FGMOS is increased
from 0 V to 1 V while keeping bias voltage of p-channel FGMOS fixed at 0 V, the propagation
delay decreases from 0.32 ns to 0.19 ns. Therefore, the appropriate selection of bias voltages of n
and p-channel FGMOS at 1V and 0V respectively decreases the propagation delay of FGMOS
inverter, thus enhancing the operating speed.
Now, the comparative transient characteristics of CMOS and FGMOS inverters have been
obtained by selecting Vbp = 0 V and Vbn = 1 V as shown in Fig. 10.
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5
Vout(Volts)
Time (ns)
Vin
Vbn = 0V
Vbn = 0.4V
Vbn = 0.8V
Vbn = 1V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1
Delay(ns)
Biasvoltage
Vbn
Vbp
8. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
44
Figure 10. Comparative transient characteristics of CMOS and FGMOS inverters
From these results, it has been observed that FGMOS based inverter has less propagation delay
(0.2 ns) as compared to CMOS inverter which has the propagation delay of 0.4 ns, implying that
FGMOS based inverter exhibits better switching response and has high operating speed.
Since, the energy delay product represents the trade-off between power dissipation and the speed,
implying the operation of digital circuits at low power would result in loss of speed. Therefore,
lower value of energy delay product is required for circuits suitable for operation with low
operating voltage and low power consumption without much loss in operating speed. Now, the
values of propagation delay obtained from the transient analysis of CMOS and FGMOS based
inverters has been used to calculate the energy delay product (EDP) at different values of VDD as
shown in Fig. 11.
Figure 11. Comparative EDPs of CMOS and FGMOS inverters
The results obtained from Fig. 11 show that EDP is a function of supply voltage and for VDD=1V,
FGMOS inverter has EDP of 1×10-23
Js where as the value of EDP for CMOS inverter is 2×10-23
Js. Therefore, FGMOS inverter shows better performance as compared to CMOS due to lower
value of energy delay product, thus posing as an alternative design technique for low voltage and
high speed digital circuits.
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5Vout(Volts)
Time (ns)
Inputvoltage
CMOS inverter
FGMOS inverter
0
0.5
1
1.5
2
2.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EDP(Js)*10-23
VDD (Volts)
CMOS Inverter
FGMOS Inverter
9. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
45
4. RING OSCILLATOR
Since FGMOS inverter exhibits better response than its CMOS counterpart in terms of speed,
noise immunity and power dissipation, therefore it has been further employed to implement a ring
oscillator which is often used in the information, communication and sensor technology for
frequency translation and channel selection [17-19].
A ring oscillator based on FGMOS is shown in Fig. 12 which consists of a cascade of three
inverters and the frequency of oscillation is given by [20]:
Figure 12. FGMOS based ring oscillator
)(6
1
tt
f
plhphl
o
+
= (5)
where tphl and tplh are the propagation delay for high-to-low and low-to-high transitions
respectively in an inverter which are given as under:
2
21
211
)(
)(
kVVVk
kVVVkkC
t
bnTnDDn
bnTnDDL
phl
+−
−+
=
β
(6)
2
21
211
)(
)}(3{
kVVVk
kVVVkkC
t
bpTpDDp
bpTpDDL
plh
−+
−+
=
β
(7)
−+
−+
+
+−
−+
=+ 2
21
21
2
21
21
1
)(
)(3
)( kVVVk
kVVVk
kVVVk
kVVVk
kCtt
bpTpDDp
bpTpDD
bnTnDDn
bnTnDD
Lplhphl
ββ
(8)
10. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
46
From Eq. 8, we see that propagation delay decreases with increase in Vbn and decrease in Vbp.
Therefore, increasing bias voltage of n-channel FGMOS while keeping bias voltage of p-channel
FGMOS at zero volt will lead to small propagation delay and hence, enhanced frequency of
oscillation. Now, the circuit of FGMOS ring oscillator has been simulated at different values of
Vbn while keeping Vbp fixed at 0 V by selecting W/L of M1, M3 and M5 as 26µm/0.13µm and M2,
M4 and M6 as 13µm/0.13µm with the supply voltage of 1 V. The simulation results are shown in
Fig. 13.
Figure 13. Oscillations of FGMOS based ring oscillator at different Vbn
From the above results we have observed that the frequency of oscillation increases with increase
in bias voltage (Vbn) as shown in table 2.
Table 2. Variation of fo with Vbn
Vbn (V) fo (GHz)
0.2 4
0.4 4.5
0.6 5.2
0.8 5.9
1 6.7
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Time(ns)
Vbn=1V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vbn=0.8V
Vout(Volts)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Vbn=0.4V
11. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
47
The comparative performance of CMOS and FGMOS based three stage ring oscillator
has been obtained by selecting Vbp = 0 V and Vbn =1 V and is shown in Fig. 14. It has
been observed that frequency of oscillations in FGMOS ring oscillator is 6.7 GHz while
for CMOS ring oscillator it is 5 GHz.
Figure 14. Oscillations of CMOS and FGMOS based ring oscillators
The number of inverter stages in ring oscillator may be increased for multiphase outputs
but at the expense of reduced operating speed, high power dissipation and large chip area
[20]. The comparative frequency of oscillations in ring oscillator using CMOS and
FGMOS with different stages is given in table 3
Table 3. Comparative oscillation frequency of multistage ring oscillator
From the above results, we observe that with increase in the number of inverter stages in the
structure of ring oscillator, the frequency of oscillation decreases due to increased propagation
delay.
No. of
stages
CMOS FGMOS
fo (GHz) fo (GHz)
3 5 6.7
5 3.3 3.8
7 2.5 2.8
9 2 2.1
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Time(ns)
OutputVoltage(V)
CMOS
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
FGMOS
12. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
48
5. CONCLUSIONS
In this paper, we have studied the effect of threshold voltage tunability in FGMOS for enhancing
the performance of inverter and ring oscillator. It has been found that by varying the bias voltage
of FGMOS, the voltage transfer characteristics of inverter can be suitably altered resulting in
decreased switching threshold voltage, increased noise margins, reduced propagation delay and
energy delay product as compared to its CMOS version. Further, it has been observed that the
oscillation frequency of ring oscillator depends on the propagation delay of inverter stages and
FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to CMOS ring
oscillator.
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13. Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 5, No 2, May 2016
49
AUTHORS
Susheel Sharma received his MSc Physics (Electronics) from University of
Jammu, Jammu, India in 1991 and PhD degree from the same University in 2007
on the title ‘Analog applications of Floating-Gate MOS transistor in current
mirrors and current conveyors’. He has been working as faculty in the Department
of Physics & Electronics, University of Jammu since 1995. Presently he is an
Associate Professor in Electronics and his area of research interest includes Low
voltage analog and digital integrated circuits and he has 44 publications to his
credit in various National/International conferences and journals. He is a life member of Institution of
Electronics and Telecommunication Engineers (IETE) India and Indian Science Congress.
Rockey Gupta received his M.Sc. degree in Electronics from University of
Jammu in 2000 with gold medal. He received his Ph. D degree in Electronics in
2014 from the same university. He has been working as a faculty member in the
department of Physics and Electronics since March 2002. He has been teaching
courses of electronic devices and circuits, digital electronics, IC technology,
microprocessors and microcontrollers and computer programming with c++ to
M.Sc electronics students. He is a life member of Institution of Electronics and
Telecommunication Engineers (IETE) India and Indian Science Congress. Presently he is working as a
senior Assistant Professor in Department of Physics and Electronics, University of Jammu. His area of
research includes low voltage analog circuit design techiques using quasi-flaoting-gate MOSFETs. He has
20 publications to his credit in various National/International conferences and journals.
Roshani Gupta received her M.Sc. and M.Phil. in Electronics from University of
Jammu in the years 2011 and 2014, respectively. Presently she is pursuing Ph.D.
in Electronics from the same University. Her research interests include designing
CMOS digital circuits for low power applications.