This document summarizes a research paper that proposes a new low-voltage, low-power regulated cascode current mirror circuit designed using floating gate MOS (FGMOS) transistors. The proposed circuit achieves a high output impedance of 1.125 teraohms, a current range of up to 1500 microamps, low power dissipation of 10.56 microwatts, and a bandwidth of 4.1 megahertz. Simulation results show that the circuit operates with a single 1.0 volt power supply and outperforms previous FGMOS current mirror designs in terms of power, supply voltage, and output characteristics.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
This document analyzes and compares the performance of CMOS and FinFET logic technologies. It discusses key parameters for both technologies including gate area, gate capacitance, channel length, delay, subthreshold leakage current, and power dissipation. CMOS has advantages of low power consumption but suffers from short channel lengths. FinFET addresses this issue with a longer channel gate but higher power. The document provides equations to calculate parameters like power dissipation, delay dependence on input rise/fall time, impact of loading capacitance on gate delay, subthreshold leakage current, and threshold voltage for both CMOS and FinFET technologies.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
This document summarizes research on gate leakage reduction techniques for deep submicron integrated circuits. It discusses how gate leakage has become a significant source of power dissipation as devices are scaled down, due to increased subthreshold leakage, gate oxide tunneling, and reverse bias junction leakage. The document then describes complementary pass transistor logic (CPL) and differential cascade voltage switch logic (DCVSL) as logic families that aim to reduce static power by using fewer transistors and eliminating inverters.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
This document analyzes and compares the performance of CMOS and FinFET logic technologies. It discusses key parameters for both technologies including gate area, gate capacitance, channel length, delay, subthreshold leakage current, and power dissipation. CMOS has advantages of low power consumption but suffers from short channel lengths. FinFET addresses this issue with a longer channel gate but higher power. The document provides equations to calculate parameters like power dissipation, delay dependence on input rise/fall time, impact of loading capacitance on gate delay, subthreshold leakage current, and threshold voltage for both CMOS and FinFET technologies.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
This document summarizes research on gate leakage reduction techniques for deep submicron integrated circuits. It discusses how gate leakage has become a significant source of power dissipation as devices are scaled down, due to increased subthreshold leakage, gate oxide tunneling, and reverse bias junction leakage. The document then describes complementary pass transistor logic (CPL) and differential cascade voltage switch logic (DCVSL) as logic families that aim to reduce static power by using fewer transistors and eliminating inverters.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
The document discusses a proposed new logic family called current-steering CMOS (CS-CMOS) that aims to reduce switching noise in mixed-signal systems.
[1] CS-CMOS is obtained through a simple modification to standard CMOS logic, adding a pair of complementary transistors to provide a constant bias current through the gate. This helps minimize noise generation during state transitions while keeping power consumption lower than other constant-current logic families.
[2] The static transfer characteristics of the CS-CMOS inverter are analyzed, showing it provides the same output high and low voltages as CMOS. Positive feedback is present due to the biasing transistors, leading to high gain during output transitions.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
This document summarizes the evolution of LDMOS transistor technology for S-band radar applications over the last decade. Key improvements include a doubling of power density at 3.6 GHz to over 1 W/mm, and an increase in gain from 7 dB to 14 dB. The latest generation LDMOS devices outperform bipolar transistors at S-band frequencies, with gains over 5 dB higher and efficiencies 5-10% greater. 100W and 120W microwave products in the S-band demonstrate state-of-the-art performance with gains of 11-12 dB and efficiencies near 50%.
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
The document describes the impact of on-chip interconnect wires on integrated circuits. It discusses how wire parasitics such as capacitance, resistance, and inductance can increase propagation delay, power dissipation, and noise. The document then examines electrical wire models including lumped models that treat parasitics as single components and distributed models that account for parasitics varying along the wire length. Key interconnect parameters like capacitance are calculated using parallel plate models and the factors that affect resistance and inductance are also explored.
This paper presents the design and simulation of a low voltage Si LDMOS transistor using ATLAS SILVACO. The proposed LDMOS structure has a channel length of 0.3 μm and gate length of 0.75 μm, smaller than the reference device. Simulations show the new device has higher breakdown voltage of 13.75 V and lower on resistance compared to the reference LDMOS. Impact ionization occurs away from the drain in the drift region, allowing for the higher breakdown voltage. The feedback capacitance is also reduced compared to the reference device. In summary, the proposed lower voltage LDMOS transistor has a more compact size while improving key characteristics like breakdown voltage and on resistance.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
This document provides an overview of CMOS technology. It discusses how CMOS circuits use complementary pairs of NMOS and PMOS transistors to implement logic gates like inverters. The CMOS inverter uses one transistor to pull the output low and the other to pull it high, allowing for low power operation. Larger CMOS logic gates consist of pull-down and pull-up networks of NMOS and PMOS transistors respectively. Transistor sizing is also covered, with sizing done to ensure equal driving capability between pull-up and pull-down networks.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
THE DESIGN OF A LOW POWER FLOATING GATE BASED PHASE FREQUENCY DETECTOR AND CH...VLSICS Design
A simple new architecture of phase frequency detector with low power and low phase noise is presented in
this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors
including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion
input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm
technology. Floating gate based methodology reduced the power of phase frequency detector about 51%.
Introduction of floating gate based phased frequency detector also reduces the number of transistor as
compared with conventional phase frequency detector.
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUITVLSICS Design
This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
The document discusses a proposed new logic family called current-steering CMOS (CS-CMOS) that aims to reduce switching noise in mixed-signal systems.
[1] CS-CMOS is obtained through a simple modification to standard CMOS logic, adding a pair of complementary transistors to provide a constant bias current through the gate. This helps minimize noise generation during state transitions while keeping power consumption lower than other constant-current logic families.
[2] The static transfer characteristics of the CS-CMOS inverter are analyzed, showing it provides the same output high and low voltages as CMOS. Positive feedback is present due to the biasing transistors, leading to high gain during output transitions.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
This document summarizes the evolution of LDMOS transistor technology for S-band radar applications over the last decade. Key improvements include a doubling of power density at 3.6 GHz to over 1 W/mm, and an increase in gain from 7 dB to 14 dB. The latest generation LDMOS devices outperform bipolar transistors at S-band frequencies, with gains over 5 dB higher and efficiencies 5-10% greater. 100W and 120W microwave products in the S-band demonstrate state-of-the-art performance with gains of 11-12 dB and efficiencies near 50%.
1) The document reviews a differential tunable active inductor LC-tank voltage-controlled oscillator (VCO) circuit proposed by Lu et al. that achieves a wide tuning range.
2) The circuit uses a differential active inductor and varactor capacitors in the LC tank. Coarse tuning is achieved by varying the equivalent inductance through a voltage-controlled resistor, while fine tuning uses a varactor.
3) This topology achieved a 143% extended tuning range and significant size reduction compared to previous VCO designs.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
The document describes the impact of on-chip interconnect wires on integrated circuits. It discusses how wire parasitics such as capacitance, resistance, and inductance can increase propagation delay, power dissipation, and noise. The document then examines electrical wire models including lumped models that treat parasitics as single components and distributed models that account for parasitics varying along the wire length. Key interconnect parameters like capacitance are calculated using parallel plate models and the factors that affect resistance and inductance are also explored.
This paper presents the design and simulation of a low voltage Si LDMOS transistor using ATLAS SILVACO. The proposed LDMOS structure has a channel length of 0.3 μm and gate length of 0.75 μm, smaller than the reference device. Simulations show the new device has higher breakdown voltage of 13.75 V and lower on resistance compared to the reference LDMOS. Impact ionization occurs away from the drain in the drift region, allowing for the higher breakdown voltage. The feedback capacitance is also reduced compared to the reference device. In summary, the proposed lower voltage LDMOS transistor has a more compact size while improving key characteristics like breakdown voltage and on resistance.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
This document provides an overview of CMOS technology. It discusses how CMOS circuits use complementary pairs of NMOS and PMOS transistors to implement logic gates like inverters. The CMOS inverter uses one transistor to pull the output low and the other to pull it high, allowing for low power operation. Larger CMOS logic gates consist of pull-down and pull-up networks of NMOS and PMOS transistors respectively. Transistor sizing is also covered, with sizing done to ensure equal driving capability between pull-up and pull-down networks.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
THE DESIGN OF A LOW POWER FLOATING GATE BASED PHASE FREQUENCY DETECTOR AND CH...VLSICS Design
A simple new architecture of phase frequency detector with low power and low phase noise is presented in
this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors
including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion
input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm
technology. Floating gate based methodology reduced the power of phase frequency detector about 51%.
Introduction of floating gate based phased frequency detector also reduces the number of transistor as
compared with conventional phase frequency detector.
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUITVLSICS Design
This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The document presents a novel approach called "stacking with sleepy keeper" for reducing leakage power in 65nm CMOS technologies. It combines transistor stacking, sleep transistors, and sleepy keeper techniques. Simulation results show the proposed approach significantly reduces average and static power compared to basic NAND gates and other techniques. For a 2-input NAND gate, the proposed approach with high Vth transistors reduces average power by 97.32% and static power by 99.24% compared to a basic NAND gate. When implemented in an SRAM cell, the proposed approach also improves power, delay, and power-delay product metrics.
This document discusses techniques to reduce leakage current and power consumption in static random-access memory (SRAM) cells implemented using independent gate fin field-effect transistors (FinFETs). It first describes the independent gate FinFET SRAM cell design and its advantages over other designs. It then examines two circuit-level leakage reduction techniques: 1) using multi-threshold voltages by connecting high-threshold transistors to reduce leakage when in standby mode, and 2) adding a gated power supply transistor to reduce leakage through stacking effects. Simulation results show that both techniques can reduce leakage current and power in the independent gate FinFET SRAM cell, with multi-threshold voltages providing better leakage control.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
This document presents a study on implementing an extremely low power fifth-order FIR digital filter using sub-threshold source coupled logic (STSCL) in a 45nm CMOS process. STSCL allows logic gates to operate at sub-threshold voltage levels, enabling significantly lower power consumption compared to traditional CMOS implementations. The paper designs basic logic gates like XOR, OR, AND in STSCL. A fifth-order FIR filter with transposed direct form structure is implemented using the STSCL gates, with five-bit canonic signed digit multipliers for coefficient multiplication. Simulation results show the STSCL-based FIR filter achieves lower power-delay product than a comparable CMOS implementation, demonstrating the potential for STS
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes a research paper that proposes low-leakage 1-bit full adder cell designs for reducing power consumption in nanometer technologies. It introduces two modified full adder circuit designs (Design1 and Design2) that apply transistor resizing and power gating techniques. Simulation results show that the proposed designs reduce standby leakage power and active power compared to a conventional 28-transistor CMOS full adder. Design1 sizes transistors with a 3.17x PMOS-to-NMOS ratio while Design2 uses a 1.5x ratio. Both aim to minimize area and leakage through optimized transistor widths and lengths.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
This document summarizes the design and simulation of a low power, low voltage bulk driven balanced operational transconductance amplifier (OTA) in a 130nm CMOS process with a 0.9V supply. The OTA uses bulk driven NMOS transistors at the input stage to avoid threshold voltage limitations. Simulation results show the OTA achieves a power consumption of 3.9uW with a 550mV output voltage swing. Key performance metrics like gain, bandwidth, slew rate and noise are provided and meet expectations for low power analog circuit design in modern CMOS processes. The bulk driven approach allows designing circuits for voltages lower than transistor thresholds and maintains reasonable performance for low power analog applications.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Design of a High Precision, Wide Ranged Analog Clock Generator with Field Pro...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a
continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
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Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
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Blood finder application project report (1).pdfKamal Acharya
Blood Finder is an emergency time app where a user can search for the blood banks as
well as the registered blood donors around Mumbai. This application also provide an
opportunity for the user of this application to become a registered donor for this user have
to enroll for the donor request from the application itself. If the admin wish to make user
a registered donor, with some of the formalities with the organization it can be done.
Specialization of this application is that the user will not have to register on sign-in for
searching the blood banks and blood donors it can be just done by installing the
application to the mobile.
The purpose of making this application is to save the user’s time for searching blood of
needed blood group during the time of the emergency.
This is an android application developed in Java and XML with the connectivity of
SQLite database. This application will provide most of basic functionality required for an
emergency time application. All the details of Blood banks and Blood donors are stored
in the database i.e. SQLite.
This application allowed the user to get all the information regarding blood banks and
blood donors such as Name, Number, Address, Blood Group, rather than searching it on
the different websites and wasting the precious time. This application is effective and
user friendly.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELijaia
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#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
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#Prerequisites:
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Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
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FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CURRENT MIRROR
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
DOI : 10.5121/vlsic.2013.4204 39
FGMOS BASED LOW-VOLTAGE LOW-POWER
HIGH OUTPUT IMPEDANCE REGULATED
CASCODE CURRENT MIRROR
Abhinav Anand1
, Prof. Sushanta K. Mandal2
, Anindita Dash3
, B. Shivalal Patro4
1,2,3,4
School of Electronics Engineering, KIIT University, Bhubaneswar, India
abhinavvlsi@gmail.com1
, sushantakumar@yahoo.com2
, litun.1103@gmail.com3
,
shivalal.lali@gmail.com4
ABSTRACT
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply.
KEYWORDS
Floating Gate MOSFET, Current Mirror, Regulated Cascode, Low-Voltage & Low-Power
1. INTRODUCTION
A current mirror (CM) is a circuit designed to copy a current through one active device by
controlling the current in another active device of circuit, keeping the output current constant
regardless of loading. The responsibilities of current mirror circuit are current amplification and
to provide proper biasing to analog circuits. Due to very wide application of current mirror in low
voltage low-power analog circuits, accuracy, output impedance and power consumption play key
role in determining CM performance [6]. Their utilization in analog signal processing extends the
advantages of low-voltage operations, derivation of resistorless topologies and electronic
adjustment capability of their frequency characteristics [13].
With the increasing demand for smaller and faster products, there is an ongoing trend in
fabrication process towards smaller transistors. Reducing feature size arises potential problem
like power dissipation and dielectric breakdown due to high electric field across the feature.
These potential problems can be compensated by reducing the voltage and hence low-voltage
power supply is beneficial. In addition to this battery lifetime is crucial factor in various
applications and hence low-power device is also a compulsory requirement as per current market
trend. In the quest to achieve low-voltage and low-power, various techniques have evolved in due
course of time and Floating Gate MOS (FGMOS) technique is one amongst them.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
40
FGMOS is proven technology in digital circuits but has also gained pace when it comes to its
application in the area of low-voltage, low-power analog design. FGMOS is a device in which the
second gate generally called floating gate is electrically isolated but capacitively coupled to input
gates. A control voltage present at one of the multi-input FGMOS and facility to additional
weighted inputs provides wide range of tunability to the circuit [1]. Implementation of FGMOS
allows threshold voltage (Vth) controllability without reducing the feature size, thus operates at
power supply voltage levels which are well below the intended operational limit. Also, it
consumes less power than the minimum required power for a circuit designed with conventional
MOSFET. Using regulated cascode configuration achieves high output impedance of the order of
gm
2
rout
3
where gm is device trans-conductance and rout is output resistance [5], [10]-[11].
Various FGMOS based current mirror designs have been presented in [4], [7] and [8]-[9].
FGMOS based current mirror design presented in [4] and [8] suffers from higher power
dissipation and lower current range. On the other hand [7] and [9] both presents FGMOS based
design having better results with respect to input impedance, bandwidth and supply voltage but
exhibits very low output impedance. Current mirror suggested in [12] has ultra low power
dissipation but at a very low biasing current of the order of atto ampere.
In this paper a new low-voltage, low-power regulated cascode current mirror has been proposed.
At input side of the proposed design a 3-input FGMOS device has been introduced to control the
input characteristics of CM by varying the input bias voltage at one of the floating gate. The
design has been supported by the simulated results.
The rest of the paper is organised as follows: Brief introduction of FGMOS and regulated cascode
current mirror (RCCM) is given in section 2. Section 3 describes the proposed low-voltage, low-
Power CM (LV-LPCM). Simulation results are discussed in section 4. Finally, some conclusions
are drawn in section 5.
2. FGMOS AND REGULATED CASCODE CURRENT MIRROR
In this section floating gate MOSFET (FGMOS) and regulated cascode CM (RCCM) have been
briefly introduced with their diagrammatic representation. This section also justifies the
implementation of FGMOS and RCCM into the final design.
2.1. Floating Gate MOSFET (FGMOS)
Floating Gate MOS transistors are widely used in digital world as EPROM, EEPROM, flash
memories, and neuronal computational element in neural network, digital potentiometers and
single transistor DAC’s. But, it is also gaining its popularity in analog design and has found
application in low-voltage low-power analog design and analog storage elements. A typical multi
input floating gate transistor is shown in Figure 1. It is a conventional MOSFET in which the gate
is capacitively coupled to the input using another poly-silicon layer. The equation that models the
behaviour of floating gate voltage (VFG) of FGMOS is given by equation (1) [1], [3].
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Figure 1. Equivalent schematic of N-input n-channel FGMOS
(1)
Where and QFG accounts for the amount of charges that is being
trapped in FG during fabrication.
FGMOS device provides impressive features relevant to low-voltage, low-power context. It
shows flexibility in implementing both linear as well as non-linear functions. Independent control
of threshold voltage (Vth) accounts for controllability of the device. Also, since it is a multi-input
device, FGMOS allows addition of extra inputs as per designer’s requirement and hence provide
tunability to the circuit.
In order to simulate FGMOS in Cadence design environment, a simulation model is needed which
is shown in Figure 2 [1], [3]. In the model, the voltages V1, V2, ..., Vn are the input voltages which
are coupled to gate by resistor-capacitor parallel combination. VF and V0 are floating gate voltage
and substrate voltage respectively. M is a conventional MOSFET.
Figure 2. Simulation Model for N-input n-channel FGMOS
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Figure 3. Test circuit for comparison between N-type FGMOS and NMOS
Figure 3 shows the test circuit for comparison between 2-input N-type FGMOS and a
conventional NMOS. The simulated output characteristics and power dissipation on comparative
basis is shown in Figure 4 and Figure 5 respectively.
Figure 4. DC response of N-type FGMOS and conventional NMOS
Power dissipation of 2-input N-type FGMOS is 673.9 µW for the test circuit, which is nearly 40%
less than that of conventional NMOS transistor. This suffices for one of the reason why FGMOS
device is used in low-voltage, low-power design.
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Figure 5. Power Dissipation of N-type FGMOS and conventional NMOS
2.2. Regulated Cascode Current Mirror (RCCM)
Regulated cascode CM is improved version of simple CM and it uses negative feedback concept
for output current stabilization [2]. A typical regulated cascode configuration is shown in Figure
6. The primary reason behind considering RCCM configuration as a basis for the proposed design
is its high output impedance of the order of gm
2
rout
3
. Also, current gain matching for regulated
cascode configuration is good as long as primary transistors are properly biased.
Figure 6. Regulated Cascode Current Mirror configuration
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3. PROPOSED FGMOS BASED LV-LPCM
The proposed LV-LP RCCM is based on FGMOS technique and is shown in Figure 7. It allows
the design to work at a voltage as low as +0.8 Volts but works best at a single supply voltage of
+1.0 Volts. It exhibits good matching accuracy and high output impedance of the order of 1.125
TΩ.
Table 1. Transistor Sizes of the Proposed CM
Transistors W(µm) L(nm) W/L
3-input N-
Type
FGMOS
18 180 100
NM0 36 180 200
NM1 18 180 100
NM2 5.4 180 30
NM3 18 180 100
NM4 18 180 100
PM0 18 180 100
PM1 18 180 100
Figure 7. Proposed LV-LP Regulated Cascode CM
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Power dissipation of the circuit has been reduced to a value as low as 10.56 µW. It achieves
higher current range of up to 1500 µA. The aspect ratios for various transistors have been
summarized in Table1.
Transistors NM1, 3-input N-type FGMOS, NM4 and NM3 accounts for conventional regulated
cascode CM. Transistors PM0 and PM1 are biasing transistors and provides accurate matching at
the output. Transistor NM2 is connected in negative feedback to increase the output resistance
and stabilize the output current. NM0 is specifically introduced in common gate configuration to
achieve higher output resistance up to TΩ range. The circuit however suffers from low bandwidth
which is overshadowed by other satisfactory results viz. high output resistance, large current
range and very low power dissipation.
3. SIMULATION RESULTS
The proposed circuit is simulated with Cadence Spectre simulator in Virtuoso ADEL
environment. Various simulated results corresponding to its respective analysis viz. transient, DC
or AC analysis with appropriate test circuits has been done. DC analysis is carried out to obtain
current range. Figure 8 shows that the design achieves a current range of upto 1500 µA. Input and
output characteristics are shown in Figure 9 and Figure 10 respectively.
Figure 8. Transfer Characteristics
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Figure 9. Input Characteristics
Figure 10. Output Characteristics
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Figure 11 illustrates the variation in input resistances with input biasing current. It can be
observed from the graph that input impedance of the circuit is 24.5 KΩ for biasing current of 20
µA and as low as 540 Ω for a input biasing current of 500 µA.
Figure 11. Input Impedance versus Input biasing current
Transient analysis is carried out to evaluate power dissipation of the circuit. It is observed to be
10.56 µW as shown in Figure 12, which makes the circuit a low power design.
Figure 12. Power dissipation
AC analysis is performed to obtain the output impedance and bandwidth of the proposed FGMOS
based LV-LP RCCM. The output impedance comes out to be 1.125 TΩ and bandwidth of 4.1
MHz at a biasing current of 10 µA and is shown in Figure 13 and Figure 14 respectively.
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Figure 13. Output Impedance
Figure 14. Frequency Response
The performance of the proposed design has been compared with previous works and is being
presented in Table 2.
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Table 2. Comparison with previous works
4. CONCLUSION
This paper demonstrates a floating gate MOSFET (FGMOS) based low-voltage, low-power
regulated cascode current mirror which exhibits a very high output impedance of 1.125 TΩ and
dissipates power as low as 10.56 µW at an input biasing current of 10 µA. The current range for
the circuit is also at par with respect to other design. The proposed design can work well with
low-power, low-voltage analog signal processing & bio-medical application. Measured
performance of proposed current mirror is comparable with other proposals reported to date, as
shown in Table 2. The simulation is done in Cadence design environment for 180 nm CMOS
technology with a single power supply of +1.0 Volts.
REFERENCES
[1] Esther Rodriguez-Villegas, “Low Power and Low Voltage Circuit Design Techniques with FGMOS
Transistor”, IET Circuit and Device System Series 20.
[2] Hitesh, Anuj Goel, “Advancement in Current Mirror Technique”, International Journal of Advance
Research in Computer Science & Software Engineering, Vol. 2, Issue 1, January 2012.
[3] Yin, L., Embabi, S. H. K., and Sánchez-Sinencio, E.: “A floating-gate MOSFET D/A converter”,
Proceedings of the IEEE International Symposium on Circuits and Systems, 1997, pp. 409–12.
[4] Parshotam S. Manhas, Susheel Sharma, K. Pal, L.K.Mangotra & K.S. Jamwal, “High performance
FGMOS-based low volage current mirror”, Indian journal of Pure & Applied Physics, Vol. 46, May
2008, pp. 355-358
[5] Behzad Razavi, Design of analog integrated circuits, McGraw Hill, 2001.
[6] S.S Rajput and S.S Jamuar, “ A high performance current mirror for low voltage designs”, Asia-
Pacific Conference on Circuits and Systems, pp. 170-173, Dec 2000.
[7] Susheel Sharma, S.S. Rajput, L.K. Mangotra and S.S. Jamuar, “FGMOS based wide range low
voltage current mirror and its application”, Asia-pacific conference on Circuit & Systems. Vol. 2 pp.
331-334, Oct 2002.
[8] Rockey Gupta, Shusheel Sharma, S.S. Jamuar, “A low voltage current mirror based on quasi-floating
gate MOSFET”, IEEE Conference, 2010.
[9] Bhawna Aggarwal, Maneesha Gupta, “Low-voltage cascode current mirror based on bulk-driven
MOSFET and FGMOS Techniques”, International Conference on Advances in Recent Technologies
in Communication and Computing, 2009.
[10] D.Johns and K.Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, 1997.
Parameters
Proposed
Work
REF[12] REF[7] REF[9] REF[8] REF[4]
Process
Technology (µm)
0.18 0.18 0.50 0.25 0.50 0.50
Supply Voltage
(Volts)
+1.0(single
supply)
±1.8 ±0.75 ±0.45 ±0.75 ±0.75
Current
Range(µA)
0-1500 - 0.1-500 0-150 0-500 ~2-500
Output
Impedance(TΩ)
1.125 0.045 0.00135 0.0153 0.00167 0.7854
Input
Impedance(KΩ)
3.73 (Ibias=
50 µA)
20000 0.2 1.99 0.48 -
Power
Dissipation(µW)
10.56 1.5 - 96.5 1500 250
Bandwidth(MHz) 4.1 15.8 500 - 640 631
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[11] P.E. Allen and D.R. Holberg, “CMOS Analog Circuit Design”, 2nd ed. Oxford, U.K. : Oxford, 2002.
[12] Seyed Javad Azhari, Khalil Monfaredi, and Hassan Faraji Baghtash, “A Novel Ultra Low Power High
Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth”, Journal of Electronics
Science and Technology, Vol. 8, No. 3, September 2010.
[13] Costas Laoudias and Costas Psychalinos, “Application of current mirrors in analog signal
processing”, Physics Department, Electronics Laboratory, University of Patras, Rio Patras, Greece.
Authors
Mr. Abhinav Anand : He received his B.Tech in Electronics & Telecommunication
Engineering from College of Engineering Roorkee, Uttarakhand. He has worked as
Lecturer with Uttaranchal Institute of Technology, Dehradun. Currently he is an
M.Tech student in VLSI design & Embedded System in School of Electronics
Engineering at KIIT University, Bhubaneswar, Odisha. His main researches focus on
Low-Voltage, Low-Power analog circuit design.
Dr. Sushanta K. Mandal : He received his B.E. degree in Electrical Engineering from
Jalpaiguri Govt. Engineering College, West Bengal, India in 1993, MS and Ph.D degree
from Indian Institute of Technology (IIT), Kharagpur, India in 2002 and 2008
respectively. He has 12 years of teaching and industry experience. He was actively
associated with Advanced VLSI Design Laboratory at IIT. Kharagpur from 2002-2007.
From August 2007 to June 2010, he worked as an Assistant Professor at Dhirubhai
Ambani Institute of Information and Communication Technology (DA-IICT),
Gandhinagar. Currently he is a Professor at KIIT University, Orissa since July 2010. He has published
number of research papers in reputed journals and conferences. His research interests include modelling
and synthesis of on-chip passive devices, digital, analog and mixed-signal CMOS VLSI design, high-
level synthesis and optimization of analog circuits, soft computing applications in VLSI.
Mrs. Anindita Dash : She received her B.Tech in Electronics & Telecommunication
Engineering from Ghanashyam Hemalata Institute Of Technology and Management,
Odisha in 2008. She has worked as embedded engineer in Larsen and Toubro Embedded
Division , Mysore from June 2008 to September 2010. Currently She is pursuing
M.Tech in VLSI design & Embedded System in School of Electronics Engineering at
KIIT University, Bhubaneswar, Odisha. Her area of research includes low-voltage, low-
power, high speed analog and mixed signal circuit design.
Mr. B. Shivalal Patro : He has completed his B.Tech from Trident Academy of
Technology in Electronics & Telecommunication Engineering in 2010, Odisha. He then
completed M.Tech in Communication Systems from KIIT University in 2012. Currently,
he is a Ph.D scholar at KIIT University, Bhubaneswar, Odisha. His area of research
includes high speed, low power analog and mixed signal IC design and optimization.