This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a
continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS ring oscillator delay cell performance: a comparative studyIJECEIAES
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS ring oscillator delay cell performance: a comparative studyIJECEIAES
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE...IJERA Editor
The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since
this is the only signal which has the highest switching activity. Normally for a multiband clock domain network
we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase
clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide
band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed
which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of
6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of
frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible
divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW.
This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE
802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology.
This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized
using „Xilinx ISE 10.1‟.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
THIS PPT IS GIVEN BY EC FINAL YEAR STUDENTS OF BCE-MANDIDEEP TO PROF. RAVITESH MISHRA ON CHARGED PUMP PLLS AS AN ASSIGNMENT FROM RAZAVI,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.
Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications IJECEIAES
In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.
An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
As Technology progress deeper into submicron
CMOS, traditional analog circuits face problems that are
not to be solved purely by analog innovations. Instead,
new architectures are being proposed which take advantages
of the relatively cheaper of the digital circuits to augment or
improve the diminishing performance of the analog
circuitry. The conventional approach performs the design of
14 bands CMOS frequency synthesizers with spur reduction
for MB-OFMD for analog circuits which have high
distortions and noise. My proposed work is to replace the
analog input PLL into All Digital PLL with spur reduction.
Then the frequency mixing architecture alleviates
harmonics mixing and pulling to diminish spur
generation. The simulation is performed using Model SIM
and the implementation using Microwind to diminish spur
reduction.
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERSIJMEJournal1
In this paper, we are present design and analysis of PLL, which is simulated in CMOS 0.18μm technology.The digital phase locked loop achieves locking within about 100 reference clock cycles. The pure digital
phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog
counterpart.In this PLL circuit successfully achieved 1.55GHz frequency. Jitter is 1.09ns achieved is very
less. Also achieve low phase noise -98.5827 at 1MHz Frequency
A miniature tunable quadrature shadow oscillator with orthogonal control IJECEIAES
This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE...IJERA Editor
The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since
this is the only signal which has the highest switching activity. Normally for a multiband clock domain network
we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase
clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide
band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed
which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79
prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of
6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of
frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible
divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW.
This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE
802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology.
This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized
using „Xilinx ISE 10.1‟.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
THIS PPT IS GIVEN BY EC FINAL YEAR STUDENTS OF BCE-MANDIDEEP TO PROF. RAVITESH MISHRA ON CHARGED PUMP PLLS AS AN ASSIGNMENT FROM RAZAVI,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.
Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications IJECEIAES
In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.
An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
As Technology progress deeper into submicron
CMOS, traditional analog circuits face problems that are
not to be solved purely by analog innovations. Instead,
new architectures are being proposed which take advantages
of the relatively cheaper of the digital circuits to augment or
improve the diminishing performance of the analog
circuitry. The conventional approach performs the design of
14 bands CMOS frequency synthesizers with spur reduction
for MB-OFMD for analog circuits which have high
distortions and noise. My proposed work is to replace the
analog input PLL into All Digital PLL with spur reduction.
Then the frequency mixing architecture alleviates
harmonics mixing and pulling to diminish spur
generation. The simulation is performed using Model SIM
and the implementation using Microwind to diminish spur
reduction.
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERSIJMEJournal1
In this paper, we are present design and analysis of PLL, which is simulated in CMOS 0.18μm technology.The digital phase locked loop achieves locking within about 100 reference clock cycles. The pure digital
phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog
counterpart.In this PLL circuit successfully achieved 1.55GHz frequency. Jitter is 1.09ns achieved is very
less. Also achieve low phase noise -98.5827 at 1MHz Frequency
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This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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In high speed data path network flop is one of the major functional elements to store intermediate
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design is decreased. The existing works implement various Flipflop topology in data path structure design such
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(WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is
minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a
definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide
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A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...IOSR Journals
Abstract: In high speed data path network flop is one of the major functional elements to store intermediate results and data at different stages. But the most important problem is huge power utilization due to switching activity and increase in clock period that is Timing Latency; causes the performance of data path in digital design is decreased. The existing works implement various Flipflop topology in data path structure design such as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop (WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area of the circuit is also reduced while comparing with previous methods. Index Terms: Circuit enhancement, flip-flops (FFs), high-speed, logical effort, master–slave, transmission-gate.
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The pulse generator which has been implemented in the pulse electric field (PEF) treatment system for food processing is worth to be highlighted and improved. It is parallel with the advancement in semiconductor technology, which offers robust and accurate devices. This research is an effort to produce a low cost, compact and reliable pulse generator as well as equipped with a pulse width modulation (PWM) method for wide selection of frequency and duty cycle. The result shows that the simulation process has proven the theoretical concept to be right and yields the desired outcome based on the designed values. Then, the actual printed circuit board (PCB) has been fabricated to obtain practical results which intended to be compared with the simulation outcomes. Concerning the frequency and its duty cycle, both parameters can be altered without affecting each other. It means by changing the frequency, duty cycle remains the same and vice versa. Thus, this proposed pulse generator achieves its objective and fits to be implemented in PEF treatment technology. It also can replace the conventional pulse forming network (PFN) which is bulky and costly.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
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on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
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and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
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Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
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transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
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higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
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sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
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A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
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source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
A new SOGI-PLL method based on fuzzy logic for grid connected PV inverterIJECEIAES
Phase angle detection of the grid voltage is an imperative part of control in most applications, especially for the synchronization of the current injected by the grid-connected photovoltaic inverters. Consequently, fast and accurate detection of the phase angle, frequency and amplitude of the grid voltage are indispensable data to ensure a correct generation of reference signals and operation of the grid connected inverters. We present in this work a new phase-locked loop (PLL) method for single-phase systems. The novelty is to generate an orthogonal voltage system using a second-order generalized integrator (SOGI), followed by a Park transformation, whose quadrature component is forced to zero by the fuzzy logic, in order to obtain rapid detection and a more accurate picture of the phase angle. Furthermore, simulation results with PSIM software will be submitted to verify the performance and effectiveness of the proposed method strategy. Finally, the experimental test will be used to extract the result and discuss the validity of the proposed algorithm.
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Design of a High Precision, Wide Ranged Analog Clock Generator with Field Programmability Using Floating-Gate Transistors
1. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
DOI : 10.5121/vlsic.2010.1305 49
DESIGN OF A HIGH PRECISION, WIDE RANGED
ANALOG CLOCK GENERATOR WITH FIELD
PROGRAMMABILITY USING FLOATING-GATE
TRANSISTORS
Garima Kapur
kapur.garima@gmail.com
Department of Physics and Computer Science,
Dayalbagh Educational Institute, Dayalbagh, Agra, INDIA
C.M Markan
cm.markan@gmail.com
Department of Physics and Computer Science,
Dayalbagh Educational Institute, Dayalbagh, Agra, INDIA
V. Prem Pyara
Department of Electrical Engineering,
Dayalbagh Educational Institute, Dayalbagh, Agra, INDIA
ABSTRACT
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip
programmability feature using Floating-gate transistors. The programmable oscillator can attain a
continuous range of time-periods lying in the programming precision range of Floating Gates. The
circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of
current generator circuit is programmable and mirrored to the wave generator to generate the desired
square wave. The topology is well suited to applications like clocking high performance ADCs and DACs
as well as used as the internal clock in structured analog CMOS designs. A simulation model of the
circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with
programmability precision of about 13bit [1]. Simulation results show high amount of temperature
insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate
any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
KEYWORDS
Square wave generator, floating gate FET, field programmability
1. INTRODUCTION
There are many oscillators like crystal oscillators; Novel RC oscillator [2], RC active frequency
Oscillator [3], etc., have been developed, to accomplish the need of internal clock for
synchronization between cells in VLSI circuit designs. However due to large size limitation, op-
amp offsets and complicated designs respectively, many digitally on-chip trimmed RC oscillator
2. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
50
circuit designs [4], [5], [6] have also been developed. These clock generators are temperature
insensitive and produce accurate clock which can be digitally trimmed using array of resistors or
weighted capacitors.
With time the need for high speed data transmission and accuracy increases in the system
designs. Hence a highly flexible and high precision clock generator is required to optimize for
the next generation of wired or wireless network equipment that demands highly accurate clock
generator and distribution for robust high speed transmission. Thus the research went in some
other direction; clock generator using organic thin film transistors (OTFT) and inverters with
bootstrapped transistors have been developed [7]. However it generates very low frequency
clock. The wide and continuous ranged, accurate clocks are required in optical networks, mixed
signal circuits, ATE, medical imaging and automated test equipments. Solutions proposed for
such clock generation in recent years include usage of large devices and careful layout or some
trimming and calibration techniques.
In this paper we use floating gate p-channel field effect transistor (FG-pFET) as a method for
field programmable trimming of clock frequencies. The design can generate fine-tuning of the
clock. In FG-pFET, by changing the charge at the gate we can program the variable frequency
range. Tunable FG-pFET resistor offers good precision while passive resistors implemented
using polysilicon, diffusion or well strips in CMOS technology exhibit around 0.1% matching
accuracy and around 30% tolerance [8]. As well as tunable FG-pFET resistor will acquire less
chip area as compared to other on-chip digital trimming circuit designs.
In section 2, we give the circuit diagrams of floating gate transistor, its programming and
simulation model of tunable FG-pFET resistor. We perform the simulations for output clock
generation and explained the design and programming methodology of the proposed circuit
design. In section 3 and 4, we compared our proposed clock generator with digitally trimmed
clock generator [4]. In section 5 and 6 technique used for on-chip programming and topology to
widen frequency range of the output clock are briefly described. The temperature analysis of the
proposed circuit is also shown in section 7.
2. PROPOSED CIRCUIT
This paper presents a simple RC Oscillator circuit based on the charge variation at the floating-
gate of a FG-pFET which provides the flexibility of achieving a continuous range of resistance
value, which in turn provides variable current required to generate the output clock. The clock
generated can be precisely tuned with approximately 13 bit resolution [1]. The continuous, fine-
tuned and wide ranged clock can be obtained. Compensation of variations due to change in
temperature can be obtained by just tweaking the floating gate voltage of FG-pFET according to
the specified temperature.
2.1 Floating-gate Transistor
Before introducing the basic floating gate clock generator, a brief discussion of floating gate
transistors is beneficial. Though there are different types and variations of floating gate
transistors, their basic construction and operation remain the same. Floating gate transistors are
usually MOS transistors wherein memory is stored in the form of charge trapped on floating
gate, affecting its threshold voltage. Since the gate is electrically isolated due to oxide
completely surrounding it, the charge on the gate is fixed and is responsible for establishing the
3. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
51
amount of current flowing through the transistor. While the charge on the gate will not change
on its own, that the processes such as UV photo injection, Fowler-Nordheim tunneling, and Hot-
electron injection can modify that amount of charge. The last two are the primary means of
programming floating-gate transistors to precise currents [9]. Once the desired charge is pushed
onto the floating gate, it can be utilized to provide a constant bias to other transistors in a
design, from which a precisely tuned clock can be generated.
Figure.1 shows the structure of a floating gate transistor. Due to their architecture, floating
gate transistors are small, easily manufactured in CMOS processes, and provide simple post-
fabrication programmability; characteristics which make them very useful in designing clock
generator circuits.
Figure 1: Structure of floating-gate transistor [9]
Programming ability of the oscillator is obtained by modifying the charge stored on the
floating gate. There are two programming topologies: direct and indirect programming.
However, indirect programming provides real time applications to the design. It removes the
necessity of a separate programming phase and an operational phase. As, in indirect
programming, one pFET is connected to the programming structure while the source and drain
of the other transistor are connected to the respective circuit (proposed circuit). The first pFET
is programmed with hot-electron injection and tunneling. Since the charge on this
“programmer” pFET (Mp) is modified, the current of the other transistor (the “agent”) (Ma) will
also be set as explained in figure2. With this programming technique, multiple FETs can share a
common floating gate, and hence output range can be extended as explained in section 6.
Figure 2: Indirectly programmed FG-pFET [10]
4. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
52
2.2 Tunable FG-pFET Resistor
The fundamental requirement to operate a single MOS transistor in the triode region as a linear
resistive element is to suppress its nonlinearities by applying a function of the input signal to its
gate [11] and/or its body [12]. The three principal nonlinearities in the drain current of a long-
channel transistor in the triode region are identified as the body effect, the mobility degradation,
and the fundamental quadric component due to the common-mode of the drain and source
voltages [13]. Therefore to attain linearization in CMOS resistor a common mode and large
voltage is employed at the gate. However, this technique does not completely eliminate the
body effect and the mobility degradation. The gate linearization is achieved by using model
from [13].
Since the transistor does not need to be disconnected from the circuit to program it, the
switch count is reduced, resulting in fewer parasitic and better overall performance [10]. With
the reference from [14] we have implemented FG-pFET indirectly programming circuit.
Voltage dependent current sources and programmable PMOS have been used for tunneling and
hot-electron injection to the floating gate as shown in figure3. For injection drain to source
voltages of the programming PFET is varied and for tunneling Vtun is varied. Thus charge at the
floating gate voltage changes and consecutively range of resistance can be obtained across the
transistor.
Figure 3. T-Spice 0.35um CMOS process Simulation Model of indirectly programmed tunable
FG-pFET resistor
The simulation model of the indirectly programmed tunable FG-pFET was built in T-Spice,
0.35um CMOS process. The characteristics have been obtained from the simulation model. The
hot-electron injection and tunneling currents have been plotted with respect to the floating gate
voltage, as shown in figure 4. Due to these injection and tunneling currents variation which in
turn, varied by using Vtun, Vs_prog and Vd_prog in the simulation model in figure 3, the floating
gate voltage changes and hence the tunable resistance range can be obtained. Thus, the tuning
range of FG-pFET resistor with change in floating gate voltage has been catered in figure 5.
5. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
53
Figure 4: Characteristic currents of the indirectly programmed Floating gate transistor
Figure 5: Tunable FG-pFET resistor range with respect to varying floating gate voltage,
obtained from its simulation model implemented in T-Spice 0.35um CMOSS process.
2.3 FG-pFET Programmable Clock Generator
The proposed Clock generator circuit using floating gate pFET as shown in Figure 6 consists of
a current source sub-circuit and a wave generator sub-circuit [4]. The current generator is a kind
of current mirror whose current is controlled by FG-pFET. The current from the current
generator sub-circuit is mirrored to the wave generator sub-circuit. The wave generator uses a
switch (nmos) to control the charging and discharging function of the capacitance to generate a
triangular wave. Then this triangular wave is transformed to spikes by the combination of
invertors, which in turn feed to the clock input of the D flip-flop where, input of the D flip-flop
6. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
54
is shorted with the inverted output of the D flip-flop to generate the square wave from the
spikes.
Figure 6: Proposed Clock generator circuit design simulated using T-Spice 0.35um CMOSS
process.
In the current source sub-circuit, a FG-pFET is employed which is programmed by indirect
programming as explained in the last section. The continuous ranges of resistance value are
obtained to generate varying current which in turn mirrored to the wave generator circuit. Thus,
continuous and finely tuned square wave is generated.
2.4 Design Methodology
The architecture consists of the two sub-circuits as shown in figure 6:
Wave generator circuit:
Voltage at the capacitor C depends on the current transferred from current mirror (i.e. current at
node 4)
C
t
I
V c
∆
×
=
(1)
Threshold of invertors, turn on the low impedance NMOS switch to discharge the capacitor to
zero voltage. Hence, period of the triangular voltage waveform is:
I
V
C
t
T c
c
∆
×
=
∆
=
(2)
Current generator circuit:
A constant current source is built using current mirror. The current is generated from a PFET
(source follower). A feedback circuit always stabilizes the voltage above floating-gate PFET
(V1). Therefore, the floating gate PFET will decide the current.
ds
th
gs
ox
PFET
FG V
V
V
V
V
L
W
C
I =
−
=
− 1
1 ,
)
(
µ
(3)
7. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
55
This current is substituted to get the period of charging/ discharging of capacitor as:
1
)
( V
V
V
W
C
L
V
C
T
th
gs
ox
c
c
−
∆
=
µ
(4)
The threshold voltage of the floating-gate PFET decreases/increases with increase/decrease of
floating gate voltage (to maintain transistor in linear region). Hence, the resistance of the
transistor changes which in turn changes the period of charging/discharging of the capacitor.
1
V
V
C
R
T c
PFET
FG
c
∆
×
= −
(5)
However, the period of the output clock is two times of this period (Tc). Therefore the output
square wave generated can be tuned by just varying the resistance of the floating-gate PFET.
2.5 Programming Methodology
Using floating gate transistor synapse as shown in figure 3 we have implemented the indirect
programming of FG-pFET (M3 in figure 6). Injection requires > 1.5V drain-to-source voltage
across the injection transistor (Mp in figure 3) while tunneling requires > 8V across the
tunneling terminal for 0.35µm CMOS process.
Figure 7: Variation in output clock with respect to tunneling voltage (Vt=Vtun)
The following two graphs will represent the change in output clock with change in tunneling
voltage and with change in drain to source voltage in programmable PFET i.e. changes due to
tunneling and injection respectively.
With increasing tunneling voltage, threshold voltage of floating-gate pFET (Ma in figure 3)
increases and thus the resistance, this sequentially increases the time period of the output clock
(as shown in figure 7). Whereas when the drain-to-source voltage of programmable PFET
decreases, i.e. injection decreasing, threshold voltage increases and hence the period of the
output clock (as shown in figure 8).
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Figure 8: Variation in output clock with respect to injection voltage (Vds (inj) =Vd_prog-Vs_prog)
2.6 Simulated Results
Figure 9 first wave shows the voltage across the capacitor (V4) (node 4 in figure 6). It shows the
charging and discharging of the capacitor using NMOS switch. Fig8 middle wave shows the
invertors output (V6) (node 6). The input D of the flip flop is shorted with its complemented
output. Thus, Figure 9 last wave showing the output square wave (output clock) obtained from
the D flip-flop (V7) (node 7).
The square wave generated has been kept at low frequencies by adjusting the W&Ls of
transistor used and by keeping high capacitor(C) value (250fF). As at high frequency like
20MHz very high distortion in the clock has been observed. While at low frequency 1 to 8 MHz
clear and better clock is generated as shown in figure 9.
Figure 9: The simulated output waveforms (capacitor C output, inverters output and the D flip-
flop output sequentially represented) obtained from proposed simulation model on T-spice
0.35um CMOSS process.
9. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
57
3. COMPARATIVE TRIMMING RESULTS
Table 1. Digitally trimmed resistor array RC oscillator inspired from [5]
The simulation model of the previous work by [4] is approximated in T-spice under 0.35µm
CMOS process. There is seven resistors array and each resistor switches ON/OFF using seven
nmos switches. The 32k, 30k, 25k, 22k, 20k, 18k, 14k, 10k resistors are used and the
corresponding impedance of the nmos switches are approximately 3.2k, 3.0k, 2.5k, 2k, 1.8k,
1.4k, 1k, respectively. The operating supply voltage is 2V. The equivalent resistance of the array
changes with the switching of the nmos switches. At different switching conditions (almost 27
cases of switching is possible as shown in table 1) specific range of resistance occur which in
turn generate specific ranged periodic clocks. Thus, clock generated has discrete range of
frequencies as shown in figure10.
Whereas proposed Analog Field Programmable RC oscillator circuit using FG-pFET
generates a continuous and finely tuned frequency ranged clock. With every change
(decrease/increase) in floating gate voltage, resistance increase/decrease respectively as
tabulated in table 2.
Table 2: Proposed clock generator using tunable FG-pFET resistor
FG Volt.
(V)
Resistance (K) Time Period
(us)
Frequency (MHz)
-0.31762 53.37 0.2 5
-0.26421 61.17 0.21 4.7619
-0.17629 75.65 0.22 4.5454
-0.14521 85.92 0.231 4.3290
-0.08863 108.44 0.245 4.0816
-0.0606 118.94 0.25 4
-0.04759 127.45 0.258 3.8759
-0.00543 142.88 0.28 3.6363
0.02732 154.87 0.3 3.3333
Switching Resistance (K) Time Period
(us)
Frequency (MHz)
1111111 47.8 0.15 6.67
0111111 75.9 0.18 5.55
0011111 99.98 0.2 5
0001111 120.4 0.22 4.76
0000111 137.89 0.26 3.33
0000011 154.26 0.3 2.63
0000001 167.83 0.38 2.63
0000000 175.3 0.45 2.22
1000000 151.02 0.3 3.33
1100000 125.35 0.25 4
1110000 105.35 0.2 5
1111000 88.62 0.19 5.124
1111100 70.34 0.18 5.55
111110 57.98 0.16 6.25
10. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
58
0.03106 176.99 0.32 3.125
0.032451 182.76 0.33 3.0303
0.033759 184.35 0.34 2.9411
0.036823 186.12 0.35 2.8571
0.038071 190.45 0.38 2.6315
The frequency range is small (0.97MHz-4.04MHz) or (1.63MHz-5.5MHz) because FG-
pFET resistor can vary to a certain limit. The floating gate voltage changes from -0.25V to
0.0027V at low range of resistances (45K to 130K) and FG voltage is -0.31 to 0.03 at high R
(63.37kto180.45k). At low resistance the characteristics are linear as compared to at high
resistances. Due to body effect and mobility degradation non linearity occurs when MOS
transistor operates in triode region.
Figure 10: Period variation clock generated in digitally trimmed RC oscillator design inspired
from [5] & continuous and finely tuned clock generated in proposed clock generator.
However, it gives very high resolution. Least possible change in floating gate voltage
which can affect the output clock =.0003V. The resolution limit of programmability can be
extended to 13-bit as mentioned in paper [1]. Thus, the number of changes in resistance value or
trimming can be extended till (2^13=8192 cases). Hence, more accurate and fine-tuning of
clock can be performed using proposed oscillator design.
4. THEORETICAL APPROXIMATION OF EFFECTIVE CHIP AREA
The chip area of the simulated model inspired from [5] is estimated. The transistor Effective
Area= min poly-silicon width + 2*(min poly to contact spacing) + 2*(min contact size) +2*(min
spacing from contact to active area edge). It can be approximated as poly-silicon gate area +
20% of this area. Thus, effective area of an nmos switch (for say 25k resistor w=2.7um, l=1um)
= 2.7um*1um + 0.54um=3.24sq.um. However, in the paper [5] the impedance of the nmos
switches is about 0.15ohm, i.e., (high w/l) nmos was considered (hence larger effective area). In
11. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
59
addition, the resistor (25k) will consume approximately 35.75um*35.75um chip area in 0.35um
CMOS technology [18]. Thus, the effective area consumed by the resistors array comes out to
be approximately 10224.5sq.um. Hence, the effective chip area consumed by the switching
resistor array is 10259.48sq.um.
However, in the proposed RC oscillator circuit design two layers of poly-silicon are used.
The effective area of the floating gate PFET synapse [19] is approximately 110um*93um when
the floating gate PFET synapse is generated in 0.5um CMOS process technology. The area
occupied by the capacitor (double poly layer) affect the total area of the circuit design. In
addition, this Floating gate PFET synapse will implement in 0.35um CMOS technology.
Therefore, the chip area occupied by the floating gate PFET will reduce further.
5. ON-CHIP PROGRAMMABILITY
The period of the output clock depends on floating-gate voltage, as shown in figure11. With
fixed W and L specifications of floating-gate pFET, the circuit can be trimmed by just varying
floating gate voltage of the floating gate pFET (by varying charge at the floating-gate)
fabricated as a part of proposed design of clock generator. Thus, the generation of finely tuned
frequency clock can be field programmable by simple tweaking charge at gate voltage of
transistors.
Figure 11: Variations in Clock period with change in floating gate voltage of tunable FG-pFET
resistor in the proposed circuit.
6. TOPOLOGY TO WIDEN THE CLOCK RANGE
The proposed circuit generates very highly precise and continuous ranged clock as mentioned in
last sections. However the range in which clock period can be programmed is small because
floating gate voltage of FG-pFET resistor can vary to a certain limit. Thus, to increase this range
place transistors with different W/L values in parallel with FG-pFET in the proposed circuit
(figure 4.) with the common floating gate. For example, two transistor with w/l (2/1) and (2/0.8)
are used independently then, range of resistances obtained respectively are (45K to 130K) and
12. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
60
(63.37kto180.45k); and hence clock obtained are (0.97MHz-4.04MHz) and (1.63MHz-5.5MHz)
respectively. When placed parallel with common floating gate, the clock can be generated with
frequency variation in the range between 0.97MHz-5.5MHz. As shown in Figure 12 the range
of clock can be increased further by increasing more number of transistors at common floating
gate.
Figure 12: Circuit Diagram showing Topology to extend the frequency range of output clock
7. TEMPERATURE STABILITY
TABLE 3: Variations with Temperature
Temperature(°C) Time period(us) Frequency(MHz)
0 0.280982 3.56
10 0.279235 3.58
23 0.268301 3.73
25 0.265236 3.77
27 0.264132 3.78
30 0.259952 3.84
60 0.250887 3.98
80 0.240421 4.16
13. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
61
In proposed design the variation of FG-pFET resistor values varies with temperature as shown
in figure 13. In addition, the frequency and time period change with temperature variation from
0 °C to 80 °C is shown in Table 3. The period varies at rate of 0.507ns/°C.
Figure 13: Plot representing FG-pFET resistance variation with change in temperature (about
0.1875K/°C)
The temperature dependence of the FG-pFET can be obtained using equation 4 and 5:
)
(
_
th
gs
ox
PFET
FG
V
V
W
C
L
R
−
=
µ
(6)
The temperature dependence of µ and VT can expressed as µ=µno(T/To)-m
and VT = VTo-
αVT(T-To), where To is the reference temperature, and m is the positive constant that ranges
from 1.5 to 2, and µno & VT0 are the temperature independent parameters. Also αVT is in the
range of 0.5 to 4 mV/°C[15]. Hence, the temperature coefficient of the FG-pFET can be
expressed as
T
g
VT
T
T
g
no
V
V
T
m
T
V
V
V
T
Y
R
R −
−
=
−
+
−
=
α
δ
δ
δ
δµ
µ
δ
δ 1
1
1
(7)
where, m
T
no 1
1
−
=
δ
δµ
µ & VT
T
T
V
α
δ
δ
−
=
. As a result, the temperature coefficient of the FGPFET
can be tuned by altering the effect of αVT through the use of Vg. For desired temperature, Td, and
T
d
T
g
VT
g V
T
V
V
V +
−
=
α
the temperature coefficient of the FG-pFET can be set to zero at Td.
Hence, at specific temperature by adjusting the floating gate voltage temperature coefficient of
the FG-pFET can be tuned to zero
14. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
62
8. CONCLUSION
The floating gate transistor using T-Spice, 0.35µm CMOS process, was successfully
implemented as an efficient and accurate RC Oscillator circuit. FG-pFET resistors easily
achieve high and precise (13bit) resistance values. FG-pFET resistor used in the circuit
generates continuous and linear frequency range (1.63-5.5MHz at FG-pFET’s R=110-500K or
0.95-4.04MHz at FG-pFET’s R=63.87-183.84K).By switching multiple FG-pFET (with
different W/Ls) at common floating gate, frequency range can be increased. With tweaking
charges at the floating gate of FG-pFET, the frequency of the square wave can be finely and
accurately tuned. The 13 bit of programming resolution can be obtained. It can also be operated
at 1v supply voltage.
The circuit is adaptive to the change in temperature. By programming the FG-pFET the
temperature coefficient can be tuned to zero value at any specific temperature. The size of the
proposed circuit was relatively reduced when compared to other on-chip discrete trimming
circuits. The proposed clock generator produces analog, highly precise and widely tuned square
waveform which can find its application in wired or wireless network equipment which requires
clock for highly accurate and high speed data transmission.
Table 4:Comparative Analysis of latest clock generators (RC oscillators)
1
simulated results
2
from simulated model on 0.35um CMOS process
3
Theoretically estimate
The proposed clock generator is being compared with the latest clock generators (RC
oscillators) and noted in table IV. The proposed clock generator provides continuous and finely
tuned (13bit resolution) clock. Comparable frequency range which can be extendable using
Parameters Proposed osc S.Yu, et.al[5] C.Ghidini,
et.al.[6]
J.H Choi[7] S.K.Kim,
et.al [8]
Technique FG-PFET On-chip
resistors array
5&3 bit C&R
arrays
4-bit weighted-
capacitors
OTFT
transistors
Technology 0.35um 0.5um 0.25um 0.28um Not
mentioned
Min supply
Voltage
1.8v 4.5v 2v 1.8v -40v
Frequency
Range
5.5MHz-
1.63MHz
2.22MHz-
6.67MHz2
30MHz-
36MHz
1.6MHz-
2.4MHz
140KHz
Oscillations
behaviour
Continous Discrete Discrete Discrete Discerte
Frequency
variation
0.507ns/°C 0.015ns/°C
(0.5%)
2% Not mentioned Not
mentioned
Temperature
range
0°C -80°C 0°C-80°C 0°C-80°C Not mentioned Not
mentioned
On-chip size (110um×93um)3
130um×145um 444um×280um 240um×130um Not
mentioned
Programming
resolution
13-bit
(2^13=8192)[13]
7 bit (27
=128) 8-bit 4-bit Not
mentioned
15. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
63
topology as explained before. Comparable clock period variation with temperature change
which too can be compensated.
ACKNOWLEDGMENT
The authors wish to thank funding agency MHRD and DST, Govt of India for the financial
support for this work.
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[10] D. Graham, E. Farquhar, B. Degnan, C. Gordon, and P. Hasler:, “Indirect programming of floating-
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17. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
65
Authors:
Garima Kapur is currently perusing research in
VLSI Design Lab, Department of Physics and
Computer Science, Dayalbagh Educational
Institute, Agra, India. After completing M. Tech
in VLSI and Embedded System Design from
MACT, Bhopal, INDIA. Her interests are in
applications of floating gate transistors as
tunable resistor. She is a student member of
IEEE and VLSI society of India.
Dr. C. M. Markan is an Associate Professor in
Department of Physics and Computer Science,
Dayalbagh Educational Institute, Dayalbagh,
Agra, India. His areas of interests are in
Neuromorphic and Adaptable Analog VLSI,
Virtual Laboratories. He is a member of IEEE,
Systems Society of India, and International
Association of Online Engineering.
Prof. V. Prem Pyara is currently professor in the
Department of Electrical Engineering,
Dayalbagh Educational Institute, Dayalbagh,
Agra, India. His current areas of interest are
Electronics and Signal Processing.