This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Substrate integrated waveguide power divider, circulator and coupler in [10 1...ijistjournal
The Substrate Integrated Waveguide (SIW) technology is an attractive approach for the design of high
performance microwave and millimeter wave components, as it combines the advantages of planar
technology, such as low fabrication costs, with the low loss inherent to the waveguide solution. In this
study, a substrate integrated waveguide power divider, circulator and coupler are conceived and optimized
in [10-15] GHz band by Ansoft HFSS code. Thus, results of this modeling are presented, discussed and
allow to integrate these devices in planar circuits.
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Improved Low Voltage High Speed FVF Based Current Comparator with Logical Eff...IJERA Editor
In this paper an improved current comparator is using flipped voltage follower (FVF) to obtain the single supply
voltage. This circuit has short propagation delay and occupies a small chip area. All circuits have been simulated
employing Tanner EDA Tool 14.1v for 90nm CMOS technology and a comparison has been performed with its
non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Design of Two Two-Way Out-of-Phase Slotline Power Divider in C-BandIJTET Journal
Abstract— Power divider is one of the major components of radio frequency circuits. In this paper two two-way out-of-phase slotline power dividers designed was presented in a microstrip platform. The power dividing circuit, low profile is designed at compact size structure. To provide better isolation at the two output ports microstripline is bent and a slotline is provided. The design is simulated using ADS, results substantiate low insertion loss, better isolation and amplitude balancing at the output ports.
This paper presents a new type of wideband waveguide (SIW) cavity-backed patch antenna for millimeter wave (mmW). The antenna proposed applies to applications of 31-36 GHz Ka-band such as satellites communications. The SIW is intended with settings for particular slots. The antenna is constructed on Rogers RT5880 (lossy) with 2.2 dielectric constant, l.27 mm thickness, and 0.0009 loss tangent. It is simulated in the programming of computer simulation technology (CST) Microwave Studio. The simulated results show that the SIW antenna resonates across 31 to 36 GHz bands, which means that this new antenna covers all applications within this range. The reflection coefficients in targeting range are below 10 dB. The antenna achieves good efficiency and gain with 80% and 8.87 dBi respectively.
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Substrate integrated waveguide power divider, circulator and coupler in [10 1...ijistjournal
The Substrate Integrated Waveguide (SIW) technology is an attractive approach for the design of high
performance microwave and millimeter wave components, as it combines the advantages of planar
technology, such as low fabrication costs, with the low loss inherent to the waveguide solution. In this
study, a substrate integrated waveguide power divider, circulator and coupler are conceived and optimized
in [10-15] GHz band by Ansoft HFSS code. Thus, results of this modeling are presented, discussed and
allow to integrate these devices in planar circuits.
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Improved Low Voltage High Speed FVF Based Current Comparator with Logical Eff...IJERA Editor
In this paper an improved current comparator is using flipped voltage follower (FVF) to obtain the single supply
voltage. This circuit has short propagation delay and occupies a small chip area. All circuits have been simulated
employing Tanner EDA Tool 14.1v for 90nm CMOS technology and a comparison has been performed with its
non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Design of Two Two-Way Out-of-Phase Slotline Power Divider in C-BandIJTET Journal
Abstract— Power divider is one of the major components of radio frequency circuits. In this paper two two-way out-of-phase slotline power dividers designed was presented in a microstrip platform. The power dividing circuit, low profile is designed at compact size structure. To provide better isolation at the two output ports microstripline is bent and a slotline is provided. The design is simulated using ADS, results substantiate low insertion loss, better isolation and amplitude balancing at the output ports.
This paper presents a new type of wideband waveguide (SIW) cavity-backed patch antenna for millimeter wave (mmW). The antenna proposed applies to applications of 31-36 GHz Ka-band such as satellites communications. The SIW is intended with settings for particular slots. The antenna is constructed on Rogers RT5880 (lossy) with 2.2 dielectric constant, l.27 mm thickness, and 0.0009 loss tangent. It is simulated in the programming of computer simulation technology (CST) Microwave Studio. The simulated results show that the SIW antenna resonates across 31 to 36 GHz bands, which means that this new antenna covers all applications within this range. The reflection coefficients in targeting range are below 10 dB. The antenna achieves good efficiency and gain with 80% and 8.87 dBi respectively.
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Two-section branch-line hybrid couplers based broadband transmit/receive switchIJECEIAES
This article introduces a broadband microstripline-based transmit/receive switch for 7-Tesla magnetic resonance imaging. The designed switch aims to handle a signal of multiple frequencies to/from a multi-tuned radio-frequency coil that resonates at frequencies corresponding to the speed of precession of a wide range of atomic X-nuclei, at the same time and without tuning. These include 1H, 23Na, 13C, 31P, 19F, and 7Li used in magnetic resonance spectroscopy as a measure to the existence of many diseases. The fundamental and third harmonic center frequencies of the switch are adjusted to resonate at two broadbands covering a wide range of atomic X-nuclei. Two section branch-line hybrid couplers with phase inverters are designed to build the broadband switch. The designed switch used the minimum trace widths of transmission lines that reveal a compact size without increasing the heat and then the loss beyond specific values. The couplers and the switch S-parameters exhibited good return loss (<-10 dB), high isolation (<-40 dB), less insertion loss (<1 dB) and two clear wide bands covering many atomic X-nuclei used in diagnosis, at the same time and without the need for any tuning circuit during operation.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
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AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE BIAISNG
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
DOI : 10.5121/vlsic.2014.5403 33
AN OPERATIONAL AMPLIFIER WITH
RECYCLING FOLDED CASCODE TOPOLOGY
AND ADAPTIVE BIAISNG
Saumya Vij1
, Anu Gupta2
and Alok Mittal3
1,2
Electrical and Electronics Engineering, BITS-Pilani, Pilani, Rajasthan, India
3
High Speed Links, STMicroelectronics, Greater Noida
ABSTRACT
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptive-
biasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
KEYWORDS
Recycling Folded Cascode, Operational Amplifier, slew rate, Adaptive biasing, Transconductance
1. INTRODUCTION
In high performance analog integrated circuits, such as switch-capacitor filters, delta-sigma
modulators and pipeline A/D converters, op amps with very high dc gain and high unity-gain
frequency are needed to meet both accuracy and fast settling requirements of the systems.
However, as CMOS design scales into low-power, low-voltage and short-channel CMOS process
regime, satisfying both of these aspects leads to contradictory demands, and becomes more and
more difficult, since the intrinsic gain of the devices is limited. [1]
In order to achieve high-gain, the folded cascode amplifier is often adopted as the first-stage of
two-stage amplifiers. Actually, in the deep-submicron CMOS technology, high-gain amplifiers
are difficult to be implemented because of the inherent low intrinsic gain of the standard threshold
voltage MOS transistors. At the same time, because of the reliability reasons in the deep-
submicron processes, the output swing of amplifier is severally restricted with the lower power
supply voltage. [2]
To efficiently increase operational amplifier’s gain and output swing, multi-stage fully-
differential operational amplifier topology is appreciated. The operational amplifier with three or
even more stages equipped with the Nested-Miller compensation or the Reversed Nested-Miller
compensation shows high efficiency in the gain enhancement, while they require additional large
compensation capacitors compared to the traditional two-stage operational amplifier, which will
lead to a larger die area and the limited slew rate. Besides, additional common mode feedback
(CMFB) circuits would consume additional power. [3]
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
34
This paper presents a novel idea of implementing recycling folded cascode [4] along with an
adaptive-biasing circuit[5] to achieve high gain, high bandwidth and high slew rate specifications.
Section 2 describes the proposed design. Section 3 analyzes the design and working of the circuit.
Implementation is discussed in section 4, simulations in section 5, followed by conclusion in
section 6.
2. PROPOSED STRUCTURE
The proposed design presented in this paper employees the recycling folded cascode along with
an adaptive bias current circuit. This single stage operational amplifier is capable of providing
high gain of around 70dB along with a high bandwidth of 250 MHz and a slew rate of around
100V/µs which is approximately twice as that of the recycling folded cascode without the
additional adaptive-biasing circuit.
Recycling folded cascode is basically a modified folded cascode where the load transistor also
acts as a driving transistor, hence, enhancing the current carrying capability of the circuit.
Recycling folded cascode is obtained by splitting the input transistors and the load transistors as
given in figure 1. The cross-over connections of these current mirrors ensure that the small signal
currents are added at the sources of M1, M2, M3 and M4 and are in phase.
This is called as recycling folded cascode (RFC), as it reuses/recycles the existing devices and
currents to perform an additional task of increasing the current driving capability of the circuit.
The proposed modification in the recycling folded cascode topology involves replacing the
transistor M0 with an adaptive-biasing circuit (figure 1) [5] which further enhances the current
driving capability of this circuit and hence the speed.
2.1 Adaptive Biasing Design
Adaptive biasing circuit consists of two level shifters and a current sources IB. They have a very
low output resistance (typically in the range of 20 – 100 ohms). Quiescent current in M1 and M2
is the well-controlled bias current IB of the level-shifter transistors assuming M1, M2, M1a and
M1b are matched.
Since the ac input signal is applied to both the gate and the source terminals of M1 and M2, the
transconductance of this input stage is twice as that of a conventional differential pair.
It is clear that for large Vin,d the output current increases with it, enhancing quadratically the
current boosting. The minimum supply voltage of this circuit is |VTH| + 3|VDS,sat| where |VDS,sat| is
the minimum |VDS| for operation in saturation region. For |VTH| = 0.7V and |VDS,sat| = 0.2 V, it
yields 1.3V. Hence, the circuit is suitable for low voltage operations.
3. ANALYSIS AND DESIGN OF THE PROPOSED STRUCTURE
3.1 Low Frequency Gain
The open loop gain of an operational amplifier determines the precision of the feedback systems
employing it. A high open loop gain is a necessity to suppress linearity [6]. The low frequency
gain of OTAs is frequently expressed as the product of the small signal transconductance, Gm
and the low frequency output impedance, Ro. The low frequency gain of the adaptive recycling
folded cascode is almost the same as that of the recycling folded cascode topology, i.e.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
35
RoARFC ≈ gm16r016 (ro4||ro10) || gm14ro14ro12 (1)
GmARFC ≈ GmRFC (=gm1(1+K) ) where K=3 (2)
Both the RFC and adaptive RFC (ARFC) have similar noise injection gains from either supply.
Although there is no discernable change in low frequency gain but extended bandwidth of the
adaptive RFC ensures high GBW. Moreover, the extended GBW of the adaptive RFC extends the
improved PSRR performance to higher frequencies than the RFC.
3.2 Phase Margin
The phase margin is often viewed as a good indicator to the transient response of an amplifier,
and is determined by the poles and zeros of the amplifier transfer function. The adaptive RFC
shares a dominant pole ωp1, determined by the output impedance and capacitive load and a non-
dominant pole ωp2, determined by the parasitic at the source of M15/M16. It has a pole-zero pair,
ωp3 and ωpz (= (K+1) ωp3), associated with the current mirrors M7:M8 and M9:M10. However,
this pole-zero pair is associated with NMOS devices, which puts it at a high frequency. In
addition, adaptive RFC also have a pole due to adaptive current source, ωp4. Due to low
Impedence at that node it is pushed to a high frequency.
Figure1. Schematic of the proposed design
The pole-zero values from the PZ analysis in cadence virtuoso have been tabulated in Table 1 and
Table 2. Also, their positioning with respect to each other is shown in figure 2.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
36
Table1. Pole Analysis
Pole Real Value
ωp1 -1.267e+05
ωp2 -3.551e+08
ωp3 -5.324e+08
ωp4 -9.908e+08
ωz -21.296e+08
Table 2. Zero Analysis
Pole Real Value
ωz -21.296e+08
Figure 2. Pole-zero analysis of the proposed design
3.3 Slew Rate
Slew rate is one of the most critical design aspects especially for the kind of circuits where high
speed is necessity. To achieve a high slew rate, adaptive biasing circuit plays a vital role. The
upper part of the proposed design [5] that is the adaptive biasing circuit consists of four matched
transistors M1, M2, M3 and M4 cross-coupled by two dc level shifters. Each level shifter is built
using two transistors (M1a, M2a and M1b, M2b) and a current source. These level shifters are called
Flipped Voltage Followers (FVFs). The dc level shifters must be able to source large currents
when the circuit is charging or discharging a large load capacitance. Moreover, they should be
simple due to noise, speed, and supply constraints.
Analysis of the proposed design shows that there is a significant improvement in its slew rate
over the RFC topology. Suppose Vin+ goes high, it follows that M1 and M2 turn off, which forces
M9 and M10 to turn off. Consequently, the drain voltage of M9 rises and M16 is turned off whereas
M3 is driven into deep triode. This directs current Id into M4 and in turn is mirrored by a factor of
3(K) (M7, M8) into M15, and again by a factor of 1 into (M11, M12). For simplicity, if we ignore
any parasitic capacitance at the sources of M1,2,3,4 and follow the similar derivation steps but
assuming Vin+ goes low, the result is symmetric slew rate expressed in (3)
SR (adaptive) RFC = 6Id/CL [4] (3)
We know that, Id = ID + id (4)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
37
Due to presence of the adaptive biasing circuit, this circuit changes current according to the input
voltage and hence remains self-biased. It also causes minimal increase in power dissipation as the
current only increase proportional to the voltage in one branch and correspondingly decreases in
the other one.
Since the ac input signal is applied to both the gate and the source terminals of M1,2 and M3,4, the
transconductance of this input stage is twice as that of a conventional differential pair.
The ac small-signal differential current of the input stage is
Id = i1-i2 ≈ (1 + ( gm2A.B roA,B -1)/(gm2A,B roA,B+1)) (5)
Clearly ac small signal current is twice as that in the case of RFC without adaptive biasing circuit.
Hence, Slew rate has improved in the proposed circuit.
Figure 3. Snapshot from Virtuoso of Proposed Design Schematic
4. IMPLEMENTATION
To validate the theoretical results, we first implemented the recycling folded cascode topology as
a benchmark for comparison with our proposed design. And then we simulated our own design
and compared the results with our implementation of the RFC. Table 3 details the transistor sizes
used in the implementation of the proposed structure as well as of our RFC implementation.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
38
Table 3. Device sizes in implementation
Device Proposed design RFC
Mo[4] - 60µm/500nm
M1a, M1b 100µm/500nm -
M2a, M2b 128µm/360nm -
M1, M2, M3, M4 64µm/360nm 64µm/360nm
M11, M12 64µm/360nm 70µm/500nm
M13, M14 64µm/360nm 84µm/500nm
M5, M6 8µm/180nm 8µm/180nm
M15, M16 10µm/180nm 10µm/180nm
M7, M10 24µm/500nm 24µm/500nm
M8, M9 8µm/500nm 8µm/500nm
5. SIMULATION RESULTS
All the simulations were done on cadence virtuoso with 0.18 µm technology using a VDD of
1.8V. The load capacitance was taken to be 5.6pF for all the simulations.
Here is the procedure for all the simulations. First of all DC analysis was done to ensure
saturation for all transistors. After that, the AC analysis with differential input signal as 1VPP was
done to measure the gain, GBW, UGB and Phase margin. After the AC analysis, a transient
analysis was done to measure the slew rate and settling time (1%). For the transient analysis, the
input signal was given as a square pulse (as shown in figure 12) of amplitude 1V at 5MHz. The
results of the simulations are tabulated in Table 4 and Table 5. Table 6 details the bias currents in
all the transistors of the proposed structure implementation.
Table 4. Results comparison with RFC Implementation
Parameters
Proposed
structure (tt)
RFC simulation
DC Gain(dB) 68.48 71
UGB(MHz) 247.1 153
GBW(MHz) 335.5 172.26
Slew rate(V/µs) 92.8 67.4
Settling time (1%)(ns) 12.39 21.93
Phase Margin 26.3o
58.1o
Power Dissipation(mW) 2.493 2.18
I(total) (mA) 1.385 1.215
Capacitive load 5.6 pF 5.6 pF
Technology 0.18µm 0.18µm
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
39
Table 5. Result of proposed design at extreme corners
Parameters tt ff ss
DC Gain(dB) 68.48 63.83 66.3
UGB(MHz) 247.1 267.6 203.9
GBW(MHz) 335.5 352 280.27
Slew rate(V/µs) 92.8 134.4 71.4
Settling time
(1%)(ns)
12.39 8.9 17.25
Phase Margin 26.3o
34.9o
25.2o
Power
Dissipation(mW)
2.493 3.334 2.049
I(total) (mA) 1.385 1.684 1.265
Capacitive load 5.6 pF 5.6 pF 5.6pF
Technology 0.18µm 0.18µm 0.18µm
Table 6. Bias Current in Proposed Structure
Device Ibias(µA) (tt)
M1a, M2a 181.1
M1b, M2b 86
M1, M4 48.79
M2, M3 46.29
M11, M12, M13, M14, M15, M16 90.63
M5, M6 46.29
M7, M10 139.4
M8, M9 46.29
The UGB of the proposed design is 247.1MHz while for RFC it is 153MHz showing a significant
increase in bandwidth as expected. The GBW has also increased from 172.26 MHz for RFC to
335.5 MHz for the proposed design. As proved theoretically, the slew rate has improved from
67.4V/µs to 92.8V/µs. Also, correspondingly, the settling time (1%) has decreased from 21.93 ns
to 12.39 ns showing an increase in the speed of the circuit significantly. Although the phase
margin has reduced but it can be dealt with by using a compensation capacitance when a second
stage is added to this design. Compensation capacitor will introduce a RHP zero in two stage op
Amp, which will cause serious issue. Hence RC compensation is a better choice, as it will allow
moving the zero away or forcing it in LHP. The most impressive aspect of this design is the fact
the increased speed and bandwidth is achieved with nearly the same power dissipation as the
RFC. The circuit has been implemented on all corners with all transistors in the saturation state.
Table III demonstrates the simulation results of the circuit in all corners i.e. tt, ss and ff.
Figure 4 shows the linear settling time response plotted during the transient analysis which was
used for the slew rate and settling time calculations. The open loop AC response of the amplifier
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
40
in tt, ff and ss corners is shown in figures 5, 6 and 7 respectively. Simulation graphs of settling
time calculation are shown in figure 8, 9 and 10.
Figure 4. Graph for calculating rate slew
Figure 5. Gain & Phase plot for tt case
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
41
Figure 6. Gain & Phase plot for ff corner
Figure 7. Gain & Phase plot for ss corner
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
42
Figure 8. Settling time calculation at ff corner
Figure 9. Settling time calculation at tt
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
43
Figure 10. Settling time calculation at ss corner
5.1 Operational Amplifier as a Voltage Follower
The proposed design was implemented with a negative feedback in a voltage follower
configuration (shown in figure 11) to test the stability of the design. An input pulse of 1V was
given at 5MHz to check its response and functioning. Figure 9 below shows the input and output
pulses in a voltage follower configuration. It is evident from the output graph that the delay
introduced by the voltage follower is very small. Also, a distortion less and non-sluggish output is
achieved as a result of high slew rate and bandwidth provided by the ARFC.
Due to high slew rate and bandwidth characteristics, ARFC finds application in various other
speed critical circuits such as switched capacitor circuits, comparators etc.
Figure 11. Voltage follower
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
44
Figure 12. Transient Response in a voltage follower
7. FUTURE WORK
Figure 13. Preliminary layout of the proposed design
Figure 13 shows the preliminary layout that has been implemented for the proposed design. The
future work for this research includes the optimization of the layout. Once an efficient layout is
achieved with better routing and placement, the target will be to achieve a robust design. In the
final stage, the design will be implemented on silicon.
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
45
From the design perspective, this design can be improved in terms of GBW by introducing a
second stage. We can also implement compensation technique (in this case RC compensation) to
improve the phase margin.
Other than focusing on solving the previous challenges, we aim to implement and test this
topology for other technology such as 40nm etc. as this design is scaling independent (up to some
extent).
8. CONCLUSION
It has been demonstrated that the proposed design shows a significant improvement over the
conventional RFC in terms of UGB, GBW and slew rate with nearly the same power
consumption. The additional adaptive biasing circuit added to the RFC, not only improves its
speed and frequency response but also makes the circuit very adaptive to the changes in input
voltage and noise fluctuations. With the RFC itself having an adaptive load, this addition of a
self-adjusting current source makes it a very flexible, adaptive and self-biased circuit. This feature
of the circuit also helps reducing the power consumption by changing currents corresponding to
the changes in the input voltage. The theoretical results were confirmed with good agreement
with the simulation data.
ACKNOWLEDGEMENT
The authors would like to take this opportunity to thank BITS Pilani, Pilani Campus
Administration for providing them with the facilities and resources, which were required to
conduct the research for this paper.
REFERENCES
[1] SU Li QIU Yulin, “Design of a Fully Differential Gain-Boosted Folded-Cascode Op Amp with
Settling Performance Optimization” IEEE Conference Electronic Devices and Solid-State Circuits,
pp. 441 – 444, Dec 2005.
[2] Zhou Qianneng' , Li Hongjuan2, Duan Xiaozhong', and Yang Chong’, “A Two-Stage Amplifier with
the Recycling Folded Cascode Input-Stage and Feedforward Stage”Cross Strait Quad-Regional Radio
Science and Wireless Technology Conference (CSQRWC), vol. 2, , pp. 1557 – 1560, July 2011.
[3] Hong Chen, Vladimir Milovanovic, Horst Zimmermann “A High Speed Two-Stage Dual-Path
Operational Amplifier in 40nm Digital CMOS” Mixed Design of Integrated Circuits and Systems
(MIXDES) conference, pp. 198-202, May 2012
[4] Rida S. Assaad, Student Member, IEEE, and Jose Silva-Martinez, Senior Member, IEEE “The
Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier” IEEE J. solid-
state circuits, vol. 44, no. 9,pp. 2535 - 2542 September 2009.
[5] Antonio J. López-Martín, Member, IEEE, Sushmita Baswa, Jaime Ramirez-Angulo, Fellow, IEEE,
and Ramón González Carvajal, Senior Member, IEEE “Low-Voltage Super Class AB CMOS OTA
Cells With Very High Slew Rate and Power Efficiency” IEEE J. solid-state circuits, vol. 40, no. 5,
pp. 1068-1077, May 2009
[6] B. Razavi,Design of Analog CMOS Integerated Circuit.New York: McGraw-Hill, pp. 291-333, 2001.
[7] R. Assaad and J. Silva-Martinez, “Enhancing general performance of folded cascode amplifier by
recycling current,” IEE Electron. Lett., vol. 43, no. 23, Nov. 2007.
[8] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design., 2nd ed.Oxford, U.K.: 2002.
[9] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, pp. 210–213.
14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
46
AUTHORS
Saumya Vij
2014 Graduate in B.E.(Hons.) Electrical and Electronics Engineering and MSc(Hons.)
Economics, BITS Pilani. Currently working as an ASIC Design Engineer at NVidia Pvt.
Ltd., Bangalore
Anu gupta
Presently working as Associate Professor in the Electrical and Electronics Engineering
department of BITS, Pilani. Holds a post graduate degree in Physics from Delhi University,
which was followed up with M.E in Microelectronics from BITS, Pilani. In March 2003,
she obtained her PhD from BITS, Pilani, Rajasthan.
Alok Mittal
2013 Graduate in B.E(Hons.) Electrical and Electronics from BITS, Pilani. Currently
working as Analog Front End design engineer at ST Microelectronics in High speed Links,
NOIDA.