This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Power quality improvement using impedance network based invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A new structure of a wide band bridge power limiter IJECEIAES
In this work, new design and simulation of a microstrip power limiter based on Schottky diode is presented. The proposed circuit is a zero bias power limiter built by associating a transmission line in parallel to a four Schottky rectifier bridge circuit. The first circuit using a single stage rectifier is analyzed and simulated. To improve this single stage, a second and final limiter is designed with two stages rectifier. Simulation results for the final circuit show an ideal limiter behavior and good performance of limiting rate up to 20dB for a threshold input power varying from 5 dBm to 30 dBm. While insertion loss remains low at small signal.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Power quality improvement using impedance network based invertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A new structure of a wide band bridge power limiter IJECEIAES
In this work, new design and simulation of a microstrip power limiter based on Schottky diode is presented. The proposed circuit is a zero bias power limiter built by associating a transmission line in parallel to a four Schottky rectifier bridge circuit. The first circuit using a single stage rectifier is analyzed and simulated. To improve this single stage, a second and final limiter is designed with two stages rectifier. Simulation results for the final circuit show an ideal limiter behavior and good performance of limiting rate up to 20dB for a threshold input power varying from 5 dBm to 30 dBm. While insertion loss remains low at small signal.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
A unity power factor bridgeless isolated cuk converter fed brushless dc motor...LeMeniz Infotech
A unity power factor bridgeless isolated cuk converter fed brushless dc motor drive
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
IFB-244 Series is an ultra-fast auto-recovering solution to prevent and maintain fiber network communication during power loss.
The IFB-244 Series is an industrial-grade optical fiber bypass switch with built-in 4 duplex LC or SC connectors featuring 2-channel duplex or 4-channel simplex fiber connection with optical bypass function. The optical fiber ports support 100Gbps/40Gbps/10Gbps/1Gbps/100Mbps fiber connections. It automatically switches optic network traffic to prevent link failure during power loss. It also allows the local network switch to be replaced or removed without network downtime.
Contact us
Tel: +91-7875432180 Email: sales@bbcpl.in
Website: https://www.bbcpl.in
Development and Deployment of Saturated-Core Fault Current Limiters in Distri...Franco Moriconi
Zenergy Power has been developing an inductive-type of fault current limiter (FCL) for electric power grid applications. The FCL employs a magnetically saturating reactor concept which acts as a variable inductor in an electric circuit. In March 2009 Zenergy Power, with funding from the California Energy Commission and the U.S. Department of Energy (DOE), installed an FCL in the Avanti distribution circuit of Southern California Edison’s Shandin substation in San Bernardino, CA. Rated at 15 kV and 1,250 amperes steady-state, the “Avanti” device is the first superconductor FCL installed in a US utility. In January 2010, the “Avanti” device successfully limited its first series of real-world faults when the circuit experienced multiple single-phase and three-phase faults. After successfully validating the performance of a new “compact” saturated-core FCL, Zenergy Power received contracts to install a 12 kV, 1,250 amperes compact FCL in the CE Electric UK grid in early 2011 and a 138 kV, 1,300 amperes FCL at the Tidd substation of American Electric Power in late 2011.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
Here are the elements you need to get back again when your rankings went down. All these onsite and offsite factors are important in making your website rank.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
A unity power factor bridgeless isolated cuk converter fed brushless dc motor...LeMeniz Infotech
A unity power factor bridgeless isolated cuk converter fed brushless dc motor drive
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
IFB-244 Series is an ultra-fast auto-recovering solution to prevent and maintain fiber network communication during power loss.
The IFB-244 Series is an industrial-grade optical fiber bypass switch with built-in 4 duplex LC or SC connectors featuring 2-channel duplex or 4-channel simplex fiber connection with optical bypass function. The optical fiber ports support 100Gbps/40Gbps/10Gbps/1Gbps/100Mbps fiber connections. It automatically switches optic network traffic to prevent link failure during power loss. It also allows the local network switch to be replaced or removed without network downtime.
Contact us
Tel: +91-7875432180 Email: sales@bbcpl.in
Website: https://www.bbcpl.in
Development and Deployment of Saturated-Core Fault Current Limiters in Distri...Franco Moriconi
Zenergy Power has been developing an inductive-type of fault current limiter (FCL) for electric power grid applications. The FCL employs a magnetically saturating reactor concept which acts as a variable inductor in an electric circuit. In March 2009 Zenergy Power, with funding from the California Energy Commission and the U.S. Department of Energy (DOE), installed an FCL in the Avanti distribution circuit of Southern California Edison’s Shandin substation in San Bernardino, CA. Rated at 15 kV and 1,250 amperes steady-state, the “Avanti” device is the first superconductor FCL installed in a US utility. In January 2010, the “Avanti” device successfully limited its first series of real-world faults when the circuit experienced multiple single-phase and three-phase faults. After successfully validating the performance of a new “compact” saturated-core FCL, Zenergy Power received contracts to install a 12 kV, 1,250 amperes compact FCL in the CE Electric UK grid in early 2011 and a 138 kV, 1,300 amperes FCL at the Tidd substation of American Electric Power in late 2011.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
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Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
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A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Design of A Low Power Low Voltage CMOS OpampVLSICS Design
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um
technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2 ) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.
Comparison of CMOS Current Mirror Sourcesidescitation
The benefits of using good current sources in analog
signal conditioning circuit are well known. The objectives of
this paper are to built and compare the CMOS current mirror
sources fit for the desired applications. The current sources
are developed by using current mirror circuits fed from
identical input current source. A straightforward approach to
design and compare the current sources based on four
parameters is presented here. The current mirror, Cascode
current mirror and Wilson current mirror sources are
compared with output resistance, systematic gain error, input
voltage and minimum output voltage. The simulation results
are included in the paper and validated with the derived values.
The proposed current sources circuits have designed in 0.25μm
CMOS technology with the help of EDA tool Tanner V14.1.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Power Dissipation of VLSI Circuits and Modern Techniques of Designing Low Pow...IJSRD
This paper focus on the various sources of power dissipation in modern VLSI circuits. This paper also discuss the importance of designing low power VLSI circuits along with various techniques of power reduction and its advantages and disadvantages. It is basically a comparative study between various power reduction techniques in modern VLSI circuits.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Power quality improvement using impedance network based invertereSAT Journals
Abstract Inverters are suited for applications where DC supply is converted to AC signal with desired waveform & adequate quality of power. Recently proposed Trans Z –source inverters and T –source inverters characterize improved power quality with the help of coupled inductors with turn’s ratio higher than one. This paper presents the concept of LC network based inverter. The built in DC current blocking capacitors connected in series with transformer windings and therefore prevent the transformer core from saturation. The novel LC network based inverter topology proposed in this paper characterize available continuous input current which is the advantage compared to TZSI and TSI. Simulations have been carried out in PSIM platform and results are presented to validate the proposed topology of the inverter system. Index Terms: Power quality, LC network, Impedance source inverter, Boost control, Shoot through state.
Design of a Low Power Low Voltage CMOS Opamp VLSICS Design
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
Study of Low Voltage Cascode Current Mirror with Enhance Dynamic Rangeijsrd.com
The current mirror is one of most common building blocks both in analog and mixed mode VLSI circuits and the performance of analog structures largely depends on their characteristics. The current mirror can be used as an active element and as a biasing circuit. In this paper we study about the current mirror, cascode current mirror and different low voltage current mirror topology and study the literature survey. After that we study, analysis and design of convention Level shifted low voltage current mirror and TSPICE simulation technology. Presented analysis low voltage current mirror input –output characteristic, high output swing capability and wide input -output swing capabilities, suitable for low voltage operation and minimum power dissipation.
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A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUIT
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
DOI : 10.5121/vlsic.2013.4405 41
A NEW LOW VOLTAGE P-MOS BULK DRIVEN
CURRENT MIRROR CIRCUIT
Anuj Dugaya1
and Laxmi Kumre2
1
Department of Electronics and Communication Engineering, Maulana Azad National
Institute of Technology, Bhopal, India
akdugaya@gmail.com
2
Department of Electronics and Communication Engineering, Maulana Azad National
Institute of Technology, Bhopal, India
laxmikumre99@rediffmail.com
ABSTRACT
This work proposes a new low voltage current mirror circuit using bulk driven technique. Bulk driven
technique is used to reduce the threshold of PMOS used in low voltage current mirror circuits (LVCM).The
Proposed circuit consist of 4 PMOS and 5 NMOS. The proposed circuit operated at +0.85 V supply
voltage.The bandwidth of this circuit has also been enhanced using resistive compensation technique. The
proposed circuit has been simulated in Cadence Design Environment in UMC 180nm CMOS technology. A
transfer characteristic of the proposed circuit has been discussed. The proposed circuit find application in
low voltage and low power analog integrated circuits.
KEYWORDS
Low voltage, Current Mirror, Bulk driven.
1. INTRODUCTION
Advances in CMOS technology have made it feasible to design chips with high packaging
density, better performance and lower power consumption. To attain these goals, the size of the
CMOS devices has been scaled down to very small features and dimensions. However, the power
supply voltage has not been scaled down proportionally to ultra-deep sub-micron technology. The
limitation of low voltage circuit design using the existing technology is that the power supply
must be at least equal to the sum of the magnitude of the threshold voltages of cascaded P-MOS
and N-MOS transistors. There are several techniques, such as bulk-driven, sub-threshold, self
cascode, and floating-gate has been evolved to construct high performance analog circuits under
low power supply voltages. Figure 1 shows the symbols of current mirror circuits in which arrow
is used to show the direction of the current flow on the input side. The ratio 1: K shows the
current gain of the Current mirror circuit.
Figure 1 Current Mirror symbols (a) NMOS current mirror (b) PMOS current mirror.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
42
The bulk-driven technique is used to scale down the threshold voltage of PMOS transistor used in
circuit. The body terminal of PMOS is connected to input to provide weak positive bias so that
threshold voltage of PMOS is reduced and supply voltage is effectively scale down. This
technique is completely compatible with standard CMOS process.
Current mirror (CM) circuits are widely used in analog integrated circuit. It is clear from its name
that it copies the current. Current mirror are circuits whose output current is independent of
output terminal voltage and depends on input current only. They are used for current
amplification, biasing, active loading and level shifting. Efficient design of current mirror circuit
improves the overall performance of analog integrated circuit and reduces the supply voltage
requirement of the circuit.
2. PREVIOUSLY REPORTED CURRENT MIRROR CIRCUITS
2.1 Very Low Input impedance Low Power Current Mirror
In order to get low input impedance, the main idea is to introduce transistor M3 in series with the
input terminal of the basic circuit of the current mirror and use a gain amplifier of ‘−A’ gain to
control the gate voltage of M3. In Figure 2 (a) a simple current mirror is shown and in Figure 2 (b)
conceptual schematic of the current mirror. Any increase in source voltage of M3 (i.e. due to
injected input current) causes its gate voltage to decrease ‘−A’ times, hence causing stronger sink
of input current which results in decrease of input impedance by ‘A’ times.
Figure 2 (a) Simple current mirror (b) Conceptual schematic of the current mirror [4].
2.2 Self Cascode Current Mirror
As the device sizes are reducing the output impedance of the MOSFET is also reducing due to the
channel length modulation. For having high gains we need high output impedance of the devices
and short channel MOSFETs cannot provide high gain structures for which cascoding of
MOSFETs is the obvious technique. Cascode MOSFETs increase the gains but it decreases the
output signal swing as well. The technique is to use the self cascode structure which requires low
compliance voltages at output nodes as compare to regular cascode and provides high output
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
43
impedance to give high output gains. This approach has potential applications in low voltage
design.
A self-cascode is a 2-transistor structure which can easily be treated as a single composite
transistor. The composite structure has higher effective channel length and the effective output
conductance is much low. The lower transistor M1 is equivalent to a resistor, where value is input
dependant. For optimal operation, the W/L ratio of M2 must be greater than that of M1, i.e., m>l.
For the composite transistor, the effective trans-conductance is given as
Figure 4 Self Cascode Current mirror [6].
2.3 Multi Input Floating Gate Low Voltage Current Mirror
The Current Mirrors are basic elements for the design of low voltage circuits and many low
voltage current mirror circuits have been developed. Most of these circuits have low compliance
voltage at output node but many of them have high compliance voltage at the input node. There
are few circuits only which have low input and output compliance voltages. However they have
high offset current, thus limiting operating range. To increase their operating range, a technique
named as multiple inputs floating gate (MIFG) need to be examined.
In multi input floating gate current mirror circuit the threshold voltage of MOSFET is made
programmable with input current Iin .This can done by providing feedback of Iin which produce a
voltage proportional to the Iin. This is done by passing Iin through a resistor. The voltage drop is
high for high Iin while it will be low at low Iin. Hence the threshold voltage of the circuit is varied
in accordance with the requirement of the circuit.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
44
Figure 5 Multi input floating gate Current mirror [7].
In Figure 5, the threshold voltage of M1 is varied as per requirement of the circuit. For low value
of Iin threshold value is reduced and when Iin is high threshold voltage increases as per
requirement of the circuit.
2.4 Adaptive Biasing Low voltage current mirror
Figure 6 Adaptive biasing Current mirror structure [8].
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
45
In low voltage current mirror circuit, if Iin increases then Vin also increases. But this increase in
Vin can be compensated by increasing the value of Ibias. In adaptive biasing low voltage current
mirror circuit the supply voltage is reduced by increasing the biasing current so that circuit should
work at low voltage. Disadvantage of adaptive biasing is that there is always an offset current
flow through circuit even in absence of input current. Figure 6 shows adaptive biasing low
voltage structure.
3. PROPOSED LOW VOLTAGE CURRENT MIRROR CIRCUIT
3.1 Circuit Description
Figure 7 shows the proposed low-voltage current mirror circuit. In this proposed circuit the
transistors M4 and M5 are generating the bias current. At node 1, two currents i.e. input current
(Iin) and bias current (Ibias) are injecting in which the input current is transferred to the output
terminal (node 4).In accordance with KCL, the value of W/L of transistor M0 is chosen in such a
manner that the current (Iin + Ib) will flow through it. The gate-to-source voltages of transistors
M0 and M1 are equal hence; the same current (Iin + Ib) will flow through these transistors. Rest of
the transistors are used to copy the currents and transfer to the relevant nodes. Finally, the output
current (Iout) through transistor M8 is same as the input current (Iin).
The bulk terminal of P-MOS M4, M5, M6 and M7 are connected to input current circuit for
reducing the threshold voltage of P-MOS instead of connecting it supply Vdd. As a result of above
connection the supply voltage is effectively reduced to + 0.85 V.
Figure 7 Proposed Low Voltage Current Mirror Circuit.
In Figure 7 KCL at node 4, we get
Iout + Ib = Iin + Ib (1)
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
46
Now (1) reduces
Iout = Iin (2)
From (2), it is clear that the proposed circuit behaves as current mirror circuit. The Bulk terminal
of PMOS used in the circuit is connected to input current source so as to provide biasing of
PMOS. The current into bulk terminal is very small i.e. current necessary for biasing the PMOS.
The transconductance parameters and parasitic capacitances of the transistors are selected as
3.2 AC analysis of the proposed circuit.
In this section the AC analysis of the proposed current mirror circuit is discussed. The AC
equivalent model of the proposed circuit is shown in Figure 8
Figure 8 AC equivalent model of proposed current mirror
In this model, it is assumed that
From Figure 8, The output current Iout is
where gm8 is the transconductance of the transistor M8 and V0 is the output voltage.
Applying KCL at nodes 1, 2, 3 and 4 different expressions can be written as follows
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After simplification (6), (7), (8) and (9) reduces to (10), (11), (12) and (13) respectively as:
Substituting (11) and (12) in (13), the output voltage Vout is
Using (14) in (5), the output current Iout is
Dividing (15) by (10), the current gain is
The above relation can be written as:
The transconductance parameters and parasitic capacitances of the transistors are selected as
Using (17) in (16), (16) becomes
From (18), it is clear that the transfer function exhibits a dominant pole which
decide the bandwidth of the proposed circuit.
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3.3 Proposed current mirror circuit with enhanced bandwidth.
The bandwidth of the proposed circuit has been enhanced by customizing the circuit as shown in
Figure 9. In this circuit, a resistance R is connected between drain and gate terminals of the
transistor M0. The working of circuit is similar to first circuit. In this figure, the resistance (R)
connected between drain and gate terminals of the transistors M0 which create the potential
difference between two terminals.
Figure 9 Proposed current mirror circuit with enhanced bandwidth.
3.4 AC analysis of the proposed current mirror circuit with enhanced bandwidth.
In this section the AC analysis of the proposed circuit with enhanced bandwidth has been
performed and the AC equivalent model of this circuit is shown in Figure 10
Figure 10 AC equivalent model of enhanced bandwidth current mirror circuit
In this model, it is assumed that
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From Figure 10, The output current Iout is
where gm8 is the transconductance of the transistor M8 and V0 is the output voltage.
Applying KCL at nodes 1, 2, 3 and 4 different expressions can be written as follows
where gmi (i = 0 to 8) is the transconductance of the ith
transistor. Voltages V0, V1, V2 and V3 are
the voltages at nodes 0, 1, 2 and 3 respectively.
After simplification (21), (22), (23), (24) and (25) reduces to (26), (27), (28), (29) and (30)
respectively as:
Substituting (29) in (26), the input current Iin is
With further calculation (30), may be written as
Using (27) and (28) in (24), the output voltage Vout is
Substituting (32) in (20), the output current Iout is
Dividing (33) by (31), the current gain is
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The above relation can be written as:
The transconductance parameters and parasitic capacitances of the transistors are selected as
Using (36) in (35), (35) becomes
From (37), it is clear that the transfer function has two zeros and five poles. In (18), the transfer
function consist of one zero and four poles. Therefore, it is visible that the resistance R connected
between drain and gate of the transistor M0 proposes a zero and a pole in the transfer function of
Figure 9. This proposed zero cancels the dominant pole and therefore, the bandwidth of the
proposed circuit (Figure 7) is now improved.
The MOSFETs sizes in case of channel width to length ratio are listed in Table 1
Table 1 MOSFET Channel Width to length ratio
MOSFET W/L Ratio (µm)
M0 44.8/2.0
M1 44.8/2.0
M2 1.8/0.9
M3 1.8/0.9
M4 5.3/0.9
M5 5.3/0.9
M6 93.6/1.44
M7 93.6/1.44
M8 16.38/0.9
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4. SIMULATION RESULTS
4.1 Current Transfer characteristics.
The proposed current mirror is simulated using Cadence Design Environment in the UMC 180
nm CMOS Technology. This proposed current mirror circuit is operated with supply voltage of
+0.85 V. Figure 11 shows the current transfer characteristics of the proposed circuit and plots the
graph between output current and input current. The input current changes from 0 to 100 uA.
From the plot, it is seen that output current follow the input current with + 10% error in copying
current.
Figure 11 DC characteristics of the proposed current mirror circuit.
4.2 AC characteristics.
Figure 12 shows the frequency response of the proposed circuit. In this figure current gain versus
frequency graph is plotted. In the same figure, frequency response of the proposed current mirror
circuit with bandwidth enhancement resistor (R1=3.7K ) is also plotted. The bandwidths of the
proposed circuits without and with compensation resistor are 38 MHz and 92 MHz, respectively.
Figure 12 Frequency response of the proposed circuit.
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TABLE 2 Comparison of proposed current mirror with other reported current mirror.
Circuit Parameters Current mirror [4] Current mirror [1] Proposed current mirror
Power supply +1.5 V +1.3 V +0.85 V
CMOS Technology 180 nm 180nm 180nm
Input Current Range 0 to 100uA 0 to 100uA 0 to 100uA
Bandwidth 577MHz 163MHz 92MHz
5. CONCLUSION
This work presents a new low voltage current mirror circuit operating with a supply voltage of
+0.85 V. The proposed circuit can be used for wide variety of low voltage and low power
application. The bandwidth of the circuit has been enhanced using resistive compensation
technique. The mathematical analysis of the proposed low voltage current mirror has also been
presented.The simulation results have been presented to validate the usefulness of the proposed
current mirror circuit.
ACKNOWLEDGEMENTS
First of all, i am thankful to mrs. laxmi kumre, assistant professor, electronics and communication
engineering department, maulana azad national institute of technology, bhopal for his patient
guidance and support throughout this work.
I am thankful to entire faculty and staff electronics and communication engineering department.
Finally, i would like to thank my family and friends for standing by me through all the joys and
sorrows that life had to offer.
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AUTHORS
Anuj Dugaya received his B.E. degree in Electronics and Communication Engineering
from the Rajiv Gandhi Technical University, Bhopal, India in 2010, and currently
pursuimg M.Tech from Maulana Azad National Institute of Technology, Bhopal,
India. His current area of interest includes low power analog circuits.
Laxmi Kumre received her B.Tech Degree in Electronics and Communication
engineering in 1998, M.Tech Degree in Digital Communication in 2010 and currently
pursuing Ph.D in Low Power Digital System Design. She is working as Senior Assistant
Professor in D epartment of Electronics and Communication Engineering in MANIT,
BHOPAL. Her field of Interest are Low Power Digital Circuit Design Techniques,
VLSI Digital System design and Communication Systems. She is Fellow member of
IEEE, INDIA.