The document discusses a proposed new logic family called current-steering CMOS (CS-CMOS) that aims to reduce switching noise in mixed-signal systems.
[1] CS-CMOS is obtained through a simple modification to standard CMOS logic, adding a pair of complementary transistors to provide a constant bias current through the gate. This helps minimize noise generation during state transitions while keeping power consumption lower than other constant-current logic families.
[2] The static transfer characteristics of the CS-CMOS inverter are analyzed, showing it provides the same output high and low voltages as CMOS. Positive feedback is present due to the biasing transistors, leading to high gain during output transitions.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes a research paper that proposes low-leakage 1-bit full adder cell designs for reducing power consumption in nanometer technologies. It introduces two modified full adder circuit designs (Design1 and Design2) that apply transistor resizing and power gating techniques. Simulation results show that the proposed designs reduce standby leakage power and active power compared to a conventional 28-transistor CMOS full adder. Design1 sizes transistors with a 3.17x PMOS-to-NMOS ratio while Design2 uses a 1.5x ratio. Both aim to minimize area and leakage through optimized transistor widths and lengths.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
High performance domino full adder design under different body biased technologyIAEME Publication
This document presents the design and analysis of different body-biased domino full adder circuits at 150nm and 45nm technologies. Six different body biasing schemes are proposed and their performance is compared in terms of power consumption, delay, and noise. Simulation results show that connecting the NMOS substrate to its source and the PMOS substrate to the clock (SB6 biasing) provides the best performance with minimum power consumption and delay. This design is shown to be effective across both technology nodes, indicating technology independence. Overall, the document evaluates body biasing techniques for optimizing domino logic circuits at reduced technology scales.
This document summarizes research on gate leakage reduction techniques for deep submicron integrated circuits. It discusses how gate leakage has become a significant source of power dissipation as devices are scaled down, due to increased subthreshold leakage, gate oxide tunneling, and reverse bias junction leakage. The document then describes complementary pass transistor logic (CPL) and differential cascade voltage switch logic (DCVSL) as logic families that aim to reduce static power by using fewer transistors and eliminating inverters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document discusses the implementation of low power integrators and differentiators using memristors. It first provides background on memristors and describes the linear ion drift model used to model memristor behavior. It then shows circuit diagrams for traditional op-amp-based integrators and differentiators and their memristor-based counterparts. Transient analyses are performed and results show the memristor-based circuits provide significantly lower power dissipation in the nano-Watt range compared to milli-Watt ranges for traditional designs. Therefore, memristors allow for more compact and reliable analog circuit implementation with reduced power consumption.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document summarizes a research paper that proposes low-leakage 1-bit full adder cell designs for reducing power consumption in nanometer technologies. It introduces two modified full adder circuit designs (Design1 and Design2) that apply transistor resizing and power gating techniques. Simulation results show that the proposed designs reduce standby leakage power and active power compared to a conventional 28-transistor CMOS full adder. Design1 sizes transistors with a 3.17x PMOS-to-NMOS ratio while Design2 uses a 1.5x ratio. Both aim to minimize area and leakage through optimized transistor widths and lengths.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
High performance domino full adder design under different body biased technologyIAEME Publication
This document presents the design and analysis of different body-biased domino full adder circuits at 150nm and 45nm technologies. Six different body biasing schemes are proposed and their performance is compared in terms of power consumption, delay, and noise. Simulation results show that connecting the NMOS substrate to its source and the PMOS substrate to the clock (SB6 biasing) provides the best performance with minimum power consumption and delay. This design is shown to be effective across both technology nodes, indicating technology independence. Overall, the document evaluates body biasing techniques for optimizing domino logic circuits at reduced technology scales.
This document summarizes research on gate leakage reduction techniques for deep submicron integrated circuits. It discusses how gate leakage has become a significant source of power dissipation as devices are scaled down, due to increased subthreshold leakage, gate oxide tunneling, and reverse bias junction leakage. The document then describes complementary pass transistor logic (CPL) and differential cascade voltage switch logic (DCVSL) as logic families that aim to reduce static power by using fewer transistors and eliminating inverters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
This document discusses the implementation of low power integrators and differentiators using memristors. It first provides background on memristors and describes the linear ion drift model used to model memristor behavior. It then shows circuit diagrams for traditional op-amp-based integrators and differentiators and their memristor-based counterparts. Transient analyses are performed and results show the memristor-based circuits provide significantly lower power dissipation in the nano-Watt range compared to milli-Watt ranges for traditional designs. Therefore, memristors allow for more compact and reliable analog circuit implementation with reduced power consumption.
Fea of pcb multilayer stack up high voltage planar transformer for aerospace...elelijjournal
High voltage planar transformer is a technology which can replace conventional transformer with its distinct advantages of saturation and cost efficiency. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer
stack up of PCB Cu-tracks, producing High voltage power supply for aerospace application.With finite element analysis (FEA) simulations, different simulation outcomes are discussed for inspecting flux intensity and current density distribution with computing Electric field strength
and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines for
multilayer PCB stack up are discussed in this paper.
A current injection folded switch mixer for direct conversionIAEME Publication
1) The document discusses a current injection folded-switch mixer (CI-FSM) for direct conversion receivers in wireless applications.
2) CI-FSM is proposed to increase the conversion gain and reduce the noise figure of a folded switch mixer further. For comparison, a folded switch mixer (FSM) and CI-FSM are implemented in a 180nm CMOS process.
3) Simulation results show that the CI-FSM achieves a conversion gain higher by 2dB and noise figure lower by 1.0dB compared to the FSM, while maintaining similar linearity, at the cost of increased area.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
The document presents a model for estimating peak-to-peak switching noise along a vertical chain of power distribution through-silicon vias (TSVs) in a 3D stack of integrated circuits. The proposed model is accurate within 2-3% of a commercial simulator but runs 3-4 times faster and uses less memory. The model allows estimating switching noise at different locations in the stack to help determine decoupling capacitor placement and optimize the TSV pattern for power distribution. Simulation results are presented analyzing how switching noise varies with TSV dimensions, inductance, and decoupling capacitance.
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
Simulation and detection of transients on a 150kV HV Cable-paperThomas Mathew
This document discusses modeling a 150 kV underground high voltage cable in the Netherlands using the Universal Line Modeling technique. It provides background on the cable, describing its construction and specifications. It also reviews different modeling techniques and explains why the Universal Line Modeling technique was chosen to model the frequency dependent behavior of the cable and study partial discharges and transients occurring on it. The goal is to better understand the cable's insulation degradation over time.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
High Efficiency LDMOS Technology for UMTS base stations_journalSteven Theeuwen
This document summarizes the tradeoffs between linearity, gain, and efficiency that can be made for state-of-the-art LDMOS technology used in base station RF power amplifiers. It describes optimizations made to the LDMOS structure including a stepped shield and highly doped drain region that improved efficiency by 7% under two-carrier WCDMA conditions while maintaining linearity and increasing power gain by 1 dB. Further optimizations could increase device efficiencies above 30% and power gain by over 2 dB. The presented technology also enhances reliability by allowing higher operating temperatures.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This document summarizes the results of simulating a two-stage 130nm RF CMOS power amplifier designed for 2.4GHz applications. The power amplifier was simulated with variations in supply voltage from 1V to 5V and size of the second stage transistor from 150um to 500um. Supply voltage significantly impacted output power, ranging from 10.684dBm to 25.08dBm at 1dB compression point. Transistor size also impacted output power but to a lesser degree, from 15.47dBm to 20.338dBm. Power added efficiency was maximized at intermediate supply voltages and transistor sizes, from 16.65% to 48.46% and 29.085% to 45.439% respectively
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
TCAD Based Analysis of Gate Leakage Current for High-k Gate Stack MOSFETIDES Editor
Scaling of metal-oxide-semiconductor transistors
to smaller dimensions has been a key driving force in the IC
industry. This work analysis the gate leakage current behavior
of nano scale MOSFET based on TCAD simulation. The
Sentaurus Simulator simulates the high-k gate stack structure
of N-MOSFET for analysis purpose. The impact of interfacial
oxide thickness on the gate tunneling current has been
investigated as a function of gate voltages for a given equivalent
oxide thickness (EOT) of 1.0 nm. It was reported in the results
that interfacial oxide thickness plays an important role in
reducing the gate leakage current. It is also observed that high-
k stack gated MOSFET exhibits improved performance in term
of Off current and DIBL
Comparison of Wilkinson Power Divider And Gysel Power Divider Using Ads® For...cscpconf
Wilkinson Power Divider (WPD) and Gysel Power Divider(GPD) are two competing power
dividers and a simple comparison between them helps in choosing the technology for particular
application. In this paper, the performance of Wilkinson Power Divider and Gysel Power
Divider are analyzed based on the insertion loss, return loss, and also the isolation between the
output ports. The insertion loss and return loss of GPD is found to be lower about -3.061dB and
-13.754dB respectively when compared with WPD at a center frequency of 1.5GHz. These
losses of power dividers realized by microstrip line are analyzed with the operating frequency of
3GHz using ADS®
software.
1) Crosstalk noise in deep submicron circuits can destroy logic and introduce delay uncertainty, limiting circuit speed. Noise is modeled and analyzed to depend significantly on the ratio of driver strengths between adjacent wires.
2) Uniform driver strengths are proposed to limit peak noise between any pair of nets to around 25% of the supply voltage, avoiding logic errors. A capacitance management policy breaks high fanout nets into buffered trees to make capacitances uniform.
3) An experimental design flow is presented to synthesize circuits using a uniform driver strength matched to typical capacitance. Results show this reduces delay uncertainty compared to post-layout corrections.
1) The paper discusses insulation coordination challenges for Gas Insulated Switchgear (GIS) substations connected to overhead lines via underground cables. Short cable lengths complicate insulation practices due to fast front transients from lightning and switching.
2) A literature review found that GIS failure rates increase with voltage level, with 61% of failures from nominal voltage and 39% from overvoltage. Only one failure was reported due to lightning.
3) The paper reports on modeling work to examine factors like cable length, tower footing resistance, and surge arrester placement that influence transient overvoltages and the effectiveness of mitigation methods. Preliminary results suggest surge arresters and low tower footing resistance are effective at controlling overvoltages.
An empirical large signal model for rf ldmosfet transistorsIAEME Publication
This document presents an empirical large signal model for LDMOSFET transistors. The model is derived from small signal measurements of the transistor's transconductance, output conductance, and gate-source capacitance. Polynomial expressions are fitted to the measured data. A 2.5 GHz, 10 W power amplifier was designed using the model in simulation software. Measurements of the amplifier's output power, gain, efficiency, and drain current match well with simulations, validating the accuracy of the large signal model.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This document presents the design and implementation of a full adder cell using a high-performance CMOS technology to improve speed and reduce power consumption. It begins with an introduction to CMOS technology and enhancements. It then discusses the design and architecture of a traditional full adder before proposing a new design using CMOS transistors. Simulation results show the proposed design has lower power consumption of around 100 microwatts, a 35% reduction compared to the existing design. The document concludes that reducing supply voltage is an effective way to lower power dissipation for low-performance applications like sensor networks.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
This document presents a study on implementing an extremely low power fifth-order FIR digital filter using sub-threshold source coupled logic (STSCL) in a 45nm CMOS process. STSCL allows logic gates to operate at sub-threshold voltage levels, enabling significantly lower power consumption compared to traditional CMOS implementations. The paper designs basic logic gates like XOR, OR, AND in STSCL. A fifth-order FIR filter with transposed direct form structure is implemented using the STSCL gates, with five-bit canonic signed digit multipliers for coefficient multiplication. Simulation results show the STSCL-based FIR filter achieves lower power-delay product than a comparable CMOS implementation, demonstrating the potential for STS
The document discusses the need for low power VLSI circuit design. Portable devices require low power consumption to extend battery life as battery energy density is still limited. Reducing power is also important for reliability and cooling complex high performance chips. Power in CMOS circuits has three main components - dynamic switching power when nodes charge and discharge, short circuit power during transitions, and leakage power even when static. Dynamic power depends on load capacitance, supply voltage, and switching activity. Lowering voltage significantly reduces dynamic power but increases delay.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Fea of pcb multilayer stack up high voltage planar transformer for aerospace...elelijjournal
High voltage planar transformer is a technology which can replace conventional transformer with its distinct advantages of saturation and cost efficiency. This paper includes, study and solution methods for PCB winding configuration in planar magnetic elements with multilayer
stack up of PCB Cu-tracks, producing High voltage power supply for aerospace application.With finite element analysis (FEA) simulations, different simulation outcomes are discussed for inspecting flux intensity and current density distribution with computing Electric field strength
and Magnetic fields. In principal conclusion of study, complete analysis and some practical design guidelines for
multilayer PCB stack up are discussed in this paper.
A current injection folded switch mixer for direct conversionIAEME Publication
1) The document discusses a current injection folded-switch mixer (CI-FSM) for direct conversion receivers in wireless applications.
2) CI-FSM is proposed to increase the conversion gain and reduce the noise figure of a folded switch mixer further. For comparison, a folded switch mixer (FSM) and CI-FSM are implemented in a 180nm CMOS process.
3) Simulation results show that the CI-FSM achieves a conversion gain higher by 2dB and noise figure lower by 1.0dB compared to the FSM, while maintaining similar linearity, at the cost of increased area.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
The document presents a model for estimating peak-to-peak switching noise along a vertical chain of power distribution through-silicon vias (TSVs) in a 3D stack of integrated circuits. The proposed model is accurate within 2-3% of a commercial simulator but runs 3-4 times faster and uses less memory. The model allows estimating switching noise at different locations in the stack to help determine decoupling capacitor placement and optimize the TSV pattern for power distribution. Simulation results are presented analyzing how switching noise varies with TSV dimensions, inductance, and decoupling capacitance.
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
Simulation and detection of transients on a 150kV HV Cable-paperThomas Mathew
This document discusses modeling a 150 kV underground high voltage cable in the Netherlands using the Universal Line Modeling technique. It provides background on the cable, describing its construction and specifications. It also reviews different modeling techniques and explains why the Universal Line Modeling technique was chosen to model the frequency dependent behavior of the cable and study partial discharges and transients occurring on it. The goal is to better understand the cable's insulation degradation over time.
This document summarizes the performance enhancement and characterization of a junctionless vertical slit field effect transistor (JLVeSFET). Key findings from simulations include:
1) The JLVeSFET shows an optimized subthreshold slope of 65mV/decade and OFF current of ~10-18A/μm for a 50nm radius device with a high-k dielectric.
2) Using a high-k dielectric (Si3N4) instead of SiO2 increases the Ion/Ioff ratio to ~1011 and reduces the subthreshold slope to 63mV/decade.
3) Increasing the gate doping concentration reduces the subthreshold slope slightly while increasing the Ion/
High Efficiency LDMOS Technology for UMTS base stations_journalSteven Theeuwen
This document summarizes the tradeoffs between linearity, gain, and efficiency that can be made for state-of-the-art LDMOS technology used in base station RF power amplifiers. It describes optimizations made to the LDMOS structure including a stepped shield and highly doped drain region that improved efficiency by 7% under two-carrier WCDMA conditions while maintaining linearity and increasing power gain by 1 dB. Further optimizations could increase device efficiencies above 30% and power gain by over 2 dB. The presented technology also enhances reliability by allowing higher operating temperatures.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This document summarizes the results of simulating a two-stage 130nm RF CMOS power amplifier designed for 2.4GHz applications. The power amplifier was simulated with variations in supply voltage from 1V to 5V and size of the second stage transistor from 150um to 500um. Supply voltage significantly impacted output power, ranging from 10.684dBm to 25.08dBm at 1dB compression point. Transistor size also impacted output power but to a lesser degree, from 15.47dBm to 20.338dBm. Power added efficiency was maximized at intermediate supply voltages and transistor sizes, from 16.65% to 48.46% and 29.085% to 45.439% respectively
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
TCAD Based Analysis of Gate Leakage Current for High-k Gate Stack MOSFETIDES Editor
Scaling of metal-oxide-semiconductor transistors
to smaller dimensions has been a key driving force in the IC
industry. This work analysis the gate leakage current behavior
of nano scale MOSFET based on TCAD simulation. The
Sentaurus Simulator simulates the high-k gate stack structure
of N-MOSFET for analysis purpose. The impact of interfacial
oxide thickness on the gate tunneling current has been
investigated as a function of gate voltages for a given equivalent
oxide thickness (EOT) of 1.0 nm. It was reported in the results
that interfacial oxide thickness plays an important role in
reducing the gate leakage current. It is also observed that high-
k stack gated MOSFET exhibits improved performance in term
of Off current and DIBL
Comparison of Wilkinson Power Divider And Gysel Power Divider Using Ads® For...cscpconf
Wilkinson Power Divider (WPD) and Gysel Power Divider(GPD) are two competing power
dividers and a simple comparison between them helps in choosing the technology for particular
application. In this paper, the performance of Wilkinson Power Divider and Gysel Power
Divider are analyzed based on the insertion loss, return loss, and also the isolation between the
output ports. The insertion loss and return loss of GPD is found to be lower about -3.061dB and
-13.754dB respectively when compared with WPD at a center frequency of 1.5GHz. These
losses of power dividers realized by microstrip line are analyzed with the operating frequency of
3GHz using ADS®
software.
1) Crosstalk noise in deep submicron circuits can destroy logic and introduce delay uncertainty, limiting circuit speed. Noise is modeled and analyzed to depend significantly on the ratio of driver strengths between adjacent wires.
2) Uniform driver strengths are proposed to limit peak noise between any pair of nets to around 25% of the supply voltage, avoiding logic errors. A capacitance management policy breaks high fanout nets into buffered trees to make capacitances uniform.
3) An experimental design flow is presented to synthesize circuits using a uniform driver strength matched to typical capacitance. Results show this reduces delay uncertainty compared to post-layout corrections.
1) The paper discusses insulation coordination challenges for Gas Insulated Switchgear (GIS) substations connected to overhead lines via underground cables. Short cable lengths complicate insulation practices due to fast front transients from lightning and switching.
2) A literature review found that GIS failure rates increase with voltage level, with 61% of failures from nominal voltage and 39% from overvoltage. Only one failure was reported due to lightning.
3) The paper reports on modeling work to examine factors like cable length, tower footing resistance, and surge arrester placement that influence transient overvoltages and the effectiveness of mitigation methods. Preliminary results suggest surge arresters and low tower footing resistance are effective at controlling overvoltages.
An empirical large signal model for rf ldmosfet transistorsIAEME Publication
This document presents an empirical large signal model for LDMOSFET transistors. The model is derived from small signal measurements of the transistor's transconductance, output conductance, and gate-source capacitance. Polynomial expressions are fitted to the measured data. A 2.5 GHz, 10 W power amplifier was designed using the model in simulation software. Measurements of the amplifier's output power, gain, efficiency, and drain current match well with simulations, validating the accuracy of the large signal model.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This document presents the design and implementation of a full adder cell using a high-performance CMOS technology to improve speed and reduce power consumption. It begins with an introduction to CMOS technology and enhancements. It then discusses the design and architecture of a traditional full adder before proposing a new design using CMOS transistors. Simulation results show the proposed design has lower power consumption of around 100 microwatts, a 35% reduction compared to the existing design. The document concludes that reducing supply voltage is an effective way to lower power dissipation for low-performance applications like sensor networks.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
This document presents a study on implementing an extremely low power fifth-order FIR digital filter using sub-threshold source coupled logic (STSCL) in a 45nm CMOS process. STSCL allows logic gates to operate at sub-threshold voltage levels, enabling significantly lower power consumption compared to traditional CMOS implementations. The paper designs basic logic gates like XOR, OR, AND in STSCL. A fifth-order FIR filter with transposed direct form structure is implemented using the STSCL gates, with five-bit canonic signed digit multipliers for coefficient multiplication. Simulation results show the STSCL-based FIR filter achieves lower power-delay product than a comparable CMOS implementation, demonstrating the potential for STS
The document discusses the need for low power VLSI circuit design. Portable devices require low power consumption to extend battery life as battery energy density is still limited. Reducing power is also important for reliability and cooling complex high performance chips. Power in CMOS circuits has three main components - dynamic switching power when nodes charge and discharge, short circuit power during transitions, and leakage power even when static. Dynamic power depends on load capacitance, supply voltage, and switching activity. Lowering voltage significantly reduces dynamic power but increases delay.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Analog and digital circuit design in 65 nm CMOS end of the road.docxZHKhan15
This document summarizes challenges in analog and digital circuit design for 65nm CMOS technology. It discusses how leakage currents, process variability, and interconnect delays increase as technologies scale down, posing new problems. A panel of experts will discuss whether 65nm marks the "end of the road" for continued design benefits from technology scaling or if issues can be addressed.
Crosstalk noise is a major concern for deep submicrometer VLSI circuits due to increased capacitive coupling between wires. This document proposes considering crosstalk noise effects earlier in the design flow, during logic synthesis, before detailed layout information is available. It analyzes how noise is affected by basic circuit parameters like driver strength. Uniform driver strengths are shown to limit crosstalk effectively. The paper then proposes a noise-aware design flow to control driver strength ratios during synthesis. Experiments applying this flow to processor blocks show it can reduce timing uncertainty from up to 18% to below 3% of clock cycle time, with area/power penalties under 20%.
Data transmission with gbits speed using cmos based integrated circuIAEME Publication
The document discusses technologies for high-speed data transmission using optoelectronic integrated circuits. It describes how optical communication systems can be improved by increasing bit rates and wavelength counts to better utilize fiber bandwidth. This requires suitable device structures and driving electronics that can operate at gigabit per second speeds. The document then discusses requirements for these optoelectronic interface ICs, including high gain over broad bandwidths, low power consumption, and small chip area. It analyzes transmitter and receiver designs that use techniques like distributed amplification and multi-stage transimpedance amplifiers to achieve high performance optical data transmission.
Data transmission with gbits speed using cmos based integrated circuIAEME Publication
This document discusses data transmission using integrated circuits for optoelectronic interfaces. It describes how optical communication performance can be enhanced by increasing bit rates and wavelength counts to better utilize fiber bandwidth. This requires suitable optoelectronic transducer devices and driving electronics that can operate at gigabit speeds using low-voltage CMOS technology. A new pre-amplifier circuit implemented in 0.18um CMOS is presented, demonstrating a 3.5GHz bandwidth and 66dB trans-impedance gain using 0.3pF photodiodes. The circuit uses inductive peaking and negative differential feedback to boost bandwidth while reducing component values.
A NOVEL POWER REDUCTION TECHNIQUE FOR DUAL-THRESHOLD DOMINO LOGIC IN SUB-65NM...VLSICS Design
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combinationin 65nm dual- threshold footerless domino circuit for reduced leakage current. In this technique a p-type and an n-type leakage controlled transistor (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current which becomes dominant in nanometer technology. Simulations based on 65nm BISM4 model for proposed domino circuits shows that CLIL (clock low and input low) and CHIH (clock high and input high) state is ineffective for lowering leakage current. The CLIH (clock low input high) state is only effective to suppress the leakage at low and high temperatures for
wide fan-in domino circuits but for AND gate CHIL (clock high input low) state is preferred to reduce the leakage current. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 39.6% to 57.9% and by 32.4% to 40.3% at low and high die temperatures respectively when compared to the standard dual-threshold voltage domino logic circuits.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
This document summarizes a research paper that proposes a new low-voltage, low-power regulated cascode current mirror circuit designed using floating gate MOS (FGMOS) transistors. The proposed circuit achieves a high output impedance of 1.125 teraohms, a current range of up to 1500 microamps, low power dissipation of 10.56 microwatts, and a bandwidth of 4.1 megahertz. Simulation results show that the circuit operates with a single 1.0 volt power supply and outperforms previous FGMOS current mirror designs in terms of power, supply voltage, and output characteristics.
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
Introduction gadgets have gained a lot of attention.pdfbkbk37
The document discusses the increasing need for ultra-low power electronic devices due to advances in mobile technology and the internet of things. It covers limitations in further reducing power consumption and scaling transistors according to Moore's Law. Transition metal dichalcogenides are discussed as a potential channel material for ultra-low power transistors due to their ability to achieve high ON/OFF ratios even at the monolayer level. The document also mentions using technology computer-aided design (TCAD) tools like the Quantum Transport Simulator to model and optimize new materials and device geometries.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
A new improved mcml logic for dpa resistant circuitsVLSICS Design
Security of electronic data remains the major conce
rn. The art of encryption to secure the data can be
achieved in various levels of abstraction. The choi
ce of the logic style in implementing the security
algorithms has greater significance, and it can enh
ance the ability of providing better resistance to
side
channel attacks. The static CMOS logic style is pro
ved to be prone to side channel power attacks. The
exploration of CMOS current mode logic style for re
sistance against these side channel attacks is disc
ussed
in this paper. Various characteristics of the curre
nt mode logic styles, which make it suitable for ma
king
DPA resistant circuits are explored. A new methodol
ogy of biasing the sleep transistors of (MOS curren
t
mode logic) MCML families is proposed. It uses pass
gate transistors for power-gating the circuits. Th
e
power variations of the proposed circuits are compa
red against the standard CMOS counterparts. Logic
gates such as XOR, NAND and AND gate structures of
MCML families and static CMOS are designed and
compared for the ability of side channel resistance
. A distributed arrangement of sleep transistors fo
r
reducing the static power dissipation in the logic
gates is also proposed, designed and analyzed. All
the
logic gates in MCML and CMOS were implemented using
standard 180 nm CMOS technology employing
Cadence® EDA tools.
ECE 6030 Device Electronics discusses advances in low-power electronics and internet-connected devices. As transistors continue to shrink according to Moore's law, new challenges have emerged like increased OFF current. The document discusses approaches to overcoming these challenges, including new materials like transition metal dichalcogenides and their use in ultra-low power transistors. Device and circuit simulation tools are also discussed as important for optimizing new device designs without costly fabrication.
The document describes a technique called Local Common Mode Feedback (LCMFB) that can be applied to operational transconductance amplifiers (OTAs) to improve their performance. Applying LCMFB to the conventional OTA structure provides significant increases in gain-bandwidth and slew rate without increasing static power consumption or requiring much additional silicon area. LCMFB works by connecting the gates of the OTA's active load transistors to a common node with matched resistors, forming a feedback loop that enhances the amplifier's characteristics and versatility. The proposed OTA architecture with LCMFB can achieve high slew rates and gain bandwidth needed for wireless applications while keeping low static power, addressing demands for improved performance in battery-powered systems.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Similar to Cs cmos a low-noise logic family for mixed signal (20)
Submission Deadline: 30th September 2022
Acceptance Notification: Within Three Days’ time period
Online Publication: Within 24 Hrs. time Period
Expected Date of Dispatch of Printed Journal: 5th October 2022
MODELING AND ANALYSIS OF SURFACE ROUGHNESS AND WHITE LATER THICKNESS IN WIRE-...IAEME Publication
White layer thickness (WLT) formed and surface roughness in wire electric discharge turning (WEDT) of tungsten carbide composite has been made to model through response surface methodology (RSM). A Taguchi’s standard Design of experiments involving five input variables with three levels has been employed to establish a mathematical model between input parameters and responses. Percentage of cobalt content, spindle speed, Pulse on-time, wire feed and pulse off-time were changed during the experimental tests based on the Taguchi’s orthogonal array L27 (3^13). Analysis of variance (ANOVA) revealed that the mathematical models obtained can adequately describe performance within the parameters of the factors considered. There was a good agreement between the experimental and predicted values in this study.
A STUDY ON THE REASONS FOR TRANSGENDER TO BECOME ENTREPRENEURSIAEME Publication
The study explores the reasons for a transgender to become entrepreneurs. In this study transgender entrepreneur was taken as independent variable and reasons to become as dependent variable. Data were collected through a structured questionnaire containing a five point Likert Scale. The study examined the data of 30 transgender entrepreneurs in Salem Municipal Corporation of Tamil Nadu State, India. Simple Random sampling technique was used. Garrett Ranking Technique (Percentile Position, Mean Scores) was used as the analysis for the present study to identify the top 13 stimulus factors for establishment of trans entrepreneurial venture. Economic advancement of a nation is governed upon the upshot of a resolute entrepreneurial doings. The conception of entrepreneurship has stretched and materialized to the socially deflated uncharted sections of transgender community. Presently transgenders have smashed their stereotypes and are making recent headlines of achievements in various fields of our Indian society. The trans-community is gradually being observed in a new light and has been trying to achieve prospective growth in entrepreneurship. The findings of the research revealed that the optimistic changes are taking place to change affirmative societal outlook of the transgender for entrepreneurial ventureship. It also laid emphasis on other transgenders to renovate their traditional living. The paper also highlights that legislators, supervisory body should endorse an impartial canons and reforms in Tamil Nadu Transgender Welfare Board Association.
BROAD UNEXPOSED SKILLS OF TRANSGENDER ENTREPRENEURSIAEME Publication
Since ages gender difference is always a debatable theme whether caused by nature, evolution or environment. The birth of a transgender is dreadful not only for the child but also for their parents. The pain of living in the wrong physique and treated as second class victimized citizen is outrageous and fully harboured with vicious baseless negative scruples. For so long, social exclusion had perpetuated inequality and deprivation experiencing ingrained malign stigma and besieged victims of crime or violence across their life spans. They are pushed into the murky way of life with a source of eternal disgust, bereft sexual potency and perennial fear. Although they are highly visible but very little is known about them. The common public needs to comprehend the ravaged arrogance on these insensitive souls and assist in integrating them into the mainstream by offering equal opportunity, treat with humanity and respect their dignity. Entrepreneurship in the current age is endorsing the gender fairness movement. Unstable careers and economic inadequacy had inclined one of the gender variant people called Transgender to become entrepreneurs. These tiny budding entrepreneurs resulted in economic transition by means of employment, free from the clutches of stereotype jobs, raised standard of living and handful of financial empowerment. Besides all these inhibitions, they were able to witness a platform for skill set development that ignited them to enter into entrepreneurial domain. This paper epitomizes skill sets involved in trans-entrepreneurs of Thoothukudi Municipal Corporation of Tamil Nadu State and is a groundbreaking determination to sightsee various skills incorporated and the impact on entrepreneurship.
DETERMINANTS AFFECTING THE USER'S INTENTION TO USE MOBILE BANKING APPLICATIONSIAEME Publication
The banking and financial services industries are experiencing increased technology penetration. Among them, the banking industry has made technological advancements to better serve the general populace. The economy focused on transforming the banking sector's system into a cashless, paperless, and faceless one. The researcher wants to evaluate the user's intention for utilising a mobile banking application. The study also examines the variables affecting the user's behaviour intention when selecting specific applications for financial transactions. The researcher employed a well-structured questionnaire and a descriptive study methodology to gather the respondents' primary data utilising the snowball sampling technique. The study includes variables like performance expectations, effort expectations, social impact, enabling circumstances, and perceived risk. Each of the aforementioned variables has a major impact on how users utilise mobile banking applications. The outcome will assist the service provider in comprehending the user's history with mobile banking applications.
ANALYSE THE USER PREDILECTION ON GPAY AND PHONEPE FOR DIGITAL TRANSACTIONSIAEME Publication
Technology upgradation in banking sector took the economy to view that payment mode towards online transactions using mobile applications. This system enabled connectivity between banks, Merchant and user in a convenient mode. there are various applications used for online transactions such as Google pay, Paytm, freecharge, mobikiwi, oxygen, phonepe and so on and it also includes mobile banking applications. The study aimed at evaluating the predilection of the user in adopting digital transaction. The study is descriptive in nature. The researcher used random sample techniques to collect the data. The findings reveal that mobile applications differ with the quality of service rendered by Gpay and Phonepe. The researcher suggest the Phonepe application should focus on implementing the application should be user friendly interface and Gpay on motivating the users to feel the importance of request for money and modes of payments in the application.
VOICE BASED ATM FOR VISUALLY IMPAIRED USING ARDUINOIAEME Publication
The prototype of a voice-based ATM for visually impaired using Arduino is to help people who are blind. This uses RFID cards which contain users fingerprint encrypted on it and interacts with the users through voice commands. ATM operates when sensor detects the presence of one person in the cabin. After scanning the RFID card, it will ask to select the mode like –normal or blind. User can select the respective mode through voice input, if blind mode is selected the balance check or cash withdraw can be done through voice input. Normal mode procedure is same as the existing ATM.
IMPACT OF EMOTIONAL INTELLIGENCE ON HUMAN RESOURCE MANAGEMENT PRACTICES AMONG...IAEME Publication
There is increasing acceptability of emotional intelligence as a major factor in personality assessment and effective human resource management. Emotional intelligence as the ability to build capacity, empathize, co-operate, motivate and develop others cannot be divorced from both effective performance and human resource management systems. The human person is crucial in defining organizational leadership and fortunes in terms of challenges and opportunities and walking across both multinational and bilateral relationships. The growing complexity of the business world requires a great deal of self-confidence, integrity, communication, conflict and diversity management to keep the global enterprise within the paths of productivity and sustainability. Using the exploratory research design and 255 participants the result of this original study indicates strong positive correlation between emotional intelligence and effective human resource management. The paper offers suggestions on further studies between emotional intelligence and human capital development and recommends for conflict management as an integral part of effective human resource management.
VISUALISING AGING PARENTS & THEIR CLOSE CARERS LIFE JOURNEY IN AGING ECONOMYIAEME Publication
Our life journey, in general, is closely defined by the way we understand the meaning of why we coexist and deal with its challenges. As we develop the "inspiration economy", we could say that nearly all of the challenges we have faced are opportunities that help us to discover the rest of our journey. In this note paper, we explore how being faced with the opportunity of being a close carer for an aging parent with dementia brought intangible discoveries that changed our insight of the meaning of the rest of our life journey.
A STUDY ON THE IMPACT OF ORGANIZATIONAL CULTURE ON THE EFFECTIVENESS OF PERFO...IAEME Publication
The main objective of this study is to analyze the impact of aspects of Organizational Culture on the Effectiveness of the Performance Management System (PMS) in the Health Care Organization at Thanjavur. Organizational Culture and PMS play a crucial role in present-day organizations in achieving their objectives. PMS needs employees’ cooperation to achieve its intended objectives. Employees' cooperation depends upon the organization’s culture. The present study uses exploratory research to examine the relationship between the Organization's culture and the Effectiveness of the Performance Management System. The study uses a Structured Questionnaire to collect the primary data. For this study, Thirty-six non-clinical employees were selected from twelve randomly selected Health Care organizations at Thanjavur. Thirty-two fully completed questionnaires were received.
Living in 21st century in itself reminds all of us the necessity of police and its administration. As more and more we are entering into the modern society and culture, the more we require the services of the so called ‘Khaki Worthy’ men i.e., the police personnel. Whether we talk of Indian police or the other nation’s police, they all have the same recognition as they have in India. But as already mentioned, their services and requirements are different after the like 26th November, 2008 incidents, where they without saving their own lives has sacrificed themselves without any hitch and without caring about their respective family members and wards. In other words, they are like our heroes and mentors who can guide us from the darkness of fear, militancy, corruption and other dark sides of life and so on. Now the question arises, if Gandhi would have been alive today, what would have been his reaction/opinion to the police and its functioning? Would he have some thing different in his mind now what he had been in his mind before the partition or would he be going to start some Satyagraha in the form of some improvement in the functioning of the police administration? Really these questions or rather night mares can come to any one’s mind, when there is too much confusion is prevailing in our minds, when there is too much corruption in the society and when the polices working is also in the questioning because of one or the other case throughout the India. It is matter of great concern that we have to thing over our administration and our practical approach because the police personals are also like us, they are part and parcel of our society and among one of us, so why we all are pin pointing towards them.
A STUDY ON TALENT MANAGEMENT AND ITS IMPACT ON EMPLOYEE RETENTION IN SELECTED...IAEME Publication
The goal of this study was to see how talent management affected employee retention in the selected IT organizations in Chennai. The fundamental issue was the difficulty to attract, hire, and retain talented personnel who perform well and the gap between supply and demand of talent acquisition and retaining them within the firms. The study's main goals were to determine the impact of talent management on employee retention in IT companies in Chennai, investigate talent management strategies that IT companies could use to improve talent acquisition, performance management, career planning and formulate retention strategies that the IT firms could use. The respondents were given a structured close-ended questionnaire with the 5 Point Likert Scale as part of the study's quantitative research design. The target population consisted of 289 IT professionals. The questionnaires were distributed and collected by the researcher directly. The Statistical Package for Social Sciences (SPSS) was used to collect and analyse the questionnaire responses. Hypotheses that were formulated for the various areas of the study were tested using a variety of statistical tests. The key findings of the study suggested that talent management had an impact on employee retention. The studies also found that there is a clear link between the implementation of talent management and retention measures. Management should provide enough training and development for employees, clarify job responsibilities, provide adequate remuneration packages, and recognise employees for exceptional performance.
ATTRITION IN THE IT INDUSTRY DURING COVID-19 PANDEMIC: LINKING EMOTIONAL INTE...IAEME Publication
Globally, Millions of dollars were spent by the organizations for employing skilled Information Technology (IT) professionals. It is costly to replace unskilled employees with IT professionals possessing technical skills and competencies that aid in interconnecting the business processes. The organization’s employment tactics were forced to alter by globalization along with technological innovations as they consistently diminish to remain lean, outsource to concentrate on core competencies along with restructuring/reallocate personnel to gather efficiency. As other jobs, organizations or professions have become reasonably more appropriate in a shifting employment landscape, the above alterations trigger both involuntary as well as voluntary turnover. The employee view on jobs is also afflicted by the COVID-19 pandemic along with the employee-driven labour market. So, having effective strategies is necessary to tackle the withdrawal rate of employees. By associating Emotional Intelligence (EI) along with Talent Management (TM) in the IT industry, the rise in attrition rate was analyzed in this study. Only 303 respondents were collected out of 350 participants to whom questionnaires were distributed. From the employees of IT organizations located in Bangalore (India), the data were congregated. A simple random sampling methodology was employed to congregate data as of the respondents. Generating the hypothesis along with testing is eventuated. The effect of EI and TM along with regression analysis between TM and EI was analyzed. The outcomes indicated that employee and Organizational Performance (OP) were elevated by effective EI along with TM.
INFLUENCE OF TALENT MANAGEMENT PRACTICES ON ORGANIZATIONAL PERFORMANCE A STUD...IAEME Publication
By implementing talent management strategy, organizations would have the option to retain their skilled professionals while additionally working on their overall performance. It is the course of appropriately utilizing the ideal individuals, setting them up for future top positions, exploring and dealing with their performance, and holding them back from leaving the organization. It is employee performance that determines the success of every organization. The firm quickly obtains an upper hand over its rivals in the event that its employees having particular skills that cannot be duplicated by the competitors. Thus, firms are centred on creating successful talent management practices and processes to deal with the unique human resources. Firms are additionally endeavouring to keep their top/key staff since on the off chance that they leave; the whole store of information leaves the firm's hands. The study's objective was to determine the impact of talent management on organizational performance among the selected IT organizations in Chennai. The study recommends that talent management limitedly affects performance. On the off chance that this talent is appropriately management and implemented properly, organizations might benefit as much as possible from their maintained assets to support development and productivity, both monetarily and non-monetarily.
A STUDY OF VARIOUS TYPES OF LOANS OF SELECTED PUBLIC AND PRIVATE SECTOR BANKS...IAEME Publication
Banking regulations act of India, 1949 defines banking as “acceptance of deposits for the purpose of lending or investment from the public, repayment on demand or otherwise and withdrawable through cheques, drafts order or otherwise”, the major participants of the Indian financial system are commercial banks, the financial institution encompassing term lending institutions. Investments institutions, specialized financial institution and the state level development banks, non banking financial companies (NBFC) and other market intermediaries such has the stock brokers and money lenders are among the oldest of the certain variants of NBFC and the oldest market participants. The asset quality of banks is one of the most important indicators of their financial health. The Indian banking sector has been facing severe problems of increasing Non- Performing Assets (NPAs). The NPAs growth directly and indirectly affects the quality of assets and profitability of banks. It also shows the efficiency of banks credit risk management and the recovery effectiveness. NPA do not generate any income, whereas, the bank is required to make provisions for such as assets that why is a double edge weapon. This paper outlines the concept of quality of bank loans of different types like Housing, Agriculture and MSME loans in state Haryana of selected public and private sector banks. This study is highlighting problems associated with the role of commercial bank in financing Small and Medium Scale Enterprises (SME). The overall objective of the research was to assess the effect of the financing provisions existing for the setting up and operations of MSMEs in the country and to generate recommendations for more robust financing mechanisms for successful operation of the MSMEs, in turn understanding the impact of MSME loans on financial institutions due to NPA. There are many research conducted on the topic of Non- Performing Assets (NPA) Management, concerning particular bank, comparative study of public and private banks etc. In this paper the researcher is considering the aggregate data of selected public sector and private sector banks and attempts to compare the NPA of Housing, Agriculture and MSME loans in state Haryana of public and private sector banks. The tools used in the study are average and Anova test and variance. The findings reveal that NPA is common problem for both public and private sector banks and is associated with all types of loans either that is housing loans, agriculture loans and loans to SMES. NPAs of both public and private sector banks show the increasing trend. In 2010-11 GNPA of public and private sector were at same level it was 2% but after 2010-11 it increased in many fold and at present there is GNPA in some more than 15%. It shows the dark area of Indian banking sector.
EXPERIMENTAL STUDY OF MECHANICAL AND TRIBOLOGICAL RELATION OF NYLON/BaSO4 POL...IAEME Publication
An experiment conducted in this study found that BaSO4 changed Nylon 6's mechanical properties. By changing the weight ratios, BaSO4 was used to make Nylon 6. This Researcher looked into how hard Nylon-6/BaSO4 composites are and how well they wear. Experiments were done based on Taguchi design L9. Nylon-6/BaSO4 composites can be tested for their hardness number using a Rockwell hardness testing apparatus. On Nylon/BaSO4, the wear behavior was measured by a wear monitor, pinon-disc friction by varying reinforcement, sliding speed, and sliding distance, and the microstructure of the crack surfaces was observed by SEM. This study provides significant contributions to ultimate strength by increasing BaSO4 content up to 16% in the composites, and sliding speed contributes 72.45% to the wear rate
ROLE OF SOCIAL ENTREPRENEURSHIP IN RURAL DEVELOPMENT OF INDIA - PROBLEMS AND ...IAEME Publication
The majority of the population in India lives in villages. The village is the back bone of the country. Village or rural industries play an important role in the national economy, particularly in the rural development. Developing the rural economy is one of the key indicators towards a country’s success. Whether it be the need to look after the welfare of the farmers or invest in rural infrastructure, Governments have to ensure that rural development isn’t compromised. The economic development of our country largely depends on the progress of rural areas and the standard of living of rural masses. Village or rural industries play an important role in the national economy, particularly in the rural development. Rural entrepreneurship is based on stimulating local entrepreneurial talent and the subsequent growth of indigenous enterprises. It recognizes opportunity in the rural areas and accelerates a unique blend of resources either inside or outside of agriculture. Rural entrepreneurship brings an economic value to the rural sector by creating new methods of production, new markets, new products and generate employment opportunities thereby ensuring continuous rural development. Social Entrepreneurship has the direct and primary objective of serving the society along with the earning profits. So, social entrepreneurship is different from the economic entrepreneurship as its basic objective is not to earn profits but for providing innovative solutions to meet the society needs which are not taken care by majority of the entrepreneurs as they are in the business for profit making as a sole objective. So, the Social Entrepreneurs have the huge growth potential particularly in the developing countries like India where we have huge societal disparities in terms of the financial positions of the population. Still 22 percent of the Indian population is below the poverty line and also there is disparity among the rural & urban population in terms of families living under BPL. 25.7 percent of the rural population & 13.7 percent of the urban population is under BPL which clearly shows the disparity of the poor people in the rural and urban areas. The need to develop social entrepreneurship in agriculture is dictated by a large number of social problems. Such problems include low living standards, unemployment, and social tension. The reasons that led to the emergence of the practice of social entrepreneurship are the above factors. The research problem lays upon disclosing the importance of role of social entrepreneurship in rural development of India. The paper the tendencies of social entrepreneurship in India, to present successful examples of such business for providing recommendations how to improve situation in rural areas in terms of social entrepreneurship development. Indian government has made some steps towards development of social enterprises, social entrepreneurship, and social in- novation, but a lot remains to be improved.
OPTIMAL RECONFIGURATION OF POWER DISTRIBUTION RADIAL NETWORK USING HYBRID MET...IAEME Publication
Distribution system is a critical link between the electric power distributor and the consumers. Most of the distribution networks commonly used by the electric utility is the radial distribution network. However in this type of network, it has technical issues such as enormous power losses which affect the quality of the supply. Nowadays, the introduction of Distributed Generation (DG) units in the system help improve and support the voltage profile of the network as well as the performance of the system components through power loss mitigation. In this study network reconfiguration was done using two meta-heuristic algorithms Particle Swarm Optimization and Gravitational Search Algorithm (PSO-GSA) to enhance power quality and voltage profile in the system when simultaneously applied with the DG units. Backward/Forward Sweep Method was used in the load flow analysis and simulated using the MATLAB program. Five cases were considered in the Reconfiguration based on the contribution of DG units. The proposed method was tested using IEEE 33 bus system. Based on the results, there was a voltage profile improvement in the system from 0.9038 p.u. to 0.9594 p.u.. The integration of DG in the network also reduced power losses from 210.98 kW to 69.3963 kW. Simulated results are drawn to show the performance of each case.
APPLICATION OF FRUGAL APPROACH FOR PRODUCTIVITY IMPROVEMENT - A CASE STUDY OF...IAEME Publication
Manufacturing industries have witnessed an outburst in productivity. For productivity improvement manufacturing industries are taking various initiatives by using lean tools and techniques. However, in different manufacturing industries, frugal approach is applied in product design and services as a tool for improvement. Frugal approach contributed to prove less is more and seems indirectly contributing to improve productivity. Hence, there is need to understand status of frugal approach application in manufacturing industries. All manufacturing industries are trying hard and putting continuous efforts for competitive existence. For productivity improvements, manufacturing industries are coming up with different effective and efficient solutions in manufacturing processes and operations. To overcome current challenges, manufacturing industries have started using frugal approach in product design and services. For this study, methodology adopted with both primary and secondary sources of data. For primary source interview and observation technique is used and for secondary source review has done based on available literatures in website, printed magazines, manual etc. An attempt has made for understanding application of frugal approach with the study of manufacturing industry project. Manufacturing industry selected for this project study is Mahindra and Mahindra Ltd. This paper will help researcher to find the connections between the two concepts productivity improvement and frugal approach. This paper will help to understand significance of frugal approach for productivity improvement in manufacturing industry. This will also help to understand current scenario of frugal approach in manufacturing industry. In manufacturing industries various process are involved to deliver the final product. In the process of converting input in to output through manufacturing process productivity plays very critical role. Hence this study will help to evolve status of frugal approach in productivity improvement programme. The notion of frugal can be viewed as an approach towards productivity improvement in manufacturing industries.
A MULTIPLE – CHANNEL QUEUING MODELS ON FUZZY ENVIRONMENTIAEME Publication
In this paper, we investigated a queuing model of fuzzy environment-based a multiple channel queuing model (M/M/C) ( /FCFS) and study its performance under realistic conditions. It applies a nonagonal fuzzy number to analyse the relevant performance of a multiple channel queuing model (M/M/C) ( /FCFS). Based on the sub interval average ranking method for nonagonal fuzzy number, we convert fuzzy number to crisp one. Numerical results reveal that the efficiency of this method. Intuitively, the fuzzy environment adapts well to a multiple channel queuing models (M/M/C) ( /FCFS) are very well.
Taking AI to the Next Level in Manufacturing.pdfssuserfac0301
Read Taking AI to the Next Level in Manufacturing to gain insights on AI adoption in the manufacturing industry, such as:
1. How quickly AI is being implemented in manufacturing.
2. Which barriers stand in the way of AI adoption.
3. How data quality and governance form the backbone of AI.
4. Organizational processes and structures that may inhibit effective AI adoption.
6. Ideas and approaches to help build your organization's AI strategy.
CAKE: Sharing Slices of Confidential Data on BlockchainClaudio Di Ciccio
Presented at the CAiSE 2024 Forum, Intelligent Information Systems, June 6th, Limassol, Cyprus.
Synopsis: Cooperative information systems typically involve various entities in a collaborative process within a distributed environment. Blockchain technology offers a mechanism for automating such processes, even when only partial trust exists among participants. The data stored on the blockchain is replicated across all nodes in the network, ensuring accessibility to all participants. While this aspect facilitates traceability, integrity, and persistence, it poses challenges for adopting public blockchains in enterprise settings due to confidentiality issues. In this paper, we present a software tool named Control Access via Key Encryption (CAKE), designed to ensure data confidentiality in scenarios involving public blockchains. After outlining its core components and functionalities, we showcase the application of CAKE in the context of a real-world cyber-security project within the logistics domain.
Paper: https://doi.org/10.1007/978-3-031-61000-4_16
Climate Impact of Software Testing at Nordic Testing DaysKari Kakkonen
My slides at Nordic Testing Days 6.6.2024
Climate impact / sustainability of software testing discussed on the talk. ICT and testing must carry their part of global responsibility to help with the climat warming. We can minimize the carbon footprint but we can also have a carbon handprint, a positive impact on the climate. Quality characteristics can be added with sustainability, and then measured continuously. Test environments can be used less, and in smaller scale and on demand. Test techniques can be used in optimizing or minimizing number of tests. Test automation can be used to speed up testing.
Best 20 SEO Techniques To Improve Website Visibility In SERPPixlogix Infotech
Boost your website's visibility with proven SEO techniques! Our latest blog dives into essential strategies to enhance your online presence, increase traffic, and rank higher on search engines. From keyword optimization to quality content creation, learn how to make your site stand out in the crowded digital landscape. Discover actionable tips and expert insights to elevate your SEO game.
GraphRAG for Life Science to increase LLM accuracyTomaz Bratanic
GraphRAG for life science domain, where you retriever information from biomedical knowledge graphs using LLMs to increase the accuracy and performance of generated answers
Let's Integrate MuleSoft RPA, COMPOSER, APM with AWS IDP along with Slackshyamraj55
Discover the seamless integration of RPA (Robotic Process Automation), COMPOSER, and APM with AWS IDP enhanced with Slack notifications. Explore how these technologies converge to streamline workflows, optimize performance, and ensure secure access, all while leveraging the power of AWS IDP and real-time communication via Slack notifications.
Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
Ocean lotus Threat actors project by John Sitima 2024 (1).pptxSitimaJohn
Ocean Lotus cyber threat actors represent a sophisticated, persistent, and politically motivated group that poses a significant risk to organizations and individuals in the Southeast Asian region. Their continuous evolution and adaptability underscore the need for robust cybersecurity measures and international cooperation to identify and mitigate the threats posed by such advanced persistent threat groups.
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
Cosa hanno in comune un mattoncino Lego e la backdoor XZ?Speck&Tech
ABSTRACT: A prima vista, un mattoncino Lego e la backdoor XZ potrebbero avere in comune il fatto di essere entrambi blocchi di costruzione, o dipendenze di progetti creativi e software. La realtà è che un mattoncino Lego e il caso della backdoor XZ hanno molto di più di tutto ciò in comune.
Partecipate alla presentazione per immergervi in una storia di interoperabilità, standard e formati aperti, per poi discutere del ruolo importante che i contributori hanno in una comunità open source sostenibile.
BIO: Sostenitrice del software libero e dei formati standard e aperti. È stata un membro attivo dei progetti Fedora e openSUSE e ha co-fondato l'Associazione LibreItalia dove è stata coinvolta in diversi eventi, migrazioni e formazione relativi a LibreOffice. In precedenza ha lavorato a migrazioni e corsi di formazione su LibreOffice per diverse amministrazioni pubbliche e privati. Da gennaio 2020 lavora in SUSE come Software Release Engineer per Uyuni e SUSE Manager e quando non segue la sua passione per i computer e per Geeko coltiva la sua curiosità per l'astronomia (da cui deriva il suo nickname deneb_alpha).
“An Outlook of the Ongoing and Future Relationship between Blockchain Technologies and Process-aware Information Systems.” Invited talk at the joint workshop on Blockchain for Information Systems (BC4IS) and Blockchain for Trusted Data Sharing (B4TDS), co-located with with the 36th International Conference on Advanced Information Systems Engineering (CAiSE), 3 June 2024, Limassol, Cyprus.
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
HCL Notes und Domino Lizenzkostenreduzierung in der Welt von DLAUpanagenda
Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-und-domino-lizenzkostenreduzierung-in-der-welt-von-dlau/
DLAU und die Lizenzen nach dem CCB- und CCX-Modell sind für viele in der HCL-Community seit letztem Jahr ein heißes Thema. Als Notes- oder Domino-Kunde haben Sie vielleicht mit unerwartet hohen Benutzerzahlen und Lizenzgebühren zu kämpfen. Sie fragen sich vielleicht, wie diese neue Art der Lizenzierung funktioniert und welchen Nutzen sie Ihnen bringt. Vor allem wollen Sie sicherlich Ihr Budget einhalten und Kosten sparen, wo immer möglich. Das verstehen wir und wir möchten Ihnen dabei helfen!
Wir erklären Ihnen, wie Sie häufige Konfigurationsprobleme lösen können, die dazu führen können, dass mehr Benutzer gezählt werden als nötig, und wie Sie überflüssige oder ungenutzte Konten identifizieren und entfernen können, um Geld zu sparen. Es gibt auch einige Ansätze, die zu unnötigen Ausgaben führen können, z. B. wenn ein Personendokument anstelle eines Mail-Ins für geteilte Mailboxen verwendet wird. Wir zeigen Ihnen solche Fälle und deren Lösungen. Und natürlich erklären wir Ihnen das neue Lizenzmodell.
Nehmen Sie an diesem Webinar teil, bei dem HCL-Ambassador Marc Thomas und Gastredner Franz Walder Ihnen diese neue Welt näherbringen. Es vermittelt Ihnen die Tools und das Know-how, um den Überblick zu bewahren. Sie werden in der Lage sein, Ihre Kosten durch eine optimierte Domino-Konfiguration zu reduzieren und auch in Zukunft gering zu halten.
Diese Themen werden behandelt
- Reduzierung der Lizenzkosten durch Auffinden und Beheben von Fehlkonfigurationen und überflüssigen Konten
- Wie funktionieren CCB- und CCX-Lizenzen wirklich?
- Verstehen des DLAU-Tools und wie man es am besten nutzt
- Tipps für häufige Problembereiche, wie z. B. Team-Postfächer, Funktions-/Testbenutzer usw.
- Praxisbeispiele und Best Practices zum sofortigen Umsetzen
OpenID AuthZEN Interop Read Out - AuthorizationDavid Brossard
During Identiverse 2024 and EIC 2024, members of the OpenID AuthZEN WG got together and demoed their authorization endpoints conforming to the AuthZEN API
Your One-Stop Shop for Python Success: Top 10 US Python Development Providersakankshawande
Simplify your search for a reliable Python development partner! This list presents the top 10 trusted US providers offering comprehensive Python development services, ensuring your project's success from conception to completion.
HCL Notes and Domino License Cost Reduction in the World of DLAUpanagenda
Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-and-domino-license-cost-reduction-in-the-world-of-dlau/
The introduction of DLAU and the CCB & CCX licensing model caused quite a stir in the HCL community. As a Notes and Domino customer, you may have faced challenges with unexpected user counts and license costs. You probably have questions on how this new licensing approach works and how to benefit from it. Most importantly, you likely have budget constraints and want to save money where possible. Don’t worry, we can help with all of this!
We’ll show you how to fix common misconfigurations that cause higher-than-expected user counts, and how to identify accounts which you can deactivate to save money. There are also frequent patterns that can cause unnecessary cost, like using a person document instead of a mail-in for shared mailboxes. We’ll provide examples and solutions for those as well. And naturally we’ll explain the new licensing model.
Join HCL Ambassador Marc Thomas in this webinar with a special guest appearance from Franz Walder. It will give you the tools and know-how to stay on top of what is going on with Domino licensing. You will be able lower your cost through an optimized configuration and keep it low going forward.
These topics will be covered
- Reducing license cost by finding and fixing misconfigurations and superfluous accounts
- How do CCB and CCX licenses really work?
- Understanding the DLAU tool and how to best utilize it
- Tips for common problem areas, like team mailboxes, functional/test users, etc
- Practical examples and best practices to implement right away