This document summarizes a research paper that proposes two novel hybrid full adders for use in low-power digital signal processing applications. The hybrid adders were designed using a combination of existing 14-transistor and modified Shannon full adder circuits in order to achieve high performance at low voltages. The adders were simulated using a 90nm technology and were found to have lower power consumption, operate at low voltages with good signal integrity, and have performance suitable for low-power, high-performance applications.
Power Optimized Multiplexer Based 1 Bit Full Adder Cell Using .18 µm CMOS Tec...iosrjce
In this paper, a multiplexer based 1 bit full adder cell using 10 transistors is reported ( MBFA-10T).
In addition to higher speed , low power and reduced transition activity, this design has no direct power supply
connections, results in reduced consumption of short circuit current. The design was implemented using
Cadence Virtuoso tools in 180-nm CMOS technology. Performance parameters like layout area, power delay
product(PDP), transistor count, average power and delay were compared with the existing logic design styles
like static CMOS logic, pass transistor logic( TFA-16T, 14 T) , transmission gate logic and so on. The intensive
simulation shows improved operation speeds and power savings compare to the conventional design styles.
For 1.8-V supply at 180-nm CMOS technology, the average power consumption (3.9230μW) ,delay (196.8ps)
,the power delay product (PDP) (0.772fJ) and lay out area(175.79 µm2) was found to be extremely low, when
compared with other potential design styles.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Low Power Full Adder using 9T Structureidescitation
In this paper, we propose a new 9T 1-bit full adder.
The main objective is full output voltage swing, low power
consumption and temperature sustainability. The proposed
design is more reliable in terms of power consumption, Power
Delay Product (PDP) and temperature sustainability as
compared to the existing full adder designs. The design has
been implemented 45nm technology on Tanner EDA Tool
version 13.0. The simulation results demonstrate the power
consumption, delay and power delay product at different input
voltages ranging 0.4V to 1.4V.
Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Power Optimized Multiplexer Based 1 Bit Full Adder Cell Using .18 µm CMOS Tec...iosrjce
In this paper, a multiplexer based 1 bit full adder cell using 10 transistors is reported ( MBFA-10T).
In addition to higher speed , low power and reduced transition activity, this design has no direct power supply
connections, results in reduced consumption of short circuit current. The design was implemented using
Cadence Virtuoso tools in 180-nm CMOS technology. Performance parameters like layout area, power delay
product(PDP), transistor count, average power and delay were compared with the existing logic design styles
like static CMOS logic, pass transistor logic( TFA-16T, 14 T) , transmission gate logic and so on. The intensive
simulation shows improved operation speeds and power savings compare to the conventional design styles.
For 1.8-V supply at 180-nm CMOS technology, the average power consumption (3.9230μW) ,delay (196.8ps)
,the power delay product (PDP) (0.772fJ) and lay out area(175.79 µm2) was found to be extremely low, when
compared with other potential design styles.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Low Power Full Adder using 9T Structureidescitation
In this paper, we propose a new 9T 1-bit full adder.
The main objective is full output voltage swing, low power
consumption and temperature sustainability. The proposed
design is more reliable in terms of power consumption, Power
Delay Product (PDP) and temperature sustainability as
compared to the existing full adder designs. The design has
been implemented 45nm technology on Tanner EDA Tool
version 13.0. The simulation results demonstrate the power
consumption, delay and power delay product at different input
voltages ranging 0.4V to 1.4V.
Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
5GHz MIMO System Power Amplifier design with Adaptive Feedforward Linearizati...Ahmed Nasser Agag
- In such transceiver system, we used power amplifier stage in transmitter section and polyphase filter (PPF) in local oscillator (LO) section
- Less linearity of power amplifier causes higher order intermodulation and consequently destroys orthogonality between subcarriers in OFDM signals.
- Phase error in quadrature LO signal causes crosstalk between I and Q signals and results unavoidable demodulation errors.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Comparative Study of Low Power Low Area Bypass Multipliers for Signal Process...IJERA Editor
This paper presents a comparative study of 1-dimensional bypassing multipliers on basis of delay, area and power. If we can reduce the power consumption of the multiplier block, then we can reduce the power consumption of various digital signal processing chips and communication systems. In 2-dimensional bypass multiplier is presented the effective analysis of Slices, Lut, Cost & area is achieved. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL using Xilinx 12.4 ISE. Results are showed and it is verified using the Spartan-3E and Synopsys respectively.
The rapid growth in the use of portable system has triggered the research effort in low power microelectronic. This is due to the fact that the battery technology is not increasing with the same pace as the microelectronics technology. Only a limited power is available for the mobile system. Therefore low power design has become a major design consideration. Modified Gate Diffusion Input (MGDI) is a low power design which is a modification of Gate Diffusion Input (GDI).GDI is the lowest design technique, which is suitable for designing fast, low power circuit using reduced number of transistor. The main drawback associated with GDI is that the bulk terminal is not properly biased thereby the circuit exhibits threshold drop and it can be fabricated only in Twin well CMOS or Silicon on Insulator (SOI) process. So to overcome this MGDI is introduced.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsTELKOMNIKA JOURNAL
Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore
power amplifiers are the most important parts of electronic circuits. This is why the designing of power
amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design
of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using
a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The
configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The
proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also
utilized for getting the good matching condition. The advanced design system (ADS) software is used for
design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent
power gain; is changed between 28.5 and 20 dB with an output power of 12.45dBm at 1dB compression
point. For the input reflection coefficient (S11) is varied between -20 and -42 dB. While the output reflection
coefficient (S22) is varied between -10 dB and -49 dB over the wide frequency band of 3.2-3.8 GHz.
Hardware Implementation of OFDM system to reduce PAPR using Selective Level M...IOSR Journals
Abstract : OFDM is a modulation as well as multiplexing technique which is widely used in various high speed mobile and wireless communication systems because of its capacity of ensuring high level robustness against interference. In this paper the design and implementation of OFDM system along with SLM implementation to reduce PAPR[6]is illustrated and a detailed simulation of the OFDM system with 16-QAM. OFDM transceiver is implemented using FPGA Spartan6 kit. The hardware results show a detailed study of RTL schematics and Test Bench. In this paper, the software simulation results show 2dB reduction in the peaks. Keywords - Field Programmable Gate Array, Matlab Simulink, Orthogonal Frequency Division Multiplexing , Peak-to-Average Power Ratio, Selective level Mapping and Xilinx
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Designijsrd.com
Trade-off is one of the main design parameters in the field of electronic circuit design. Whereas smaller electronics devices which use less hardware due to techniques like hardware multiplexing or due to smaller devices created due to techniques developed by nanotechnology and MEMS, are more appealing, a trade-off between area, power and speed is inevitable. This paper analyses the trade-off in the design of Wimax deinterleaver. The main aim is to reduce the hardware utilization in a deinterleaver but speed and power consumption are important parameters which cannot be overlooked.
5GHz MIMO System Power Amplifier design with Adaptive Feedforward Linearizati...Ahmed Nasser Agag
- In such transceiver system, we used power amplifier stage in transmitter section and polyphase filter (PPF) in local oscillator (LO) section
- Less linearity of power amplifier causes higher order intermodulation and consequently destroys orthogonality between subcarriers in OFDM signals.
- Phase error in quadrature LO signal causes crosstalk between I and Q signals and results unavoidable demodulation errors.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Comparative Study of Low Power Low Area Bypass Multipliers for Signal Process...IJERA Editor
This paper presents a comparative study of 1-dimensional bypassing multipliers on basis of delay, area and power. If we can reduce the power consumption of the multiplier block, then we can reduce the power consumption of various digital signal processing chips and communication systems. In 2-dimensional bypass multiplier is presented the effective analysis of Slices, Lut, Cost & area is achieved. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL using Xilinx 12.4 ISE. Results are showed and it is verified using the Spartan-3E and Synopsys respectively.
The rapid growth in the use of portable system has triggered the research effort in low power microelectronic. This is due to the fact that the battery technology is not increasing with the same pace as the microelectronics technology. Only a limited power is available for the mobile system. Therefore low power design has become a major design consideration. Modified Gate Diffusion Input (MGDI) is a low power design which is a modification of Gate Diffusion Input (GDI).GDI is the lowest design technique, which is suitable for designing fast, low power circuit using reduced number of transistor. The main drawback associated with GDI is that the bulk terminal is not properly biased thereby the circuit exhibits threshold drop and it can be fabricated only in Twin well CMOS or Silicon on Insulator (SOI) process. So to overcome this MGDI is introduced.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsTELKOMNIKA JOURNAL
Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore
power amplifiers are the most important parts of electronic circuits. This is why the designing of power
amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design
of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using
a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The
configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The
proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also
utilized for getting the good matching condition. The advanced design system (ADS) software is used for
design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent
power gain; is changed between 28.5 and 20 dB with an output power of 12.45dBm at 1dB compression
point. For the input reflection coefficient (S11) is varied between -20 and -42 dB. While the output reflection
coefficient (S22) is varied between -10 dB and -49 dB over the wide frequency band of 3.2-3.8 GHz.
Hardware Implementation of OFDM system to reduce PAPR using Selective Level M...IOSR Journals
Abstract : OFDM is a modulation as well as multiplexing technique which is widely used in various high speed mobile and wireless communication systems because of its capacity of ensuring high level robustness against interference. In this paper the design and implementation of OFDM system along with SLM implementation to reduce PAPR[6]is illustrated and a detailed simulation of the OFDM system with 16-QAM. OFDM transceiver is implemented using FPGA Spartan6 kit. The hardware results show a detailed study of RTL schematics and Test Bench. In this paper, the software simulation results show 2dB reduction in the peaks. Keywords - Field Programmable Gate Array, Matlab Simulink, Orthogonal Frequency Division Multiplexing , Peak-to-Average Power Ratio, Selective level Mapping and Xilinx
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Designijsrd.com
Trade-off is one of the main design parameters in the field of electronic circuit design. Whereas smaller electronics devices which use less hardware due to techniques like hardware multiplexing or due to smaller devices created due to techniques developed by nanotechnology and MEMS, are more appealing, a trade-off between area, power and speed is inevitable. This paper analyses the trade-off in the design of Wimax deinterleaver. The main aim is to reduce the hardware utilization in a deinterleaver but speed and power consumption are important parameters which cannot be overlooked.
This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and power delay product. We designed each of these techniques by using Spice simulation soft wares.
Design of High Speed Low Power 15-4 Compressor Using Complementary Energy Pat...CSCJournals
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high speed multiplication applications using single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The main advantage of this static adiabatic logic is the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits. The proposed Compressor uses bit sliced architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed Compressor is also centered around the design of a novel 5-3 Compressor that attempts to minimize the stage delays of a conventional 5-3 Compressor that is designed using single bit full adder and half adder architectures. Firstly, the performance characteristics of CEPAL 15-3 Compressor with 14 transistor and 10 transistor adder designs are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250 nm technology libraries. The results prove that CEPAL 14T 15-4 Compressor is 68.11% power efficient, 75.31% faster over its static CMOS counterpart.
A Low power and area efficient CLA adder design using Full swing GDI techniqueIJERA Editor
The low power VLSI design has an important role in designing of many electronic systems. While designing
any combinational or sequential circuits, the important parameters like power consumption, implementation
area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient
data path logic systems forms the largest areas of research in VLSI system design. This paper presents
a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI) technique. The proposed
CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard
CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI) logic style suffers from some practical
limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections.
These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing
restoration (SR) transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and
Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results
have shown a greater reduction in delay, power dissipation and area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational
transconductance amplifier (OTA) is one of the most important components of ADC. This paper presents a
new design of two stages OTA. The design incorporates Sleep insertion technique and leakage feedback current
approach for improving design parameters such as gain, and power as compared to earlier work. The design is
simulated in 0.18µm CMOS technology with supply voltage 1.8V.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
Efficient implementation of full adder for power analysis in cmos technologyIJARIIT
In recent days, the real-time application and fast arithmetic operations require highly efficient arithmetic hardware
architecture to improve the system performances. The adder plays a vital role in digital circuits, the earlier hardware
architecture using conventional CMOS and transmission logic gate based full adder design. Moreover, the techniques using
more number of transistors and consume larger power and delay so we proposed the techniques pass-transistor logic and
transmission gate based hybrid pass logic. The hybrid technique is used to reduce the number of the transistor, so the delay
and power consumption will be reduced when compared with the earlier techniques. The proposed technique design was
implemented using 16 transistors in 180nm CMOS technology and it consumes 8.2075nW power and the delay reduced to
5.0146ns.
A Novel Method for Prevention of Bandwidth Distributed Denial of Service AttacksIJERD Editor
Distributed Denial of Service (DDoS) Attacks became a massive threat to the Internet. Traditional
Architecture of internet is vulnerable to the attacks like DDoS. Attacker primarily acquire his army of Zombies,
then that army will be instructed by the Attacker that when to start an attack and on whom the attack should be
done. In this paper, different techniques which are used to perform DDoS Attacks, Tools that were used to
perform Attacks and Countermeasures in order to detect the attackers and eliminate the Bandwidth Distributed
Denial of Service attacks (B-DDoS) are reviewed. DDoS Attacks were done by using various Flooding
techniques which are used in DDoS attack.
The main purpose of this paper is to design an architecture which can reduce the Bandwidth
Distributed Denial of service Attack and make the victim site or server available for the normal users by
eliminating the zombie machines. Our Primary focus of this paper is to dispute how normal machines are
turning into zombies (Bots), how attack is been initiated, DDoS attack procedure and how an organization can
save their server from being a DDoS victim. In order to present this we implemented a simulated environment
with Cisco switches, Routers, Firewall, some virtual machines and some Attack tools to display a real DDoS
attack. By using Time scheduling, Resource Limiting, System log, Access Control List and some Modular
policy Framework we stopped the attack and identified the Attacker (Bot) machines
Hearing loss is one of the most common human impairments. It is estimated that by year 2015 more
than 700 million people will suffer mild deafness. Most can be helped by hearing aid devices depending on the
severity of their hearing loss. This paper describes the implementation and characterization details of a dual
channel transmitter front end (TFE) for digital hearing aid (DHA) applications that use novel micro
electromechanical- systems (MEMS) audio transducers and ultra-low power-scalable analog-to-digital
converters (ADCs), which enable a very-low form factor, energy-efficient implementation for next-generation
DHA. The contribution of the design is the implementation of the dual channel MEMS microphones and powerscalable
ADC system.
Influence of tensile behaviour of slab on the structural Behaviour of shear c...IJERD Editor
-A composite beam is composed of a steel beam and a slab connected by means of shear connectors
like studs installed on the top flange of the steel beam to form a structure behaving monolithically. This study
analyzes the effects of the tensile behavior of the slab on the structural behavior of the shear connection like slip
stiffness and maximum shear force in composite beams subjected to hogging moment. The results show that the
shear studs located in the crack-concentration zones due to large hogging moments sustain significantly smaller
shear force and slip stiffness than the other zones. Moreover, the reduction of the slip stiffness in the shear
connection appears also to be closely related to the change in the tensile strain of rebar according to the increase
of the load. Further experimental and analytical studies shall be conducted considering variables such as the
reinforcement ratio and the arrangement of shear connectors to achieve efficient design of the shear connection
in composite beams subjected to hogging moment.
Gold prospecting using Remote Sensing ‘A case study of Sudan’IJERD Editor
Gold has been extracted from northeast Africa for more than 5000 years, and this may be the first
place where the metal was extracted. The Arabian-Nubian Shield (ANS) is an exposure of Precambrian
crystalline rocks on the flanks of the Red Sea. The crystalline rocks are mostly Neoproterozoic in age. ANS
includes the nations of Israel, Jordan. Egypt, Saudi Arabia, Sudan, Eritrea, Ethiopia, Yemen, and Somalia.
Arabian Nubian Shield Consists of juvenile continental crest that formed between 900 550 Ma, when intra
oceanic arc welded together along ophiolite decorated arc. Primary Au mineralization probably developed in
association with the growth of intra oceanic arc and evolution of back arc. Multiple episodes of deformation
have obscured the primary metallogenic setting, but at least some of the deposits preserve evidence that they
originate as sea floor massive sulphide deposits.
The Red Sea Hills Region is a vast span of rugged, harsh and inhospitable sector of the Earth with
inimical moon-like terrain, nevertheless since ancient times it is famed to be an abode of gold and was a major
source of wealth for the Pharaohs of ancient Egypt. The Pharaohs old workings have been periodically
rediscovered through time. Recent endeavours by the Geological Research Authority of Sudan led to the
discovery of a score of occurrences with gold and massive sulphide mineralizations. In the nineties of the
previous century the Geological Research Authority of Sudan (GRAS) in cooperation with BRGM utilized
satellite data of Landsat TM using spectral ratio technique to map possible mineralized zones in the Red Sea
Hills of Sudan. The outcome of the study mapped a gossan type gold mineralization. Band ratio technique was
applied to Arbaat area and a signature of alteration zone was detected. The alteration zones are commonly
associated with mineralization. The alteration zones are commonly associated with mineralization. A filed check
confirmed the existence of stock work of gold bearing quartz in the alteration zone. Another type of gold
mineralization that was discovered using remote sensing is the gold associated with metachert in the Atmur
Desert.
Reducing Corrosion Rate by Welding DesignIJERD Editor
The paper addresses the importance of welding design to prevent corrosion at steel. Welding is
used to join pipe, profiles at bridges, spindle, and a lot more part of engineering construction. The
problems happened associated with welding are common issues in these fields, especially corrosion.
Corrosion can be reduced with many methods, they are painting, controlling humidity, and also good
welding design. In the research, it can be found that reducing residual stress on the welding can be
solved in corrosion rate reduction problem.
Preheating on 500oC and 600oC give better condition to reduce corosion rate than condition after
preheating 400oC. For all welding groove type, material with 500oC and 600oC preheating after 14 days
corrosion test is 0,5%-0,69% lost. Material with 400oC preheating after 14 days corrosion test is 0,57%-0,76%
lost.
Welding groove also influence corrosion rate. X and V type welding groove give better condition to reduce
corrosion rate than use 1/2V and 1/2 X welding groove. After 14 days corrosion test, the samples with
X welding groove type is 0,5%-0,57% lost. The samples with V welding groove after 14 days corrosion test is
0,51%-0,59% lost. The samples with 1/2V and 1/2X welding groove after 14 days corrosion test is 0,58%-
0,71% lost.
Router 1X3 – RTL Design and VerificationIJERD Editor
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks (as opposed to a network switch, which connects data lines from one single network). This paper,
mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of
router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top
module.
Active Power Exchange in Distributed Power-Flow Controller (DPFC) At Third Ha...IJERD Editor
This paper presents a component within the flexible ac-transmission system (FACTS) family, called
distributed power-flow controller (DPFC). The DPFC is derived from the unified power-flow controller (UPFC)
with an eliminated common dc link. The DPFC has the same control capabilities as the UPFC, which comprise
the adjustment of the line impedance, the transmission angle, and the bus voltage. The active power exchange
between the shunt and series converters, which is through the common dc link in the UPFC, is now through the
transmission lines at the third-harmonic frequency. DPFC multiple small-size single-phase converters which
reduces the cost of equipment, no voltage isolation between phases, increases redundancy and there by
reliability increases. The principle and analysis of the DPFC are presented in this paper and the corresponding
simulation results that are carried out on a scaled prototype are also shown.
Mitigation of Voltage Sag/Swell with Fuzzy Control Reduced Rating DVRIJERD Editor
Power quality has been an issue that is becoming increasingly pivotal in industrial electricity
consumers point of view in recent times. Modern industries employ Sensitive power electronic equipments,
control devices and non-linear loads as part of automated processes to increase energy efficiency and
productivity. Voltage disturbances are the most common power quality problem due to this the use of a large
numbers of sophisticated and sensitive electronic equipment in industrial systems is increased. This paper
discusses the design and simulation of dynamic voltage restorer for improvement of power quality and
reduce the harmonics distortion of sensitive loads. Power quality problem is occurring at non-standard
voltage, current and frequency. Electronic devices are very sensitive loads. In power system voltage sag,
swell, flicker and harmonics are some of the problem to the sensitive load. The compensation capability
of a DVR depends primarily on the maximum voltage injection ability and the amount of stored
energy available within the restorer. This device is connected in series with the distribution feeder at
medium voltage. A fuzzy logic control is used to produce the gate pulses for control circuit of DVR and the
circuit is simulated by using MATLAB/SIMULINK software.
Study on the Fused Deposition Modelling In Additive ManufacturingIJERD Editor
Additive manufacturing process, also popularly known as 3-D printing, is a process where a product
is created in a succession of layers. It is based on a novel materials incremental manufacturing philosophy.
Unlike conventional manufacturing processes where material is removed from a given work price to derive the
final shape of a product, 3-D printing develops the product from scratch thus obviating the necessity to cut away
materials. This prevents wastage of raw materials. Commonly used raw materials for the process are ABS
plastic, PLA and nylon. Recently the use of gold, bronze and wood has also been implemented. The complexity
factor of this process is 0% as in any object of any shape and size can be manufactured.
Spyware triggering system by particular string valueIJERD Editor
This computer programme can be used for good and bad purpose in hacking or in any general
purpose. We can say it is next step for hacking techniques such as keylogger and spyware. Once in this system if
user or hacker store particular string as a input after that software continually compare typing activity of user
with that stored string and if it is match then launch spyware programme.
A Blind Steganalysis on JPEG Gray Level Image Based on Statistical Features a...IJERD Editor
This paper presents a blind steganalysis technique to effectively attack the JPEG steganographic
schemes i.e. Jsteg, F5, Outguess and DWT Based. The proposed method exploits the correlations between
block-DCTcoefficients from intra-block and inter-block relation and the statistical moments of characteristic
functions of the test image is selected as features. The features are extracted from the BDCT JPEG 2-array.
Support Vector Machine with cross-validation is implemented for the classification.The proposed scheme gives
improved outcome in attacking.
Secure Image Transmission for Cloud Storage System Using Hybrid SchemeIJERD Editor
- Data over the cloud is transferred or transmitted between servers and users. Privacy of that
data is very important as it belongs to personal information. If data get hacked by the hacker, can be
used to defame a person’s social data. Sometimes delay are held during data transmission. i.e. Mobile
communication, bandwidth is low. Hence compression algorithms are proposed for fast and efficient
transmission, encryption is used for security purposes and blurring is used by providing additional
layers of security. These algorithms are hybridized for having a robust and efficient security and
transmission over cloud storage system.
Application of Buckley-Leverett Equation in Modeling the Radius of Invasion i...IJERD Editor
A thorough review of existing literature indicates that the Buckley-Leverett equation only analyzes
waterflood practices directly without any adjustments on real reservoir scenarios. By doing so, quite a number
of errors are introduced into these analyses. Also, for most waterflood scenarios, a radial investigation is more
appropriate than a simplified linear system. This study investigates the adoption of the Buckley-Leverett
equation to estimate the radius invasion of the displacing fluid during waterflooding. The model is also adopted
for a Microbial flood and a comparative analysis is conducted for both waterflooding and microbial flooding.
Results shown from the analysis doesn’t only records a success in determining the radial distance of the leading
edge of water during the flooding process, but also gives a clearer understanding of the applicability of
microbes to enhance oil production through in-situ production of bio-products like bio surfactans, biogenic
gases, bio acids etc.
Gesture Gaming on the World Wide Web Using an Ordinary Web CameraIJERD Editor
- Gesture gaming is a method by which users having a laptop/pc/x-box play games using natural or
bodily gestures. This paper presents a way of playing free flash games on the internet using an ordinary webcam
with the help of open source technologies. Emphasis in human activity recognition is given on the pose
estimation and the consistency in the pose of the player. These are estimated with the help of an ordinary web
camera having different resolutions from VGA to 20mps. Our work involved giving a 10 second documentary to
the user on how to play a particular game using gestures and what are the various kinds of gestures that can be
performed in front of the system. The initial inputs of the RGB values for the gesture component is obtained by
instructing the user to place his component in a red box in about 10 seconds after the short documentary before
the game is finished. Later the system opens the concerned game on the internet on popular flash game sites like
miniclip, games arcade, GameStop etc and loads the game clicking at various places and brings the state to a
place where the user is to perform only gestures to start playing the game. At any point of time the user can call
off the game by hitting the esc key and the program will release all of the controls and return to the desktop. It
was noted that the results obtained using an ordinary webcam matched that of the Kinect and the users could
relive the gaming experience of the free flash games on the net. Therefore effective in game advertising could
also be achieved thus resulting in a disruptive growth to the advertising firms.
Hardware Analysis of Resonant Frequency Converter Using Isolated Circuits And...IJERD Editor
-LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region[5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
Amateurs Radio operator, also known as HAM communicates with other HAMs through Radio
waves. Wireless communication in which Moon is used as natural satellite is called Moon-bounce or EME
(Earth -Moon-Earth) technique. Long distance communication (DXing) using Very High Frequency (VHF)
operated amateur HAM radio was difficult. Even with the modest setup having good transceiver, power
amplifier and high gain antenna with high directivity, VHF DXing is possible. Generally 2X11 YAGI antenna
along with rotor to set horizontal and vertical angle is used. Moon tracking software gives exact location,
visibility of Moon at both the stations and other vital data to acquire real time position of moon.
“MS-Extractor: An Innovative Approach to Extract Microsatellites on „Y‟ Chrom...IJERD Editor
Simple Sequence Repeats (SSR), also known as Microsatellites, have been extensively used as
molecular markers due to their abundance and high degree of polymorphism. The nucleotide sequences of
polymorphic forms of the same gene should be 99.9% identical. So, Microsatellites extraction from the Gene is
crucial. However, Microsatellites repeat count is compared, if they differ largely, he has some disorder. The Y
chromosome likely contains 50 to 60 genes that provide instructions for making proteins. Because only males
have the Y chromosome, the genes on this chromosome tend to be involved in male sex determination and
development. Several Microsatellite Extractors exist and they fail to extract microsatellites on large data sets of
giga bytes and tera bytes in size. The proposed tool “MS-Extractor: An Innovative Approach to extract
Microsatellites on „Y‟ Chromosome” can extract both Perfect as well as Imperfect Microsatellites from large
data sets of human genome „Y‟. The proposed system uses string matching with sliding window approach to
locate Microsatellites and extracts them.
Importance of Measurements in Smart GridIJERD Editor
- The need to get reliable supply, independence from fossil fuels, and capability to provide clean
energy at a fixed and lower cost, the existing power grid structure is transforming into Smart Grid. The
development of a smart energy distribution grid is a current goal of many nations. A Smart Grid should have
new capabilities such as self-healing, high reliability, energy management, and real-time pricing. This new era
of smart future grid will lead to major changes in existing technologies at generation, transmission and
distribution levels. The incorporation of renewable energy resources and distribution generators in the existing
grid will increase the complexity, optimization problems and instability of the system. This will lead to a
paradigm shift in the instrumentation and control requirements for Smart Grids for high quality, stable and
reliable electricity supply of power. The monitoring of the grid system state and stability relies on the
availability of reliable measurement of data. In this paper the measurement areas that highlight new
measurement challenges, development of the Smart Meters and the critical parameters of electric energy to be
monitored for improving the reliability of power systems has been discussed.
Study of Macro level Properties of SCC using GGBS and Lime stone powderIJERD Editor
One of the major environmental concerns is the disposal of the waste materials and utilization of
industrial by products. Lime stone quarries will produce millions of tons waste dust powder every year. Having
considerable high degree of fineness in comparision to cement this material may be utilized as a partial
replacement to cement. For this purpose an experiment is conducted to investigate the possibility of using lime
stone powder in the production of SCC with combined use GGBS and how it affects the fresh and mechanical
properties of SCC. First SCC is made by replacing cement with GGBS in percentages like 10, 20, 30, 40, 50 and
by taking the optimum mix with GGBS lime stone powder is blended to mix in percentages like 5, 10, 15, 20 as
a partial replacement to cement. Test results shows that the SCC mix with combination of 30% GGBS and 15%
limestone powder gives maximum compressive strength and fresh properties are also in the limits prescribed by
the EFNARC.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Leading Change strategies and insights for effective change management pdf 1.pdf
www.ijerd.com
1. International Journal of Engineering Research and Development
ISSN: 2278-067X, Volume 1, Issue 2 (May 2012), PP.29-33
www.ijerd.com
Novel Low Power Hybrid Adders Using 90nm Technology for
DSP Applications
B. Sathiyabama1, Dr. S. Malarkkan2
1
Research Scholar, Sathyabama University, Chennai, India,
2
Principal,Manakula Vinayagar Institute of Technology, Puducherry, India.
Abstract––In this paper, two novel Hybrid Adders are proposed for Multiplier Accumulator Unit (MAC) of low power
DSP application. Adders are the most important component of the MAC unit which can significantly affect the efficiency
of the whole system. Thus, power reduction in Full adder circuit is essential for low power applications. These novel full
adders are simulated in 90 nm Technology with BSIM model at 27 o temperature. The performance of power, delay,
voltage swing, power delay product and area of these Hybrid adders are studied at various low supply voltages (0.8V,
0.9V & 1.0V), and compared with the other five adders. The Hybrid- A full adder which shows better delay performance
than the other adders and Hybrid –B full adder which shows lower power consumption, operates at low voltage with
good signal integrity, thereby making them suitable for low power high performance applications.
Keywords–– Low power; MAC unit; full adder; dynamic power; Power Delay Product.
I. INTRODUCTION
Due to the rapid growth in portable electronics and communication systems like laptops, etc., the low power
microelectronic devices have become very important in today’s world [1]. In fact, Low-power VLSI chips have emerged
in high demand for designing any sub system. With the increase in complexity of VLSI systems and amount of power
available in certain systems like cell phones and digital cameras, minimizing power consumption is essential. Further,
lower power consumption in system is essential for many applications due to the dramatic increase in power-conscious
applications. These low power circuits can be realized using both hardware and software approach. In many VLSI
applications, arithmetic operations are used extensively. Mostly the digital processing requires high speed and low power
multiplier accumulator (MAC) unit. Addition and multiplication are the most important operations in this unit.
Specifically, speed and power efficient implementation of these adders is a very challenging problem. Lowering power
consumption not only increases reliability, but also saves package costs due to reduced heat dissipation. The main
contributor to overall power dissipation in CMOS VLSI circuits is dynamic power consumption which accounts for up to
80% of the total power [1-2]. The dominant source of power dissipation is the dynamic power dissipation due to the
charging and discharging of the node capacitances and is given by:
P=0.5 CVdd2 E (sw) fclk (1)
Where C is the physical capacitance of the circuit, V dd is the supply voltage, E(sw) (switching activity) is the
average number of transitions in the circuit per 1/fclk time, and fclk is the clock frequency. In order to reduce the power
consumption of the adders any one of the above factors of circuit needs to be changed. In this work different logic
structures are used for constructing adders for the low power DSP application.
This paper is organized as follows: the full adder cell for MAC unit is described in the section II, associated work
for full adders is described in the section III, proposed two new Hybrid adders are given in section IV, simulation results
and discussion is presented in the section V and finally conclusion is given in the section VI.
II. FULL ADDER CELL
Generally, a full adder is defined as a logical cell that performs an addition operation on three one-bit binary
numbers. The full adder produces a two-bit output which is Carry and Sum. Full Adder cell is implemented in low power
and high performance data path circuits of any system. The full adder consists of three input signals, i.e., A, B, and C
(carry in), and two output signals Sum and Carryout which is shown in Fig. 1.
Fig.1. Full Adder cell
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2. Novel Low Power Hybrid Adders Using 90nm Technology for DSP Applications
The basic operation of full adder is given by the standard Boolean expressions as,
C = AB + BC + CA (2)
S = ABC + A’B’C + A B’C’ + A’BC’ (3)
There are various design techniques for implementation of full adder circuits. Some of them are Multiplexing
Control Input Technique (MCIT), Gate Diffusion Input technique (GDI), Technique based on static CMOS Inverter,
Multi-threshold CMOS circuit technique (MTCMOS) [4-13]. The existing Shannon based full-adder cell has been
executed for the sum operation and the carry operation separately. This has the demerits of more number of transistors,
higher power consumption, larger area requirement, and pass transistor logic threshold voltage loss problem. In order to
overcome the drawback of existing full adder circuits, the proposed full adder circuits has been implemented with
different logic style and logic function. In the proposed full adder cell, Pass transistor logic is utilized among all the other
logic styles available as it is found to enhance the circuit performance in terms of speed, power and transistor counts. The
adder cell can be applied to implement low power and high performance data path circuits.
In this paper, different full adder circuits Modified Shannon, , Full adder using 10T, Full adder using 14T , Full
adder using 16T, Hybrid FA-I [8-9] are simulated and analyzed the performance using the software tool HSPICE with
90nm technology. Two New Novel Hybrid FAs are proposed and its performances are studied. The main attributes are
High-speed and high-resolution, ultra low power consumption, robust performance, immunity to noise & manufacturing
variations.
III. RELATED WORK
Adders are the basic building module in all multipliers, filters and MAC unit of DSP processor. So employing fast
adders plays a key role in the performance of the entire all data path circuits. In this section different adder cells are
described and analyzed. By using Shannon’s theorem the sum and the carry expressions are condensed and thereby the
transistor count has been decreased [7]. In the existing design of full adder the carry is generated using six transistors
where as the modified Shannon full Adder [10] design uses only two transistors. Thus the total chip area gets reduced.
Therefore the power has also been minimized to a considerable amount. (Fig .2.a). The advantage of the Modified
shannon is lower number of transistors, and better voltage swing. Full adder using 10T use more than one logic
structure for the implementation and is called as mixed logic design structure [11]. The numbers of transistors required
to implement this circuit is 10 and A, B and Cin are the inputs. Sum and Carry are the outputs (see Fig. 2 .b). The
demerits of this circuit are that produces high capacitance values for the inputs.
a. Modified Shannon FA [10] b. Full Adder Using 10T [11] c.Full Adder Using 14T [12]
d. Full Adder Using 16 T [13] e. Hybrid-I Full adder [14]
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3. Novel Low Power Hybrid Adders Using 90nm Technology for DSP Applications
f. Proposed Hybrid-A Full adder g. Proposed Hybrid-B Full adder
Fig. 2. Transistor Schematic for different Full Adders and proposed adders
Fig. 2.c shows the Full adder using 14T uses more than one logic style for the implementation and is called as a
mixed logic design style. The number of transistors required is 14, and circuit has 3 inputs and 2 outputs, [12] Full adder
using 14T generates A B and use it along with its complement as a select signal to generate the output of the circuit.
The advantage of 14T is small transistor count and enhances the non full swing pass transistor. The main drawback is that
produce high capacitance values for the input signals. Full adders using 16T are designed with specific kind of XOR and
XNOR implementation [13]This full adder has good driving capabilities in fan-out situation with area trade off.
Hybrid I and Hybrid II adders are designed using 14T and modified Shannon adders [14].The proposed adders are
discussed in detail in the following section.
IV. PROPOSED HYBRID FULL ADDERS
Full adder cell is the basic component of the Multiply Accumulate Unit in DSP processors. Based on the merits and
demerits of the existing adder’s features, the new Hybrid Full adders are designed. Here, five full adders are modeled
using 90nm technology with BSIM. These full adder circuits are analyzed for all the eight combinations of binary inputs
with voltage scaling technique (at various supply voltages). From the analyzed circuits, it is found that 14T and Modified
Shannon has better the functionality than the other existing circuits. Using 14T and Shannon Modified adders, hybrid
adders are designed. The combination of 14T’s Sum and Modified Shannon’s carry is implemented, called as Hybrid-I,
which is shown in Fig. 3.e The width is optimized by transistor sizing to bring the better power consumption without
degrading the delay. In order to improve the power, delay and driving capability, Hybrid –A and Hybrid-B Full adders
are proposed. Hybrid-A Full adder is designed with 10T Sum and modified Shannon carry which consist of 12
transistors. Hybrid B Full adder is built using low power XOR and XNOR for sum implementation and carry is designed
with modified Shannon .It requires 16transistor using pass transistor logic and NMOS transistors. The optimal value of
power is obtained by changing the size of the transistor (W/L) and the operating supply voltage V dd. The width of the
PMOS and NMOS transistors are alerted from 2.0 µm to 0.1 µm for optimizing Power Delay Product (PDP). These
circuits provide good driving capability and better power delay performance.
V. RESULTS AND DISCUSSION
All adder circuits are implemented and simulated using HSPICE with BSIM model at 90nm technology for which
parasitic capacitance are considered in the result. A proper simulation test bench is used to simulate a real environment
and minimum output load is used for power and delay measurements. Five existing adders and the two new Hybrid
adders are simulated and their layouts are developed. The circuit performances are studied using voltage scaling
technique (1V, 0.9V & 0.8V). All full adder circuits are analyzed for all the eight combinations of binary input and also
for various supply voltages. Hybrid A and Hybrid B Full adder circuits are developed using a combination of 10T, 16
T low power adder and modified Shannon full adder.
Table.1 shows the sum and carry voltage level for all the full adder circuits at Vdd =1V, 0.9V, and 0.8V. The area
occupied by the adders and number of transistors required to implement the circuit is given in the Table 1.All the full
adder circuits are compared at different voltages. The Full adder using Modified Shannon has the lowest number of
transistors with the count of 8. It is observed that the voltage loss is high in modified Shannon Full Adder. Hybrid B full
adder shows excellent voltage swing at sum and moderate voltage swing at carry outputs. In Table.2 the power and delay
for all the full adder circuits at Vdd=1V, 0.9V and 0,8V is given. Comparing the performances of the full adder circuits it
is observed that the voltage loss is less for Hybrid-B Sum, Hybrid-A has the lowest Delay and Hybrid B has the lowest
power consumption for the new design. Comparison of the power and delay of HYBRID A and HYBRID B Full adders
with other five adders are shown in Fig .5. All circuit simulations are carried out in 90nm with BSIM model using
HSPICE. The power delay product at various Vdd of Hybrid adders are shown in Table.3.HYBRID -A adder has very less
PDP, which is shown in Fig.6.
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4. Novel Low Power Hybrid Adders Using 90nm Technology for DSP Applications
Table 1. Sum and Carry voltage level , and Area Analysis of Different Full Adders at Vdd = 1V, at 90 nm Technology
S.no Adder No of Transistor Sum (V) Carry(V) Area( µm2)
1. Modified Shannon FA 8 0.6 0.6 88.1
2. FA Using 10T 10 0.8 0.8 124.7
3. FA Using 14T 14 1.0 1.0 227.7
4. FA using 16T 16 0.98 0.98 196.0
5. HYBRID-I FA 14 1.0 0.87 145.9
6. HYBRID –A FA 12 0.85 0.85 163.1
7. HYBRID –B FA 16 1.0 0.85 169.6
Table 2. Power and Delay Analysis of Different Full Adders at different voltage at 90nm technology
S.no Adder VDD =1V VDD =0.9V VDD =0.8V
Power delay Power delay Power Delay
(µw) (ps) (µ w) (ps) (µw) (ps)
1. Modified Shannon FA[10] 22.03 0.78 18.83 0.97 9.98 1.78
2. FA Using 10T [11] 1.06 41 0.96 52 0.86 94
3. FA Using 14T [12] 0.8 10 0.88 11 0.78 13
4. FA using 16T [13] 0.65 8 0.59 10 0.52 12
5. HYBRID-I FA [14] 0.61 8 0.55 10 0.48 12
6. HYBRID –A FA 1.61 0.37 1.45 0.72 1.20 0.95
7 HYBRID –B FA 0.67 6 0.61 7 0.53 9
Table 3. Power Delay Product Analysis of Different 1 Bit Full Adder At Vdd =1V, 0.9V and 0.8V
Sno Adder Power delay product
VDD 1 V (e-18) VDD 0.9 V (e-18) VDD 0.8 V (e-18)
1. Modified Shannon FA 17.18 17.46 17.76
2. FA Using 10T 43.46 49.92 88.84
3. FA Using 14T 8.0 9.68 10.14
4. FA using 16T 5.2 5.9 6.24
5. HYBRID-I FA 4.88 5.5 5.76
6. HYBRID –A FA 0.59 1.04 1.14
7. HYBRID –B FA 4.02 4.27 4.77
Fig. 5.a. Power and Delay performance of various Full Adders
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5. Novel Low Power Hybrid Adders Using 90nm Technology for DSP Applications
Fig. 5.b. Power Delay Product performance of various Full Adders
VI. CONCLUSION
In this paper, HYBRID- A and HYBRID -B full adders are proposed for data path circuit (MAC unit) for low power
DSP application. The proposed circuit uses full adder using 10T, 16 T and Modified Shannon circuits. The existing five
adders and two proposed full adder circuits are implemented and simulated in HSPICE using BSIM model at 90nm
Technology .The power, voltage level, delay and PDP values of all the full adder circuits are analyzed. The optimal value
of power and PDP is obtained by transistor sizing and voltage scaling. The performance analysis of various full adders at
Vdd=1V, 0.9V, 0.8V using 90nm technology are carried out. It is observed from the simulated results that the proposed
circuit has the lowest Delay, Voltage Loss and Power Consumption with reduction in area occupied. The functionality
test of different full adders at Vdd=1V, 0.9V, 0.8V using 90nm technology are also verified. All 8 combinations of
Binary input are tested for each circuit. It is found that HYBRID- B has the better power consumption compared with
Hybrid -A Full Adder and delay performance is good in the Hybrid -A circuits. At low voltage level (Vdd =1), HYBRID-
A adder has very less power delay product (nearly 4-95% of improvement) compared with other adders with better area
occupation. Here, all the circuits are simulated using the BSIM model at 90nm technology. This can also be tried for
other models of submicron technology less than 65nm.Therefore these Hybrid adders can be utilized for low power high
performance applications.
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