This document presents a design for a high-speed low-power Viterbi decoder for trellis coded modulation decoders. It proposes a precomputation architecture incorporated with the T-algorithm to reduce power consumption without significantly degrading decoding speed. The architecture calculates branch metric minimum values in advance and compares them to path metrics to eliminate unlikely paths early. Implementation in Verilog and synthesis results show the proposed architecture operates at a lower supply voltage for moderate throughput applications, achieving quadratic power reduction over conventional decoders.