This document summarizes the key differences between the Von Neumann and Harvard memory architectures. The Von Neumann architecture stores program instructions and data in the same memory, while the Harvard architecture keeps them separate. The Harvard architecture allows code to be executed in parallel through separate instruction and data buses, enabling typically one memory access per cycle compared to 2-4 for Von Neumann. Examples of processors that use the Harvard architecture include the Texas Instruments TMS320 C55x, AVR by Atmel, and PIC by Microchip Technology.

1. PRESENTED BY:
A.PRIYANKA
CENTURION UNIVERSITY OF TECHNOLOGYAND MANAGEMENT
Topic: DSP Memory Architecture
Digital Signal & Processing

2. Contents
• Von Neumann Model
• Harvard Memory Architecture

3. DSP Memory

4. Harvard Memory Architecture

5. Examples
• Texas Instruments TMS320 C55x processors, as one example, have
multiple parallel data buses (two write, three read) and one instruction
bus.
• Examples include, the AVR by Atmel Corp, the PIC by Microchip
Technology, Inc. and the ARM Cortex-M3 processor (not all ARM chips
have Harvard architecture).
PIC

7. Von Neumann Model
• The basic concept behind the von Neumann architecture is the ability to
store program instructions in memory along with the data on which those
instructions operate.
• It is composed of three distinct components (or sub-systems): a central
processing unit (CPU), memory, and input/output (I/O) interfaces

8. Von Neumann Model

10. Von Neumann Vs. Harvard
Von Neumann Harvard
The data and program are stored in the
same memory.
The data and program memories are
separate.
The code is executed serially and takes
more clock cycles
The code is executed in parallel
A single set of address/data buses
between CPU and memory
Two sets of address/data buses between
CPU and memory
2-4 memory accesses/cycle Typically 1 access/cycle
No caches-on-chip SRAM Use caches

11. Thank You..