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Program Sequencer
Speed issues
• Hardware architecture
• Parallelism
Pipelining
Features of external Interfacing
• Should be able to communicate with outside world.
• Most of the peripherals used in microprocessors are used in DSP.
• Interfaces for interrupts.
• Direct memory access(DMA).
• Serial I/O and Parallel I/O.
• A/D and D/A converters.
• To do all these proper address data and control data should be
available.
PROGRAMMABLE DIGITAL SIGNAL PROCESSOR (TMS320C54XX)
• The architectural features and the processing power of these devices have been constantly upgraded based, on
the advances in technology and the application needs.
• Of the various families of programmable DSP devices that are commercially available, the three most popular
1.Texas Instruments
2.Motorola,
3.Analog Devices.
• Texas Instruments was one of the first to come out with a commercial programmable DSP with the
introduction of its TMS32010 in 1982.
1. They have one program and three
data memory spaces with separate
buses
2. The central processing unit (CPU) of
TMS320C54xx processors consists
of a 40-bit arithmetic logic unit
(ALU
3. Two 40 bit accumulators, a barrel
shifter, a 17 x 17 multiplier; a 40-bit
adder, data address generation logic
(DAGEN) with its own arithmetic
unit, and a program address
generation logic (PAGEN).
4. A powerful instruction set with a
hardware-supported.
5. single-instruction repeat and block
repeat operations.
6. Block memory move instructions.
instructions that pack two or three
simultaneous reads, and arithmetic
instructions with parallel store and
load make these devices very
efficient for running highspeed DSP
algorithms.
Bus structure
1. 4 pairs of 16-bit buses.
2. Each pair having address bus and
data bus.
3. Program bus pair PAB,PB. which
carries instruction code from
program memory.
4. CAB,CB , DAB,DB and EAB,EB are
data bus pairs.
5. CAB,CB and DAB,DB are used for
the data read from memory.
6. EAB,EB are used for data write to
the memory.
CPU
1. 54xx has common CPU architecture for all
54xx devices.
2. Has 40 bit ALU.
3. 40 bit accumulator A and B.
4. A barrel shifter a 17 X 17 multiplier.
5. A 40 bit adder.
6. A compare select and store unit(CSSU).
7.An exponent encoder(EXP).
8. DAGEN(data address generation unit.
9. PAGEN(Program address generation unit).
10. ALU: Performs 2’s complement arithmetic
operation on 16, 32 and 40 bit data. also
function as to 16 bit ALUs.
Internal Memory and Memory-Mapped Registers
• The amount and the types of memory of a processor have direct relevance to the efficiency and the
performance .
• The '54xx memory is organized into three individually selectable spaces:
1. Program.
2. Data.
3. I/O spaces.
• All '54xx devices contain both RAM and ROM. RAM can be either dual-access type (DARAM) or single-
access type (SARAM).
• The '54xx processors have several CPU registers to support operand addressing and computations. Some of
the registers are listed below.
TMS320C54XX DSP Processor Features and Architecture
TMS320C54XX DSP Processor Features and Architecture

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TMS320C54XX DSP Processor Features and Architecture

  • 2. Speed issues • Hardware architecture • Parallelism
  • 4. Features of external Interfacing • Should be able to communicate with outside world. • Most of the peripherals used in microprocessors are used in DSP. • Interfaces for interrupts. • Direct memory access(DMA). • Serial I/O and Parallel I/O. • A/D and D/A converters. • To do all these proper address data and control data should be available.
  • 5. PROGRAMMABLE DIGITAL SIGNAL PROCESSOR (TMS320C54XX) • The architectural features and the processing power of these devices have been constantly upgraded based, on the advances in technology and the application needs. • Of the various families of programmable DSP devices that are commercially available, the three most popular 1.Texas Instruments 2.Motorola, 3.Analog Devices. • Texas Instruments was one of the first to come out with a commercial programmable DSP with the introduction of its TMS32010 in 1982.
  • 6. 1. They have one program and three data memory spaces with separate buses 2. The central processing unit (CPU) of TMS320C54xx processors consists of a 40-bit arithmetic logic unit (ALU 3. Two 40 bit accumulators, a barrel shifter, a 17 x 17 multiplier; a 40-bit adder, data address generation logic (DAGEN) with its own arithmetic unit, and a program address generation logic (PAGEN). 4. A powerful instruction set with a hardware-supported. 5. single-instruction repeat and block repeat operations. 6. Block memory move instructions. instructions that pack two or three simultaneous reads, and arithmetic instructions with parallel store and load make these devices very efficient for running highspeed DSP algorithms.
  • 7.
  • 8.
  • 9.
  • 10. Bus structure 1. 4 pairs of 16-bit buses. 2. Each pair having address bus and data bus. 3. Program bus pair PAB,PB. which carries instruction code from program memory. 4. CAB,CB , DAB,DB and EAB,EB are data bus pairs. 5. CAB,CB and DAB,DB are used for the data read from memory. 6. EAB,EB are used for data write to the memory.
  • 11. CPU 1. 54xx has common CPU architecture for all 54xx devices. 2. Has 40 bit ALU. 3. 40 bit accumulator A and B. 4. A barrel shifter a 17 X 17 multiplier. 5. A 40 bit adder. 6. A compare select and store unit(CSSU). 7.An exponent encoder(EXP). 8. DAGEN(data address generation unit. 9. PAGEN(Program address generation unit). 10. ALU: Performs 2’s complement arithmetic operation on 16, 32 and 40 bit data. also function as to 16 bit ALUs.
  • 12. Internal Memory and Memory-Mapped Registers • The amount and the types of memory of a processor have direct relevance to the efficiency and the performance . • The '54xx memory is organized into three individually selectable spaces: 1. Program. 2. Data. 3. I/O spaces. • All '54xx devices contain both RAM and ROM. RAM can be either dual-access type (DARAM) or single- access type (SARAM). • The '54xx processors have several CPU registers to support operand addressing and computations. Some of the registers are listed below.