The document contains VHDL code for several basic digital logic components including a parallel-in parallel-out shift register, serial-in parallel-out shift register, 4-bit binary counter, 4-bit ring counter, RS latch, D latch, SR flip-flop, and D flip-flop. The code uses processes, signals, ports, and architectures to model the behavior and dataflow of each component.

1. Behavioural modelling
VHDL code for Parallel In Parallel Out Shift Register
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(
clk : in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end pipo;
architecture arch of pipo is
begin
process (clk)
begin
if (CLK'event and CLK='1') then
Q <= D;
end if;
end process;
end arch;
Serial in parallel out shift register
library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(
clk, clear : in std_logic;
Input_Data: in std_logic;
Q: out std_logic_vector(3 downto 0) );
end sipo;
architecture arch of sipo is
begin
process (clk)
begin
if clear = '1' then
Q <= "0000";

2. elsif (CLK'event and CLK='1') then
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= Input_Data;
end if;
end process;
end arch;
VHDL Code for 4-bit binary counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_binary_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end vhdl_binary_counter;
architecture bhv of vhdl_binary_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1′) then
tmp <= "0000";
elsif (C’event and C=’1′) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;

3. end bhv;
4 bit ring counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;
architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector(3 downto 0):= "0000";
begin
process(CLOCK,RESET)
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;

4. end Behavioral;

5. DATAFLOW MODELLING
RS latch
entity RS_LATCH is
port ( R,S :in BIT :=‘1’;
Q:buffer BIT := '1'
QBAR: buffer BIT := '0');
end RS_LATCH;
architecture DELTA of RS_LATCH is
begin
QBAR <= R nand Q;
Q <= S nand QBAR;
end DELTA;
VHDL Code for a D Latch
library ieee;
use ieee.std_logic_1164.all;
entity Dl is
port(d:in bit; q,qbar:buffer bit);
end Dl;
architecture virat of Dl is
signal s1,r1:bit;
begin

6. q<= d nand qbar;
qbar<= d nand q;
end virat;
VHDL Code for an SR Flip Flop
library ieee;
use ieee.std_logic_1164.all;
entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;
architecture virat of srflip is
signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;
VHDL Code for a D Flip Flop
Library ieee;
use ieee.std_logic_1164.all;
entity dflip is
port(d,clk:in bit; q,qbar:buffer bit);
end dflip;
architecture virat of dflip is
signal d1,d2:bit;
begin
d1<=d nand clk;
d2<=(not d) nand clk;
q<= d1 nand qbar;
qbar<= d2 nand q;
end virat;