This document describes a group project to recreate two digital logic experiments in VHDL. It includes VHDL code and explanations for: 1) A 4-bit binary to gray code converter using basic gates and NAND gates. 2) An 8-input 1-bit multiplexer using switch case statements and if/elsif/else ladder statements. The group members are listed and the problem statement is to recreate experiments 3 and 2 from a previous lab assignment in VHDL. Truth tables are provided for each circuit.

1. Practical 7 DCC Lab
Submitted by:
Group: DCCL05
Members:
1. Aadit Fadia
2. Ishan Moondra
3. Ojasee Duble
4. Parth Gavade
5. Pranav Deshpande
Problem Statement:
To recreate 2 previously done experiments in VHDL(Experiments 3 & 2 as in order) .
(Experiment 3): Part A:
4 Bit Binary to Gray Code Converter using Basic Gates:
VHDL Code:
library IEEE;
use IEEE.std_logic_1164,all;
entity btg4 is
port(
I_Vec : in std_logic_vector(3 downto 0);
O_Vec : out std_logic_vector(3 downto 0));
end entity btg4;
architecture RTL of btg4 is
begin
O_Vec(3) <= I_Vec(3);
O_Vec(1) <= I_Vec(0) xor I_Vec(1);
O_Vec(2) <= I_Vec(1) xor I_Vec(2);
O_Vec(3) <= I_Vec(2) xor I_Vec(3);
end architecture RTL;
Explanation:
We know in a 4 bit binary to gray code converter, the MSB bit of the input becomes MSB of the
Gray Code. Similarly, the XORing Input Bits I0 & I1 gives us Gray Code Bit G0. Thus, G1 is
defined as the output gained from XORing I1 & I2. Thus, G2 is defined as the output gained from
XORing I2 & I3.
In our code, we first define a standard logic vector I_Vec with 4 elements, as the 4 Input Bits.
We then define another standard logic vector O_Vec with 4 elements, as the output 4 Gray Code
Bits. This ends our entity section. Now in the architecture section, we simply assign output Gray

2. Code bits as the Input Bit (n) XOR Input Bit (n-1). Finally, for Gray code bit G3, we simply
assign it as Input Bit 3. Thus, we end the architecture section of our code.
Truth Table:
Sr I3 I2 I1 I0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
8 1 0 0 0 1 0 0 0
(Experiment 3) Part B:
4 Bit Binary to Gray Code Converter using NAND Gates:
VHDL Code:
library IEEE;
use IEEE.std_logic_1164,all;
entity 4bbtgc is
port(
I_Vec : in std_logic_vector(3 downto 0);
O_Vec : out std_logic_vector(3 downto 0));
end entity 4bbtgc;
architecture RTL of 4bbtgc is
begin
variable v : std_logic_vector(2 downto 0);
variable u : std_logic_vector(5 downto 0);
v(0) <= I_Vec(0) nand I_Vec(1);
u(0) <= I_Vec(0) nand v(0);
u(1) <= I_Vec(1) nand v(0);
O_Vec(0) <= u(1) nand u(0);
v(1) <= I_Vec(1) nand I_Vec(2);
u(2) <= I_Vec(1) nand v(1);
u(3) <= I_Vec(2) nand v(1);
O_Vec(1) <= u(2) nand u(3);
v(2) <= I_Vec(2) nand I_Vec(3);
u(4) <= I_Vec(2) nand v(2);
u(5) <= I_Vec(3) nand v(2);
O_Vec(2) <= u(4) nand u(5);
O_Vec(3) <= I_Vec(3);
end architecture RTL;

3. Explanation:
We know that it is faster and cheaper to use universal inverting logic families such as NAND or
NOR gates as they can create all of our circuits with only one type of gate.
Expectedly, recreating most of the real life circuits using NAND gates is more complex, as we
get inverted outputs at the end of each gate.
To convert our 4 bit binary to gray code converter from basic gates to NAND only gates, we will
simply substitute each XOR gate with it’s set of NAND gates equivalent.
The following image shows how we specifically use NAND gates to create a 4 Bit Binary to
Gray Code Converter.
Here, we will use 2 variable std_logic_vectors, as it is more convenient to use a variable than
nest operations using parentheses. So we define 2 variables, both are std_logic_vectors, one
which is labelled u and has 6 elements, (5 downto 0) and one is labelled v, having 3 elements (2
downto 0). We also keep the I/O part of the code untouched from the previous case, since using a
different setup of gates will not affect either the inputs nor the outputs. We recreate an XOR gate
using NAND gates, by:
Assigning v(i) <= I_Vec(i) NAND I_Vec(i+1) [For ‘i’ in range 0 to 2].
Assigning u(i) <= I_Vec(i) NAND v(i)
Assigning u(i+1) <= I_Vec(i+1) NAND v(i). [‘i’ will here run from 0 to 5].
Finally, O_Vec(i) <= u(i) NAND u(i+1).
The above operations create an NAND equivalent of an XOR gate.
As seen previously, O_Vec(3) <= I_Vec(3).
Truth Table:
Sr I3 I2 I1 I0 G3 G2 G1 G0

4. 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
4 0 1 0 0 0 1 1 0
8 1 0 0 0 1 0 0 0
(Experiment 2) Part C:
8 Input 1 Bit Multiplexer using Switch Case Statements:
VHDL Code:
library IEEE;
use IEEE.std_logic_1164,all;
entity 8IMuxSwitch is
port(
I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
O : out std_logic);
end entity 8IMuxSwitch;
architecture RTL of 8IMuxSwitch is
begin
case S is
when "000" => O <= I(0);
when "001" => O <= I(1);
when "010" => O <= I(2);
when "011" => O <= I(3);
when "100" => O <= I(4);
when "101" => O <= I(5);
when "110" => O <= I(6);
when others => O <= I(7);
end case;
end architecture RTL;
Explanation:
We know a multiplexer selects a particular input to be the output based on its select lines.Thus,
in our entity section of the code, we have 2 input std_logic_vectors, I, with 8 elements (7 downto
0) & S, with 3 elements (2 downto 0), along with a single simple output of std_logic type, O.
Now, seeing how a multiplexer works, it is easy to visualize how a switch case statement would
correspond to the multiplexer in real life. Comparing the select line vector S exhaustively with
each and every possible value of S and correspondingly assigning the Output O <= I(i),
completes the architecture of the multiplexer. For example, when S = “001”, O <= I(1).
Thus, our design code for the 8 Input 1 Bit Multiplexer is complete.

5. Truth Table:
Sr S2 S1 S0 O
0 0 0 0 I0
2 0 1 0 I2
3 0 1 0 I3
7 1 1 1 I7
(Experiment 2) Part D:
8 Input 1 Bit Multiplexer using If Elsif Else Ladder:
VHDL Code:
library IEEE;
use IEEE.std_logic_1164,all;
entity 8IMux is
port(
I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
O : out std_logic);
end entity 8IMux;
architecture RTL of 8IMux is
begin
if( S = "000" ) then O <= I(0);
elsif ( S = "001" ) then O <= I(1);
elsif ( S = "010" ) then O <= I(2);
elsif ( S = "011" ) then O <= I(3);
elsif ( S = "100" ) then O <= I(4);
elsif ( S = "101" ) then O <= I(5);
elsif ( S = "110" ) then O <= I(6);
else O <= I(7);
end if;
end architecture RTL;
Explanation:
We know a multiplexer selects a particular input to be the output based on its select lines.Thus,
in our entity section of the code, we have 2 input std_logic_vectors, I, with 8 elements (7 downto
0) & S, with 3 elements (2 downto 0), along with a single simple output of std_logic type, O.
Now, seeing how a multiplexer works, it is easy to visualize how an If Elsif Else Ladder
statement would correspond to the multiplexer in real life. Comparing the select line vector S
exhaustively with each and every possible value of S, nesting each level beneath the other, and
correspondingly assigning the Output O <= I(i), completes the architecture of the multiplexer,

6. using the If Elsif Else ladder statements. . For example, when S = “001”, O <= I(1). Here, as we
are required to include at least one Else condition in the ladder, we exhaust all but one value of
select line vector S, that is, when S = “111”, which would not satisfy any of the other if & elsif
conditions, and thus output would be assigned as O <= I(7). Thus, the architecture section of our
code is complete.
Thus, our design code for the 8 Input 1 Bit Multiplexer using If Elsif Else ladder statements is
complete.
Truth Table:
Sr S2 S1 S0 O
0 0 0 0 I0
1 0 0 1 I1
5 1 0 1 I5
7 1 1 1 I7
Conclusion:
Thus, we have recreated 2 previously done experiments in VHDL (Experiments 3 & 2 as
in order.)