In digital logic and computing, a counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation .Finally we proposed counter using SRAM model, provides the best resolution, high output current and good output-input current linearity.
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION...VLSICS Design
Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
A microprocessor-compatible quadrature decoder/counter is used to interface an optical shaft encoder (OSE) to a microprocessor's system bus. Quadrature decoder/counter find application in digital data input subsystems and digital closed loop motion control systems.
Counters:
Introduction, Asynchronous counter, Terms related to counters, IC-7493 (4-bit binary counter), Synchronous counter, Bushing, Type T-Design, Type JK Design, Presettable counter, IC-7490, IC 7492, Synchronous counter ICs, Analysis of counter circuits
Describes principles of asynchronous serial communication. Explains and compares the principles and features of RS-232, RS-422 and RS-485 standards. Also outlines various registers and programming of PC16550 Universal Asynchronous Receiver/Transmitter provided by many microcontrollers,
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION...VLSICS Design
Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
A microprocessor-compatible quadrature decoder/counter is used to interface an optical shaft encoder (OSE) to a microprocessor's system bus. Quadrature decoder/counter find application in digital data input subsystems and digital closed loop motion control systems.
Counters:
Introduction, Asynchronous counter, Terms related to counters, IC-7493 (4-bit binary counter), Synchronous counter, Bushing, Type T-Design, Type JK Design, Presettable counter, IC-7490, IC 7492, Synchronous counter ICs, Analysis of counter circuits
Describes principles of asynchronous serial communication. Explains and compares the principles and features of RS-232, RS-422 and RS-485 standards. Also outlines various registers and programming of PC16550 Universal Asynchronous Receiver/Transmitter provided by many microcontrollers,
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
Analog to Digitalconvertor for Blood-Glucose Monitoringcsijjournal
ABSTRACT
This paper presents the design of a low-power CMOS current-frequency (I–F) Analog–Digital Converter. The ADC is designed for implantable blood-glucose monitoring. This current frequency ADC uses nArange of input currents to set and compare voltage oscillations against a self-produced reference to resolve 0–32nA with an accuracy of 5-bits at a 225MHz sampling rate. The comparator used is a dynamic latch comparator and the output is fetched from a 5-bit counter. This is designed in 180nm CMOS technology with a supply of 1.8V, it operating voltage taken here is 0.0- 1.8V with power consumption of 12.3nW using Cadence tools.
ANALOG TO DIGITALCONVERTOR FOR BLOOD-GLUCOSE MONITORING csijjournal
This paper presents the design of a low-power CMOS current-frequency (I–F) Analog–Digital Converter. The ADC is designed for implantable blood-glucose monitoring. This current frequency ADC uses nArange of input currents to set and compare voltage oscillations against a self-produced reference to resolve 0–32nA with an accuracy of 5-bits at a 225MHz sampling rate. The comparator used is a dynamic latch comparator and the output is fetched from a 5-bit counter. This is designed in 180nm CMOS technology with a supply of 1.8V, it operating voltage taken here is 0.0- 1.8V with power consumption of 12.3nW using Cadence tools.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADCAman JanGra
The analog-to-digital converter (ADC) is an essential part of systemon-
chip (SoC) products because it bridges the gap between the analog physical
world and the digital logical world. In the digital domain, low power and low
voltage requirements are becoming more important issues as the channel length
of MOSFET shrinks below 0.25 sub-micron values. SoC trends force ADCs to
be integrated on the chip with other digital circuits. These trends present new
challenges in ADC circuit design. This paper investigates high speed, low
power, and low voltage CMOS flash ADCs for SoC applications.
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCOVLSICS Design
In order to keep electronic world properly PLL plays a very important role. Designing of low
phase noise and less jittery PLL in generation of clock signals is an important task. Clock signals
are required for providing reference timing to electrical system and also to ICs. So in this paper
PLL is designed with improved Phase noise and also jitter. Where such types of design is
important when sophisticated timing requirements are needed to provide synchronization and
distribution of clocks like in ADC, DAC, high speed networking, medical imaging systems. The
clock signal’s quality depends upon jitter and phase noise. An ideal clock source has zero phase
noise and jitter but in reality it has some modulated phase noise. This modulated phase noise
spreads the power to the adjacent frequencies, hence produces noise sidebands. The phase noise
is typically frequency domain analysis which is expressed in terms of dBc/Hz measured at offset
frequency with respect to ideal clock frequency. The low phase noise is important factor mainly
in RF and ADC applications. In RF wireless high speed applications, increased PN will leads to
channel to channel interference, attenuates quality of signal. In ADC, increased PN limits the
SNR and data converter’s equivalent no. of bits (ENOB). Jitter is time domain meas
Design and Implementation of Schmitt Trigger using Operational AmplifierIJERA Editor
A Schmitt trigger is an electronic circuit, a Comparator that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as signal conditioning device. When an input waveform in the form of sinusoidal waveform, triangular waveform, or any other periodic waveform is given, the Schmitt trigger will produce a Rectangular or square output waveform that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. The state of the art presented in the paper is the design and implementation of Schmitt trigger using operational amplifier µA-741, generating a Rectangular waveform. Furthermore, the Schmitt trigger exhibiting hysteresis is also presented in the paper. Due to the phenomenon of hysteresis, the output transition from HIGH to LOW and LOW to HIGH will take place at various thresholds.
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Comparator holds a dominant place in fast ADC circuit for the conversion of analog to digital signal. In this modernized digital world every utilization circuits requires an ADC’s with low power to consumption. This in turn reflects in the design of comparators during the design process of the fast ADC circuits, scope is due to the higher number of comparator usage. As the technologies are scaling down, the number of transistor per unit area increases, so that the sub threshold leakage current increases which leads to power consumption in any circuit. This sources the project idea to design a comparator. It is presumed during the design that, it consumes low power in its double tail configuration which when replaces an inverter circuit in latch stage of the double tail comparator by a sleepy inverter. This presumption is validated through the analysis of the simulation results. The power consumption of the designed proposed double tail comparator is 30μw when compared to 35 μw in the conventional type. 2-bit flash ADC circuit is designed and analyzed under two different configurations of the double tail comparator. From the results, it is clear that the power consumption of the ADC circuit designed with proposed sleepy inverter based double tail comparator is observed to be 45mw.
Comparative Simulation Study Of LEACH-Like And HEED-Like Protocols Deployed I...IOSRJECE
WSNs represents one of the most interesting research areas with deep impact on technological development because of their potential usage in a wide variety of applications such as fire monitoring, border surveillance medical care, and highway traffic coordination. Therefore, WSNs researchers have defined many routing protocols for this type of network. In this paper, we have implemented and analyzed different clustering protocols, namely LEACH, LEACH-C, LEACH-1R, and HEED using MATLAB environment. These routing protocols are compared in different terms such as residual energy, data delivery to the base station, number of rounds and live nodes
Multi Slot Uwb Antennas to Minimize the Interferences from Wlan & X-Band Appl...IOSRJECE
In this paper designs of different UWB patch antennas with two rejected bands are given. The reference antenna consists of a rectangular patch etched on FR4- epoxy substrate with 50 Ω feed line and relative permittivity 4.4.. The simulated bandwidth with return loss (RL) ≥10 dB is 3.42–11.7 GHz. The rejected bands here are the WLAN and X-bands, achieved by inserting slots in the patch and the feed. The simulation results of the antennas indicate higher gain at the pass bands while a sharp drop at the rejected bands is seen. The second (reference) antenna consists of a hexagonal patch etched on FR4- epoxy substrate with 50 Ω feed line and relative permittivity 4.4,shows better return loss and rejection of the bands. The high frequency structure simulator (HFSS) is used to design and simulate the antennas behaviour over the different frequency ranges. Measurements confirm the antenna characteristic as predicted in the simulation with a slight shift in frequencies.
High –Speed Implementation of Design and Analysis by Using Parallel Prefix Ad...IOSRJECE
The binary adder is the critical element in most digital circuit designs including the digital signal processors (DSP) and microprocessor data unit path. As such as extensive research continues to be focused on improving the power, delay, improvement of the adder. The design and analysis of the parallel prefix adders (carry select adders) is to be implemented by using Verilog. In VLSI implementations, parallel prefix adders are very high speed performance. Binary adders are one of the most essential logic elements within a digital system. Therefore, binary addition is essential that any improvement in binary addition can result in a performance boost for any computing system and hence, help improve the performance of the entire system. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates (the Kogge-Stone, sparse Kogge-Stone, Ladner fischer adder, Brent-Kung adder) and compares them to the simple Ripple Carry Adder (RCA) for high number of binary bits.
Vehicle security system using ARM controllerIOSRJECE
Road accidents are a human tragedy. This involves high human suffering and pecuniary costs in terms of untimely sudden death, injuries and loss of inherent income. In this paper, a system is proposed where the main objective is to detect road signs from a moving vehicle and also enables intelligent detection of an accident at any place and reports about the accident on predefined numbers of dear one .The system will use one signal transmitter in each and every symbol or message board at road side and whenever any vehicle passes from that symbol the receiver situated inside the vehicle i.e. In-Car System will receive the signals and display proper message or the symbol details on display connected in car. Road Traffic Sign Detection is a technology by which a vehicle is able to recognize the traffic signs which are on the road e.g. ”speed limit” or ”school” or ”turn ahead”. This infrastructure is expected to deliver multiple road safety and driving assistance applications
This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and power delay product. We designed each of these techniques by using Spice simulation soft wares.
A Plasma Tweeter is an audio device which uses a pair of electrodes as a source of sound. It has a clear reproduction and Omni directional radiation pattern. A plasma tweeter has a better frequency response than a conventional speaker and does not involve any moving part (diaphragm) and thus has less reverberation and no wear and tear. Plasma tweeters invented earlier were very expensive. This paper presents a plasma audio system which is making the regular audio system more efficient because of the use of the latest plasma tweeter. Here the objective is to create a low cost and more efficient version of the most speakers invented till now with the complete audio system.
Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash AdcIOSRJECE
The present investigation proposed a low power encoding scheme of thermometer code to binary code converter for flash analog to digital conversion by the design of different circuits. In this paper, we have proposed three encoding techniques for the conversion of analog to digital signal using Multiplexer based encoder, heterogeneous encoder and encoding technique using dynamic logic circuits providing low power of operation and we compare the results obtained from each technique based on power consumption. The multiplexer based encoder was designed with the help of multiplexers which consumes less amount of power comparing with other designs.
Performance Analysis of Low Loss Gas Filled Hollow Core Photonic Crystal Fibe...IOSRJECE
A Kagome lattice hollow core photonic crystal fiber was filled by pumping pressurized inert gases (Argon, Krypton, Xenon) through the hollow core and wave guidance properties were observed for terahertz (THz) frequency. By using finite element method (FEM), effective material loss and confinement loss have been observed for different strut width, core diameter and different inert gases. Confinement of light has achieved through the hollow core for THz frequency. Lowest EML of 7.90x10-4 cm-1 is found for 5 µm strut width and 800 µm core diameter at 1 THz frequency for Xenon gas pumped at 1000 bar pressure. Observation and findings of this paper will contribute in the ongoing research trends on THz waveguide
FPGA Based Implementation of AES Encryption and Decryption with Low Power Mul...IOSRJECE
: Encryption is important to keep the confidentiality of data. There are many of encryption algorithms to ensure the data, but should be the select the algorithm depended on the fast, strong and implementation. For that choose the advance encryption standard (AES) algorithm for encryption data because speed and easy implementation on small devices and some the feature for it. In this paper, implementation of encryption and decryption of AES algorithm is presented with a High Secured Low Power Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) . The main feature in the proposed MLUT based S-Box is that, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(28 ) and affine transformation. Thus, the proposed S-Box is simpler in circuit implementation and lower in power dissipation.
Detection of Type-B Artifacts in VEPs using Median Deviation AlgorithmIOSRJECE
The primary goal of this research work is to introduce temporal artifact detection strategy to detect non responsive channels and trials in visual evoked potentials(VEPs) by tracing out the signals with very low energy and to remove artifacts in multichannel visual evoked potentials. The non responsive channels and trials are identified by calculating the energy of the average evoked potential of each channel, and the energy of the average evoked potential of each trial. Then channel wise and trial wise median test is conducted to detect and remove non-responsive channels and trials. An artifact is defined as any signal that may lead to inaccurate classifier parameter estimation. Temporal domain artifact detection tests include: a clipping (CL) test detect amplitude clipped EPs in each channel, a standard deviation (STD) test that can detect signals with little or abnormal variations in each channel, a kurtosis (KU) test to detect unusual signals that are not identified by STD and CL tests and median deviation test to detect signals containing large number of samples with very small deviation from their normal values. An attempt has been made to apply these techniques to 14-channel visual evoked potentials (VEPs) obtained from different subjects.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
Optimum Location of EDFA based on Eye Diagram, Q-factor and Bit Error Rate Me...IOSRJECE
This work investigated the optimum location of Erbium Doped Fiber Amplifier (EDFA) in an optical system based on analysis of BER analyzer metrics by simulation approach using Optisystem software. The simulation model will be studied based on many parameters as input power (dBm), gain of Amplifier (dBm), fiber cable length (km) and attenuation coefficient (dB/km), there are two different parameters will be analyzed at five different locations of EDFA which are Q-Factor and Bit Error Rate (BER) and also Eye Diagram, which Q-factor and BER are measurement parameters used to measure the quality of received signal at receiver.
VANET based Intelligent TransportationSystem using Li-Fi technologyIOSRJECE
VANET (Vehicular Ad-hoc Network) is a wireless network in vehicle for Intelligent Transportation System (ITS).In thispaper, we propose a mechanism toprevent accidents due to sleepiness and alcohol consumption of the driver. Vehicle to Vehicle (V2V) communication is the most effective solutionwe have used in order to prevent accidents using the Li-Fi technology.
An Even Data-Distribution Protocolfor Highly Dynamic VANETIOSRJECE
Vehicular ad -hoc network (VANET) has a problem called high mobility and uneven distribution of vehicles which affect the performance of routing. The high mobility may changes arrangements of a network, and the uneven distribution of vehicles leads to node failures due to network partition; In an urban environment the high density of vehicle cause drastic wireless contentions. In this paper, we use the Even Data Distribution (EDD) protocol to make uneven distribution of data transmission in the vehicular ad-hoc network to even distribution. In which the high mobility of vehicles in urban areas causes loss of data due to uneven distribution in order to reduce the impact of uneven distribution we transform it into even distribution using EDD protocol.
Performance Investigation and Enhancement of Fiber Bragg Gratingfor Efficient...IOSRJECE
In this paper, the performance of various windowfunctions for Fiber Bragg Grating Sensor (FBGS)is investigated and evaluated in order to get optimized reflection spectrum with high reflectivity and an efficient side lobe suppression for efficient sensing measurement applications.For this purpose, a wide range of design parameters which include grating length and refractive index modulation amplitudehas been chosen to evaluate the sensor design. The performances of the different windowfunctions have been then compared in terms of reflectivity, full width half maximum bandwidth (FWHM), and sidelobe level(SLL) so as to get the most suitable design parametersto be used for sensing measurement.The simulation results presented in this paper show the effectiveness of the optimizedFBG sensor, which can be further implemented for high performance sensing applications.
Surface Plasmon Modes of Dielectric-Metal-Dielectric Waveguides and ApplicationsIOSRJECE
The dielectric-metal-dielectric plasmonic waveguide structures find applications in integrated optics and fiber polarizers and sensors. Surface plasmon waves guided by thin metal film have been intensively studied over the last two decades. However, most studies have been confined to relatively low index dielectrics. With growing interest in silicon photonics and other semiconductors dielectric of relatively higher dielectric constant we carried out a detailed study of the modes supported by a metal filmbetween dielectrics of relatively higher dielectric constant. The study clearly shows that both modes, the“antisymmetric” (푎푏 ) short range and “symmetric” (푠푏 ) long range bound modes can exist only when the contrast between the indices is low. For high contrast the symmetric mode transforms into a leaky mode.For completeness we also includethe antisymmetric leaky (푎푙 ) mode and symmetric leaky (푠푙 ) mode in our study, although they are not important for guided wave structures. We have also included “leaky modes” in the bound mode domain as solution of the boundary value problem as reported in some early studies. We have also considered some applications of the DMD waveguides with an emphasis on identifying the participating mode in each application
Performance Analysis of Optical Amplifiers (EDFA and SOA)IOSRJECE
In the optical transmission systems attenuation causes signal power to drop through an optical fiber link, so need to use amplifiers to increase signal power with low noise. Semiconductor Optical Amplifier (SOA) and Erbium-Doped Fiber Amplifier (EDFA) are two of the main types of optical amplifiers, and they were used in this simulation model to analyze their performance, with a data rate of 622 Mb/s (STM-4 level) and 170 km optical fiber length for each simulation model. This was simulated by using OptiSystem simulator, including the main parameters of the optical transmission system as input power (dBm), optical fiber cable length (km) and attenuation per length of optical fiber cable (dB/km), also there are three parameters will be considered which they are output power (dBm), Q-Factor and Bit Error Rate (BER) at receiver, and also Eye Diagram.
Optimum Location of EDFA based on Eye Diagram, Q-factor and Bit Error Rate Me...IOSRJECE
This work investigated the optimum location of Erbium Doped Fiber Amplifier (EDFA) in an optical system based on analysis of BER analyzer metrics by simulation approach using Optisystem software. The simulation model will be studied based on many parameters as input power (dBm), gain of Amplifier (dBm), fiber cable length (km) and attenuation coefficient (dB/km), there are two different parameters will be analyzed at five different locations of EDFA which are Q-Factor and Bit Error Rate (BER) and also Eye Diagram, which Q-factor and BER are measurement parameters used to measure the quality of received signal at receiver.
Study of RF-MEMS Capacitive Shunt Switch for Microwave Backhaul Applications IOSRJECE
In this research paper, we have proposed a new type of capacitive shunt RF-MEMS switch. MicroElectro-Mechanical System (MEMS) is a combination of mechanical and electromagnetics properties at micro level unit. This MEMS switch can be used for switching purpose at RF and microwave frequencies, called RFMEMS switch. The RF-MEMS switch has a potential characteristics and superior performances at radio frequency. The MEMS switch has excellent advantages such as zero power consumption, high power handling capacity, high performance, and low inter-modulation distortion. In this proposed design, a new type of capacitive shunt switch is designed and analyzed for RF applications. The switch is designed both in UP and DOWN-states. The proposed switch design consists of substrate, co-planar waveguide (CPW), dielectric material and suspended metallic bridge. The proposed MEMS switch has dimension of 508 µm × 620 µm with a height of 500 µm and implemented on GaAs as a substrate material with relative permittivity of 12.9. The geometry and results of the proposed switch is designed using Ansoft HFSS electromagnetic simulator based on finite element method (FEM). The electrostatic and electromagnetic result showed better performances such as return loss, insertion loss and isolation. The switch has also excellent isolation property of -48 dB at 26 GHz.
Broad-Spectrum Model for Sharing Analysis between IMTAdvanced Systems and FSS...IOSRJECE
An appraisal of orthogonal frequency division multiplexing (OFDM) accredited for IMT-Advanced has been well thought-out in this letter. Derivation of the power spectral density (PSD) produce new model which easily assess the interfering signal power that appears in the band of a victim system without a spectrum emission mask. Furthermore, the broad-spectrum investigative model (BIM) can assess the interference from the 4G systems into FSS systems, when transmit power is unallocated to some sub-carriers overlapping the band of the victim system. Closed form is derived to create the model.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 2, Ver. I (Mar.-Apr. 2017), PP 52-56
www.iosrjournals.org
DOI: 10.9790/2834-1202015256 www.iosrjournals.org 52 | Page
Design of Counter Using SRAM
Rajat Kumar Dwibedi1
, L.Pattathurani2
1
(Assistant Professor/ECE, Jeppiaar SRR Engineering College, Chennai, India)
2
(Assistant Professor/EEE, Jeppiaar Institute Of Technology, Chennai, India )
Abstract: In digital logic and computing, a counter is a device which stores the number of times a particular
event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high
noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing
every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on
the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage
on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation
.Finally we proposed counter using SRAM model, provides the best resolution, high output current and good
output-input current linearity.
Keywords: CMOS(Complementary Metal Oxide Semiconductor),MOSFET(Metal Oxide Semiconductor Field
Effect Transistor), SRAM(Static Random Access Memory), TTL(Transistor Transistor Logic),VLSI(Very Large
Scale Integrated Circuits).
I. Introduction To Counter
Counter used in electronics, computing and mechanical counting devices. In digital logic a counter is a
device which stores the number of times a particular event or process has occurred, often in relationship to a
clock signal. The most common type is sequential digital logic circuit with an input line called the "clock"
and multiple output lines. The values on the output lines represent a number in the binary or BCD number
system. Each pulse applied to the clock input increments or decrements the number in the counter. A counter
circuit is usually constructed of a number of flip flops connected in cascade. Counters are a very widely-used
component in digital circuits, and are manufactured as separate integrated circuits and also incorporated as parts
of larger integrated circuits.
A. Types of Counter
There are seven types of electronic counters are as follows.
Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops.
Synchronous counter – all state bits change under control of a single clock.
Decade counter – counts through ten states per stage.
Up/down counter – counts both up and down, under command of a control input.
Ring counter – formed by a shift register with feedback connection in a ring.
Johnson counter – a twisted ring counter.
Cascaded counter.
Each is useful for different applications. Usually, counter circuits are digital in nature, and counting
natural binary. Many types of counter circuits are available as digital building blocks, for example a number of
chips in the 4000 series implement different counters. Occasionally there are advantages to using a counting
sequence other than the natural binary sequence such as the binary coded decimal counter, a linear feedback
shift register counter, or a fray- code counter.
B. Asynchronous Counter
Fig.1 Asynchronous Counter
2. Design of Counter Using SRAM
DOI: 10.9790/2834-1202015256 www.iosrjournals.org 53 | Page
To add additional flip-flops, always inverting the output to its own input, and using the output from the
previous flip-flop as the clock signal. The result is called a ripple counter, which can count to 2
n
- 1 where n is
the number of bits (flip-flop stages) in the counter. Ripple counters suffer from unstable outputs as the
overflows "ripple" from stage to stage, but they do find frequent application as dividers for clock signals, where
the instantaneous count is unimportant, but the division ratio overall is (to clarify this, a 1-bit counter is exactly
equivalent to a divide by two circuit; the output frequency is exactly half that of the input when fed with a
regular train of clock pulses).The use of flip-flop outputs as clocks leads to timing skew between the count data
bits, making this ripple technique incompatible with normal synchronous circuit design styles.
II. Existing System
A. Conventional Counter
Fig.2 Conventional Counter
Counter built from four positive edge triggered d type flip flops connected in series. Clock
pulses are fed into CLK input of FF0 whose output ,Q0 provides 2^0 output for flip flop 1 after 1 clock
pulse the rising edge of the q bar output of each flip flop triggers the clock input of next flip flop at half the
frequency of the clock pulses applied to its input. The Q outputs then represents a four bit binary count with
Q0 to Q3 representing 2^0(1) to 2^3(8) respectively.
Assuming that the four Q outputs are initially at 0000 ,the rising edge of the first clock pulse applied
will cause the output Q0 to go to logic 1.the next clock pulse will make Q0 output return to logic 0,and at the
same time Q0bar go from 0 to As Q0bar (and the clock input o flip flop 1 goes high ) this will now make Q1
high , indicating a value of 2^1 on the Q outputs .
The next (third clock pulse will cause Q0 to go to logic 1 again, so both Q0 and Q1 will now
be high , making the four bit output 1100.the fourth clock pulse will make both Q0and Q1 return to 0 and
as Q1bar will go high at this time, this will toggle flip flop 2,making Q2 high and indicating 0010 at the
outputs. Reading the output word from right to left ,the Q outputs therefore continue to represent a binary
number equaling the number of input pulses received at the clock input of flip flop 0.as this is a four stage
counter the flip flop will continue to toggle in sequence and the four Q outputs will output a sequence of binary
values from 0000 to 1111, before the output returns to 0000. CMOS is a technology for constructing
integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other
digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors
(CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Two
important characteristics of CMOS devices are high noise immunity and low static power consumption.
Since one transistor of the pair is always off, the series combination draws significant power only momentarily
during switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor–transistor logic (TTL) or NMOS logic, which normally have some standing current
even when not changing state. CMOS also allows a high density of logic functions on a chip. It was
primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.
CMOS circuits use a combination of p-type and n-type metal– oxide–semiconductor field-effect transistor
(MOSFETs) to can be implemented with discrete devices for demonstrations, commercial CMOS products
are integrated circuits composed of up to billions implement logic gates and other digital circuits. Although
CMOS logic of transistors of both types, on a rectangular piece of silicon of between 10 and 400 mm
2
.
III. Proposed System
Static CMOS circuits are constructed in such a way that all PMOS transistors must have either an input
from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either
an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low
resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a
high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high
3. Design of Counter Using SRAM
DOI: 10.9790/2834-1202015256 www.iosrjournals.org 54 | Page
resistance between source and drain when a low gate voltage is applied and low resistance when a high gate
voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a
pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the
nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gates causes the reverse.
This arrangement greatly reduces power consumption and heat generation. However, during the switching
time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief
spike in power consumption and becomes a serious issue at high frequencies.
In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low,
the output is high, and when the input is high, the output is low. Because of this behavior of input and
output, the CMOS circuit's output is the inverse of the input.
A. Counter using SRAM
Fig.3 Counter using SRAM
In the above diagram there are totally 4 NMOS and 2 PMOS used. WL act as the reference line, BL and
BL bar are the inputs. If BL=0 BL bar=1 whereas BL acts as the Vdd and BL bar act as the ground and
vice versa as required. Q and Q bar are the outputs.
Q is given as the input M1 and M2 ,for which the output is obtained at Q bar which should be the
complement of Q(Input).
Similarly, Q bar is given as the input to M3 and M 4 for which the output is taken from Q
,Which should be the complement of Q bar(input).
B. Four Bit Counter Using SRAM
Fig.4 4-bit Counter using SRAM
4. Design of Counter Using SRAM
DOI: 10.9790/2834-1202015256 www.iosrjournals.org 55 | Page
The above diagram is the cascaded four bit counter using SRAM ,Where Q bar of one counter is given
as input to the next counter. The principle of the matrix circuit is that if value of the pixel is higher than the
value of reference of tension (Vr),the exit of the comparator is in a high state (5V). On the other hand, if value
of the pixel is less than the value of the tension Vr, the exit of the comparator is in a low state (0V). After the
comparison, the exits of the comparator are entered to the logical gating circuit AND. In the logical gating
circuit AND, if signal comparator from line and row are 5V and corresponding LED is active.
IV. Simulation Results And Discussions
4.1 Counter Using CMOS
4.2 Counter Using SRAM
4.3. Power Output for Existing System
4.4.Power output for Proposed System
5. Design of Counter Using SRAM
DOI: 10.9790/2834-1202015256 www.iosrjournals.org 56 | Page
V. Conclusion
In this paper we have designed a counter using a SRAM whereas previously the counter was
designed using a D flip flop and CMOS in the existing system. In the proposed system the counter SRAM
has a reduced power consumption when compared to that of the existing system ,since the transistors
used in this system are connected in series, the power applied for the first transistor is used by all the
succeeding transistors in the system .Also the use SRAM has many advantages such as Low hardware
complexity, low cost for fabrication, mechanical flexibility, Strong optical absorption and efficient emission.
References
[1]. A high speed digital CMOS Divide-by-N frequency divider by S.Abdel-Hafeez,S Harb,W.Eisenstadt - 2008.
[2]. A Digital CMOS parallel counter architecture based on state look- ahead logic‖ by S. Abdel- Hafez; A.Gordon-Ross -2011 .
[ 3 ] . A digital CMOS parallel counter Architecture for frequency Divider Based on transmission Gate Logic by Anil Kumar
Choudhary,K pitambar patra - 2014.