The presentation contains Power reduction in clock networks, CLOCK GATING, REDUCED SWING CLOCK, CMOS FLOATING NODE.

1. Presented by
Shruti Shreya
M. Tech (VLSI)

2. INTRODUCTION
High Power dissipation leads to
 High efforts for cooling
 Increasing operational costs
 Reduced reliability
 Levels of optimization
System
Algorithm
Architecture
Gate
Transistor
T
T
+
ST1
ALU
MEM
MEM
MP3
Savings Speed Error
> 70 %
40-70 %
25-40 %
15-25 %
10-15 %
Seconds
Minute
Minutes
Hour
Hours
> 50 %
25-50 %
15-30 %
10-20 %
5-10 %

3. Power reduction in clock networks
In special technique
• More manual effort is required
• Design automation is less efficient in this area.
Clock signal: main source of power dissipation due to high
frequency and load
In a synchronous digital chip, the clock signal is generally one
with the highest frequency.
Clock distribution can take up to 40% of the total power
dissipation of a high performance microprocessor

4. CLOCK GATING
Technique for power reduction of clock signals
Clock gating saves power by reducing unnecessary clock activities
inside the gated module.
Usually, NAND or NOR gate is used in this process.
It is the process of mask the unwanted signal from propagation forward.
Gating signal should be enabled or disabled at a much slower rate compared
to the clock frequency.

5. REDUCED SWING CLOCK
P = CV2 f
“Reducing the clock swing by half” is another technique.
The charge sharing principle with stacked inverters is used to generate the half swing clock
signal.
The circuit relies on the parasitic loading of the clock lines CP and CN to achieve the charge
sharing effect.
To obtain the proper half swing waveform, Cp = Cn.

6. OSCILLATOR CIRCUIT FOR CLOCK GENERATION
I0- serves as a gain amplifier for the feedback oscillator
I1 reshapes the waveform to obtain a proper digital clock signal
For good stability of oscillation, a large gain is set on I0.
Large gain large voltage swing and short circuit current
increase the power dissipation.
It is important to tune the transistor sizes of the inverters.

7. CMOS FLOATING NODE
Floating nodes are
 internal nodes of a circuit that
 not driven to a logic 0 or logic 1
They should always be avoided
causes overheating and permanently failure of circuit.
Example:
If signals SEL_A and SEL_B are both not asserted, signal OUT will float to an
unknown level.
Downstream logic may interpret OUT as a logic 1 or a logic 0.

8. REDUCTION OF CMOS FLOATING NODE
Tristate Keeper Circuit
• Applicable when a chip enters in sleep mode or partial
power down mode and busses are not in used.
Blocking Gate
 NAND is used as blocking gate
 It requires a control signal for proper operation.
 This technique is also useful in blocking unwanted signal
transitions, thus saving power.