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High Speed R-to-R Input Comparator Circuit Design and Optimization

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Pushpak Dagade

Part of my Master's Thesis at IIT Delhi.

Engineering
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High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Design of a High Speed, Rail-to-Rail input CMOS comparator 1 Pushpak Dagade Under the guidance of Prof. G. S. Visweswaran, March 13, 2014 1 This work is a part of my eļ¬€ort towards my M.Tech Project 1 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References My comparator design speciļ¬cations Resolution: 2mV Delay: ā‰¤ 500ps ICMR: 0 āˆ’ 1.2V (Rail to Rail) Technology: UMC 130nm Vref Vin Vout Cmp Figure: Comparator Symbol 2 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit Topology The required speciļ¬cations demand a high speed comparator circuit topology 3 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References High speed comparator circuit topology LatchPreamp Postamp Vin Vref Vout All the stages are essentially gain stages For a low speed comparator, only the 1st stage can be suļ¬ƒcient Post ampliļ¬er stage can be omitted for medium speed comparators 4 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References NMOS input preampliļ¬er stage Vdd Vdd Vdd VddVdd Vgn+ Vgnāˆ’ X1 X2 X9X10 X7 X8 X3 X4 X5 X6 Vin Vref ICMR ā‰ˆ 0.3V to 1.2V Gain stages can be modiļ¬ed/added as per requirement Region of operation: small signal, linear 2 2 If a very large signal is given as input, overdrive recovery problem may occur, resulting in very slow output response. There are solutions to this problem 5 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Latch Stage Vbiasn X18X15 X17 X16 Vdd X21 X19 X20 Vgn+ Vgnāˆ’ Vloāˆ’ Vlo+ Figure: Diļ¬€erential ampliļ¬er loaded with a latch Can omit the diļ¬€erential pair if suļ¬ƒcient gain available from preampliļ¬er stage Region of operation: small to large signal, linear 6 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Post ampliļ¬er stage X22 X23 X27 X24 X25 X26 Vdd Vdd Vdd Vdd Vout X29 X28 vlo+ vloāˆ’ Figure: Self biased diļ¬€erential ampliļ¬er followed by inverter Quickly generates large amounts of currents Region of operation: large signal, can be non-linear Inverter acts as output driver Also acts a low gain stage 7 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References NMOS input comparator topology Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vdd Vdd Vout Vin Vref Figure: All the 3 stages put together ICMR ā‰ˆ 0.3V to 1.2V (Required: 0V to 1.2V ) 8 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References PMOS input comparator topology Vdd Vdd Vdd Vdd Vout Vdd Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vin Vref Circuit is simply the complimentary of the circuit shown in the previous slide ICMR ā‰ˆ 0V to 0.8V Notice, that post ampliļ¬er stage still remains the same! This gives a hint in combining the 2 comparators for a comparator with rail-to-rail ICMR! 9 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Rail-to-Rail ICMR Speciļ¬cation ICMR of NMOS input comparator: 0.3V to 1.2V ICMR of PMOS input comparator: 0V to 0.8V āˆ“ Both together can provide rail to rail ICMR The 2 comparators can be combined together at the post ampliļ¬er stage 10 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Rail-to-Rail ICMR Comparator topology Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vdd Vdd Vout Vdd Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vin Vref Vin Vref Figure: The complete comparator circuit 11 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit Optimization How to ļ¬nd optimum values of transistor sizings, for a given circuit topology, so as to meet the required speciļ¬cations? 12 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Practical problems Analysis given in books useful for qualitatively purposes & rough hand calculations Not of much use quantitatively, since calculations based on ideal mosfet equations, not true practically Example: You will always have some non zero oļ¬€set voltage VOS for the comparator if equations given in books are used Also, circuit cannot be simulated manually for a large number set of inputs All these demand for some form of automation & optimization 13 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit optimization algorithm ļ¬‚owchart Create controller script with variable ranges and cost function Create netlist with random values for variables Simulate using circuit simulator Create netlist from template with the new parameter values Generate new values for variable from the past history (using optimization algorithm) Read output & calculate cost function value Is cost function value desirable? Create netlist template Done YES NO 14 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Simulation Results After doing a few million iterations of optimization, in multiple steps, for almost a month, I ļ¬nally got the transistor sizings which give me the desired speciļ¬cations. Here are some simulation results on the circuit ļ¬le with optimum transistor sizings... 15 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 3mV 16 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.3V 17 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.6V 18 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.9V 19 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 1.198V 20 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 3mV 21 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.3V 22 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.6V 23 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.9V 24 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 1.198V 25 / 26
High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References References Philip E. Allen, Douglas R. Holberg (2007) CMOS Analog Circuit Design Oxford University Press (2007) David A. Johns, Kenneth W. Martin, Tony Chan Carusone (2012) Analog Integrated Circuits Design John Wiley & Sons (2012) 26 / 26
High Speed, R-to-R input comparator Pushpak Dagade Appendix Appendix: Softwares used Circuit simulator: ngspice http://ngspice.sourceforge.net/ Optimization algorithm: Python script http://www.h-renrew.de/h/python_spice/ optimisation.html Controller: Python script You need to make this as per your requirements. Some examples available here: http://www.h-renrew.de/h/python_spice/ optimisation.html Only open source free softwares were used for circuit simulation and optimization! 27 / 26

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High Speed R-to-R Input Comparator Circuit Design and Optimization

  • 1. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Design of a High Speed, Rail-to-Rail input CMOS comparator 1 Pushpak Dagade Under the guidance of Prof. G. S. Visweswaran, March 13, 2014 1 This work is a part of my eļ¬€ort towards my M.Tech Project 1 / 26
  • 2. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References My comparator design speciļ¬cations Resolution: 2mV Delay: ā‰¤ 500ps ICMR: 0 āˆ’ 1.2V (Rail to Rail) Technology: UMC 130nm Vref Vin Vout Cmp Figure: Comparator Symbol 2 / 26
  • 3. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit Topology The required speciļ¬cations demand a high speed comparator circuit topology 3 / 26
  • 4. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References High speed comparator circuit topology LatchPreamp Postamp Vin Vref Vout All the stages are essentially gain stages For a low speed comparator, only the 1st stage can be suļ¬ƒcient Post ampliļ¬er stage can be omitted for medium speed comparators 4 / 26
  • 5. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References NMOS input preampliļ¬er stage Vdd Vdd Vdd VddVdd Vgn+ Vgnāˆ’ X1 X2 X9X10 X7 X8 X3 X4 X5 X6 Vin Vref ICMR ā‰ˆ 0.3V to 1.2V Gain stages can be modiļ¬ed/added as per requirement Region of operation: small signal, linear 2 2 If a very large signal is given as input, overdrive recovery problem may occur, resulting in very slow output response. There are solutions to this problem 5 / 26
  • 6. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Latch Stage Vbiasn X18X15 X17 X16 Vdd X21 X19 X20 Vgn+ Vgnāˆ’ Vloāˆ’ Vlo+ Figure: Diļ¬€erential ampliļ¬er loaded with a latch Can omit the diļ¬€erential pair if suļ¬ƒcient gain available from preampliļ¬er stage Region of operation: small to large signal, linear 6 / 26
  • 7. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Post ampliļ¬er stage X22 X23 X27 X24 X25 X26 Vdd Vdd Vdd Vdd Vout X29 X28 vlo+ vloāˆ’ Figure: Self biased diļ¬€erential ampliļ¬er followed by inverter Quickly generates large amounts of currents Region of operation: large signal, can be non-linear Inverter acts as output driver Also acts a low gain stage 7 / 26
  • 8. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References NMOS input comparator topology Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vdd Vdd Vout Vin Vref Figure: All the 3 stages put together ICMR ā‰ˆ 0.3V to 1.2V (Required: 0V to 1.2V ) 8 / 26
  • 9. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References PMOS input comparator topology Vdd Vdd Vdd Vdd Vout Vdd Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vin Vref Circuit is simply the complimentary of the circuit shown in the previous slide ICMR ā‰ˆ 0V to 0.8V Notice, that post ampliļ¬er stage still remains the same! This gives a hint in combining the 2 comparators for a comparator with rail-to-rail ICMR! 9 / 26
  • 10. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Rail-to-Rail ICMR Speciļ¬cation ICMR of NMOS input comparator: 0.3V to 1.2V ICMR of PMOS input comparator: 0V to 0.8V āˆ“ Both together can provide rail to rail ICMR The 2 comparators can be combined together at the post ampliļ¬er stage 10 / 26
  • 11. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Rail-to-Rail ICMR Comparator topology Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vdd Vdd Vout Vdd Vdd Vdd Vdd VddVdd Vdd Vdd Vdd Vin Vref Vin Vref Figure: The complete comparator circuit 11 / 26
  • 12. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit Optimization How to ļ¬nd optimum values of transistor sizings, for a given circuit topology, so as to meet the required speciļ¬cations? 12 / 26
  • 13. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Practical problems Analysis given in books useful for qualitatively purposes & rough hand calculations Not of much use quantitatively, since calculations based on ideal mosfet equations, not true practically Example: You will always have some non zero oļ¬€set voltage VOS for the comparator if equations given in books are used Also, circuit cannot be simulated manually for a large number set of inputs All these demand for some form of automation & optimization 13 / 26
  • 14. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Circuit optimization algorithm ļ¬‚owchart Create controller script with variable ranges and cost function Create netlist with random values for variables Simulate using circuit simulator Create netlist from template with the new parameter values Generate new values for variable from the past history (using optimization algorithm) Read output & calculate cost function value Is cost function value desirable? Create netlist template Done YES NO 14 / 26
  • 15. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Simulation Results After doing a few million iterations of optimization, in multiple steps, for almost a month, I ļ¬nally got the transistor sizings which give me the desired speciļ¬cations. Here are some simulation results on the circuit ļ¬le with optimum transistor sizings... 15 / 26
  • 16. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 3mV 16 / 26
  • 17. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.3V 17 / 26
  • 18. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.6V 18 / 26
  • 19. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 0.9V 19 / 26
  • 20. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References DC Simulation Results 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (V) 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin Vout Figure: Vref = 1.198V 20 / 26
  • 21. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 3mV 21 / 26
  • 22. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.3V 22 / 26
  • 23. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.6V 23 / 26
  • 24. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 0.9V 24 / 26
  • 25. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References Transient Simulation Results 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Time 1e 9 0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Vin (smallest) Vout GND VDD Figure: Vref = 1.198V 25 / 26
  • 26. High Speed, R-to-R input comparator Pushpak Dagade Speciļ¬cations Circuit Topology NMOS input comparator PMOS input comparator R2R ICMR comparator Circuit optimization Simulation Results DC Simulation Transient Simulation References References Philip E. Allen, Douglas R. Holberg (2007) CMOS Analog Circuit Design Oxford University Press (2007) David A. Johns, Kenneth W. Martin, Tony Chan Carusone (2012) Analog Integrated Circuits Design John Wiley & Sons (2012) 26 / 26
  • 27. High Speed, R-to-R input comparator Pushpak Dagade Appendix Appendix: Softwares used Circuit simulator: ngspice http://ngspice.sourceforge.net/ Optimization algorithm: Python script http://www.h-renrew.de/h/python_spice/ optimisation.html Controller: Python script You need to make this as per your requirements. Some examples available here: http://www.h-renrew.de/h/python_spice/ optimisation.html Only open source free softwares were used for circuit simulation and optimization! 27 / 26