Measuring the cutoff frequency of a low pass filterHasnain Ali
It is required to setup an automated test and measurement system for measuring the cutoff frequency of a low pass filter using LabView and estimate the frequency response of the filter.
In digital logic and computing, a counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation .Finally we proposed counter using SRAM model, provides the best resolution, high output current and good output-input current linearity.
Measuring the cutoff frequency of a low pass filterHasnain Ali
It is required to setup an automated test and measurement system for measuring the cutoff frequency of a low pass filter using LabView and estimate the frequency response of the filter.
In digital logic and computing, a counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. CMOS devices are designed for high noise immunity and low static power consumption. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gate causes the reverse. This arrangement greatly reduces power consumption and heat generation .Finally we proposed counter using SRAM model, provides the best resolution, high output current and good output-input current linearity.
Describes principles of asynchronous serial communication. Explains and compares the principles and features of RS-232, RS-422 and RS-485 standards. Also outlines various registers and programming of PC16550 Universal Asynchronous Receiver/Transmitter provided by many microcontrollers,
Rfid interfacing & controlling with 8051Akshay Dhole
RFID-
Radio frequency identification (RFID) is a generic term that is used to describe a system that transmits the identity (in the form of a unique serial number) of an object or person wireless, using radio waves.
The information on the micro-chip can be read automatically, at a distance, by another wireless machine
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands.
Describes principles of asynchronous serial communication. Explains and compares the principles and features of RS-232, RS-422 and RS-485 standards. Also outlines various registers and programming of PC16550 Universal Asynchronous Receiver/Transmitter provided by many microcontrollers,
Rfid interfacing & controlling with 8051Akshay Dhole
RFID-
Radio frequency identification (RFID) is a generic term that is used to describe a system that transmits the identity (in the form of a unique serial number) of an object or person wireless, using radio waves.
The information on the micro-chip can be read automatically, at a distance, by another wireless machine
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands.
Counters:
Introduction, Asynchronous counter, Terms related to counters, IC-7493 (4-bit binary counter), Synchronous counter, Bushing, Type T-Design, Type JK Design, Presettable counter, IC-7490, IC 7492, Synchronous counter ICs, Analysis of counter circuits
Implementation of a digital multimeter using basic stamp2 on a professional development board. It also includes R2R ladder network for digital to analog conversion
Controlled power is a prerequisite of various sectors, including industries. The
implementation of microcontroller based firing angle control, using ATmega 32 MCU and
associated hardware circuitry is discussed here. Main emphasis is given on improved
performance of converter so as to achieve reliable and consistent power control. The power
control scheme uses commonly available components like ATmega-32 controller,
transistorized conditioning circuit, rectifier module, for firing angle control. The objective is
to achieve a reliable, affordable and accurate power control mechanism for the use of
industrial and household consumer applications, with superior performance.
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION...VLSICS Design
Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.
Analog to Digitalconvertor for Blood-Glucose Monitoringcsijjournal
ABSTRACT
This paper presents the design of a low-power CMOS current-frequency (I–F) Analog–Digital Converter. The ADC is designed for implantable blood-glucose monitoring. This current frequency ADC uses nArange of input currents to set and compare voltage oscillations against a self-produced reference to resolve 0–32nA with an accuracy of 5-bits at a 225MHz sampling rate. The comparator used is a dynamic latch comparator and the output is fetched from a 5-bit counter. This is designed in 180nm CMOS technology with a supply of 1.8V, it operating voltage taken here is 0.0- 1.8V with power consumption of 12.3nW using Cadence tools.
ANALOG TO DIGITALCONVERTOR FOR BLOOD-GLUCOSE MONITORING csijjournal
This paper presents the design of a low-power CMOS current-frequency (I–F) Analog–Digital Converter. The ADC is designed for implantable blood-glucose monitoring. This current frequency ADC uses nArange of input currents to set and compare voltage oscillations against a self-produced reference to resolve 0–32nA with an accuracy of 5-bits at a 225MHz sampling rate. The comparator used is a dynamic latch comparator and the output is fetched from a 5-bit counter. This is designed in 180nm CMOS technology with a supply of 1.8V, it operating voltage taken here is 0.0- 1.8V with power consumption of 12.3nW using Cadence tools.
On the Impact of Timer Resolution in the Efficiency Optimization of Synchrono...IJPEDS-IAES
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall efficiency
by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that comprises
duty-cycle and dead-time, and also converter frequency and analog-to-digital converter
accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.
Vulnerability of Synchrophasor-based WAMPAC Applications’ to Time-Synchroniza...Luigi Vanfretti
This paper experimentally assesses the impact of time synchronization spoofing attacks (TSSA) on synchrophasor-based Wide-Area Monitoring, Protection and Control applications. Phase Angle Monitoring (PAM), anti-islanding protection and power oscillation damping applications are investigated. TSSA are created using a real-time IRIG-B signal generator and power system models are executed using a real-time simulator with commercial phasor measurement units (PMUs) coupled to them as hardware-in-the-loop. Because PMUs utilize time synchronization signals to compute synchrophasors, an error in the PMUs’ time input introduces a proportional phase error in the voltage or current phase measurements provided by the PMU. The experiments conclude that a phase angle monitoring application will show erroneous power transfers, whereas the anti-islanding protection mal-operates and the damping controller introduces negative damping in the system as a result of the time synchronization error incurred in the PMUs due to TSSA. The proposed test-bench and TSSA approach can be used to investigate the impact of TSSA on any WAMPAC application and to determine the time synchronization error threshold that can be tolerated by these WAMPAC applications.
Part of Lecture series on EEE-413, Electrical Drives (DC Drives) delivered by me to students of VIII Semester B.E. (Electrical), Session 2018-19.
Z. H. College of Engg. & Technology, Aligarh Muslim University, Aligarh.
Missing materials will be uploaded shortly.
Please comment and feel free to ask anything related. Thanks!
Drives lec 19_20_Characteristics of a 1-Ph Full Converter fed Separately Exci...Mohammad Umar Rehman
Part of Lecture series on EEE-413, Electrical Drives (DC Drives) delivered by me to students of VIII Semester B.E. (Electrical), Session 2018-19.
Z. H. College of Engg. & Technology, Aligarh Muslim University, Aligarh.
Missing materials will be uploaded shortly.
Please comment and feel free to ask anything related. Thanks!
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
4. Digital Tachometer...Contd I
The technique employed in measuring the speed of a rotating shaft
is similar to the technique used in a conventional frequency counter.
However, the selection of the gate period is in accordance with the
rpm calibration.
Let us assume, that the rpm of a rotating shaft is R. Let P be the
number of pulses produced by the pick up for one revolution of
the shaft.
Therefore, in one minute the number of pulses from the pick up is
R × P.
Then, the frequency of the signal from the pick up is
R × P
60
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5. Digital Tachometer...Contd II
Now, if the gate period is G s the pulses counted are:
R × P × G
60
In order to get the direct reading in rpm, the number of pulses to be
counted by the counter is R, So we select the gate period as 60/P,
and the counter counts
R × P × 60
60 × P
= R pulses
and we can read the rpm of the rotating shaft directly.
BIE-601 U-5, L-3 24. 4. 2020 4 / 10
6. Digital Tachometer...Contd III
The relation between the gate period and the number of pulses pro-
duced by the pickup is G = 60/P.
If we fix the gate period as one second (G = 1 s), then the revolu-
tion pickup must be capable of producing 60 pulses per revolution.
BIE-601 U-5, L-3 24. 4. 2020 5 / 10
10. Digital C Meter...Contd
In a RC circuit, capacitance can be considered to be proportional to
the time constant.
When a capacitance is charged through a constant current source
and then discharged through a fixed resistance, 555 timer can be
used to measure the capacitance in a digital manner, along with
other necessary test equipment.
One obvious method to measure the time period of the oscillations.
By choosing the right size of the charging resistance, reading can
be obtained directly in µF or nF.
This measurement scheme can handle electrolytic capacitors of the
order of few thousands of µF
A better way is to measure the only the capacitance discharge time
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