Polynomial Division is a most common numerical
operation experienced in many filters and similar circuits next to
multiplication, addition and subtraction. Due to frequent use of
such components in mobile and other communication
applications, a fast polynomial division would improve overall
speed for many such applications. This project is to design,
develop and implement an efficient polynomial divider
algorithm, along with the circuit. Next its output performance
result is verified using Verilog simulation. A literature survey on
the normal division algorithms currently used by ALU’s to
perform division for large numbers, yielded Booth’s algorithm,
Restoring and Non-restoring algorithm. Verilog simulation of
these algorithms were used to derive efficiency in terms of the
timing characteristics, required chip area and power dissipation.
Initially, performance analysis of the existing algorithms was
done based on the simulated outputs. Later similar analysis with
the updated polynomial divider circuit is performed.
Computerized layout design methods use algorithms to represent space requirements, activity relationships, and graphical information to generate layouts. There are two main algorithm types: constructive algorithms which build layouts and improvement algorithms which optimize initial layouts. Examples of constructive algorithms are ALDEP and CORELAP, while CRAFT is an improvement algorithm that starts with an initial layout and iteratively exchanges departments to reduce transportation costs until no further improvements are possible. These computerized methods require inputs like area requirements, relationship charts, and flow data to systematically generate optimized layouts.
1) The document outlines various algorithms and software for solving plant layout problems, including pairwise exchange, graph-based, CRAFT, MCRAFT, BLOCPLAN, MIP, and LOGIC algorithms.
2) It provides details on each algorithm, including the objectives, inputs, procedures, and example outputs.
3) Finally, it lists several commercial facility layout software packages available from vendors such as Unigraphics Solutions, Production Modeling Corporation, Systemes Escape Temps, and Techomatrix Technologies.
Activity Diagram Model An activity diagram visually presents a series of actions or flow of control in a system similar to a flowshart or a data flow diagram. Activity diagrams are often used in business process modeling.
1) CRAFT is a tool that helps improve existing facility layouts by swapping departments to find an optimal floor plan. It uses a pairwise exchange algorithm.
2) CRAFT is useful for large facilities with many departments that would be difficult to manually optimize. It works best with process layouts.
3) CRAFT considers swapping only adjacent or similarly sized departments to evaluate improvements in cost and distance metrics between departments. The final solution depends on the initial layout provided.
UML Activity Diagrams show the flow of activities and processes within a system. They represent activities as rectangles and can depict conditional or parallel flows. Activity diagrams are used to model the workflow or business process perspective of a system by showing the sequence and flow from one activity to another. Key elements include initial and final activities, decisions, concurrency, and fork/join nodes. Activity diagrams differ from sequence diagrams in that they model activity flow rather than object interactions.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
This document discusses various structures for implementing discrete-time linear systems, both finite impulse response (FIR) and infinite impulse response (IIR) systems. It describes direct form, cascade form, and parallel form implementations for IIR systems using blocks for addition, multiplication, and delay. For FIR systems it discusses direct form and cascade implementations using tapped delay lines. It also covers implementations for linear phase FIR systems that reduce the number of multipliers required.
Compensator Design for Speed Control of DC Motor by Root Locus Approach using...IRJET Journal
The document discusses designing a compensator for speed control of a DC motor using the root locus approach in MATLAB. It first presents the problem statement of controlling the speed of a DC motor and introduces using a compensator as a controller. It then provides the design procedure for three types of compensators: lead compensator, lag compensator, and lag-lead compensator. The procedures include calculating transfer functions, plotting root loci, and determining pole and zero locations. Flow charts of the MATLAB program for each compensator type are presented. Finally, the results of applying each compensator are shown and their effects on performance parameters like settling time are compared.
Computerized layout design methods use algorithms to represent space requirements, activity relationships, and graphical information to generate layouts. There are two main algorithm types: constructive algorithms which build layouts and improvement algorithms which optimize initial layouts. Examples of constructive algorithms are ALDEP and CORELAP, while CRAFT is an improvement algorithm that starts with an initial layout and iteratively exchanges departments to reduce transportation costs until no further improvements are possible. These computerized methods require inputs like area requirements, relationship charts, and flow data to systematically generate optimized layouts.
1) The document outlines various algorithms and software for solving plant layout problems, including pairwise exchange, graph-based, CRAFT, MCRAFT, BLOCPLAN, MIP, and LOGIC algorithms.
2) It provides details on each algorithm, including the objectives, inputs, procedures, and example outputs.
3) Finally, it lists several commercial facility layout software packages available from vendors such as Unigraphics Solutions, Production Modeling Corporation, Systemes Escape Temps, and Techomatrix Technologies.
Activity Diagram Model An activity diagram visually presents a series of actions or flow of control in a system similar to a flowshart or a data flow diagram. Activity diagrams are often used in business process modeling.
1) CRAFT is a tool that helps improve existing facility layouts by swapping departments to find an optimal floor plan. It uses a pairwise exchange algorithm.
2) CRAFT is useful for large facilities with many departments that would be difficult to manually optimize. It works best with process layouts.
3) CRAFT considers swapping only adjacent or similarly sized departments to evaluate improvements in cost and distance metrics between departments. The final solution depends on the initial layout provided.
UML Activity Diagrams show the flow of activities and processes within a system. They represent activities as rectangles and can depict conditional or parallel flows. Activity diagrams are used to model the workflow or business process perspective of a system by showing the sequence and flow from one activity to another. Key elements include initial and final activities, decisions, concurrency, and fork/join nodes. Activity diagrams differ from sequence diagrams in that they model activity flow rather than object interactions.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
This document discusses various structures for implementing discrete-time linear systems, both finite impulse response (FIR) and infinite impulse response (IIR) systems. It describes direct form, cascade form, and parallel form implementations for IIR systems using blocks for addition, multiplication, and delay. For FIR systems it discusses direct form and cascade implementations using tapped delay lines. It also covers implementations for linear phase FIR systems that reduce the number of multipliers required.
Compensator Design for Speed Control of DC Motor by Root Locus Approach using...IRJET Journal
The document discusses designing a compensator for speed control of a DC motor using the root locus approach in MATLAB. It first presents the problem statement of controlling the speed of a DC motor and introduces using a compensator as a controller. It then provides the design procedure for three types of compensators: lead compensator, lag compensator, and lag-lead compensator. The procedures include calculating transfer functions, plotting root loci, and determining pole and zero locations. Flow charts of the MATLAB program for each compensator type are presented. Finally, the results of applying each compensator are shown and their effects on performance parameters like settling time are compared.
IRJET- A Study on Algorithms for FFT ComputationsIRJET Journal
This document analyzes and compares several algorithms for computing the Fast Fourier Transform (FFT), including Radix-2, Radix-4, and Split Radix algorithms. It examines each algorithm in terms of the amount of computations required, computation speed, and memory requirements. The Radix-4 algorithm requires the fewest floating point additions and multiplications, while the Split Radix algorithm has the fastest computation speed, especially for larger data sizes. However, all three algorithms have similar memory requirements. In general, the choice of best algorithm depends on the specific constraints of the application, such as available memory or need for computational speed.
This document summarizes a survey paper on using intelligent techniques like expert systems, fuzzy logic, genetic algorithms, and neural networks to solve facility layout problems (FLP). FLP involves assigning facilities to locations to minimize costs associated with facility interactions. The paper discusses conventional algorithms and intelligent techniques for FLP, including optimal algorithms like branch and bound, and suboptimal algorithms like construction and improvement heuristics.
An activity diagram visually presents a series of actions or flow of control in a system similar to a flowchart or a data flow diagram. They can also describe the steps in a use case diagram.
Activity diagrams can model the dynamic aspects of a system by showing the flow of control from one activity to the next. They are essentially flowcharts that can model business workflows and operations. Activity diagrams contain activity states, action states, transitions, objects, branches, forks, joins, and swimlanes. Action states are atomic while activity states can be decomposed into further detail. Transitions show the flow of control between states. Branches specify alternate paths. Forks allow concurrent flows while joins synchronize them. Swimlanes group activities by actor or thread.
IRJET- A Review on Single Precision Floating Point Arithmetic Unit of 32 Bit ...IRJET Journal
This document reviews a single precision floating point arithmetic unit that performs operations like addition, subtraction, and multiplication on 32-bit operands according to the IEEE 754 standard. It discusses how floating point units are widely used in areas like scientific computing and signal processing. The review covers the IEEE 754 standard specification for single precision floating point numbers, which uses 1 sign bit, 8 exponent bits, and 23 fraction bits. It also summarizes several previous studies that have designed and optimized reversible floating point arithmetic units to reduce costs like quantum cost, garbage outputs, and constant inputs.
This summary provides an overview of a document describing a teleoperated robot arm and hand system using shared control:
1. The system uses shared control between autonomous control, teleoperation, and simulation modules to coordinate a robot arm, dexterous hand, sensors, and a teleoperated mechanical arm and data glove.
2. Key aspects of the shared control include sensor data sharing between various sensors, multi-agent based sharing to perform complex tasks using different sensors, and human-machine interactive sharing between high-level planning and low-level autonomous control.
3. Experiments showed the system could perform autonomous operations like pushing buttons and twisting objects using vision and force sensors, and the shared control approach was high-
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Silicon Mentor
Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. For more info download this file or visit us at:
http://www.siliconmentor.com/
This document presents a design for an approximate multiplier that is intended for error-tolerant applications. The proposed multiplier divides the input operands into an accurate part and approximate part. The accurate part uses a standard parallel multiplier for the most significant bits, while the approximate part generates the least significant bits using approximate product generators that can produce small errors but reduce area and power consumption compared to a standard design. Experimental results on 8-bit and 16-bit versions of the proposed multiplier show reductions in area, power, and delay of around 50% compared to standard parallel multipliers, at the cost of small losses in accuracy that are acceptable for many applications. The proposed approximate multiplier is well-suited for error-tolerant domains like multimedia and
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...IRJET Journal
This document describes the design of a low power serial-parallel multiplier that uses a modified radix-4 Booth algorithm. It aims to improve performance over a standard serial-parallel Booth multiplier in terms of area, delay, and power. The proposed multiplier generates partial products conditionally, adding only non-zero Booth encodings and skipping zero operations to reduce transitions and increase throughput. It is implemented using FPGA technology to evaluate its utility for applications like digital signal processing and machine learning that require high performance multiplication.
IRJET- Approximate Multiplier and 8 Bit Dadda Multiplier Implemented through ...IRJET Journal
This document discusses the design and implementation of approximate multipliers for image processing applications. It proposes two new 4x4 approximate adders to reduce hardware complexity in a Dadda multiplier architecture. An 8x8 unsigned Dadda tree multiplier is modeled to evaluate the impact of using the proposed adders, which reduce the partial products into fewer columns while maintaining accuracy. Experimental results show the proposed multipliers achieve lower power-delay product compared to other approximate designs for similar precision in applications like JPEG image compression.
A Brief Review of Design of High Speed Low Power Area Efficient MultipliersIRJET Journal
This document reviews different types of multipliers and computing techniques to improve multiplier performance. It discusses array multipliers that use shift-and-add methods and Wallace tree multipliers that use parallel multiplication schemes. It also covers approximate computing techniques that can reduce complexity for error-tolerant applications by truncating partial products. Vedic multiplication and partitioning carry select adder algorithms are presented as well. The document concludes that Booth encoded Wallace tree multipliers have the lowest delay compared to other multipliers and approximate computing provides power savings for applications where exact results are not needed.
The document summarizes a research paper about designing a fast multiplier for FIR filters using a modified Booth encoding algorithm. It begins by introducing FIR filters and the need for high-speed multipliers in DSP systems. It then reviews existing memory-based algorithms like fixed-width multipliers and Booth multipliers. The proposed system is described as using a modified Booth encoding algorithm that reduces the number of partial products generated by half compared to other methods. It works by scanning triplet bit patterns to determine whether the partial product should be 0, +Y, -Y, +2Y, or -2Y. This allows for a high-speed parallel multiplier design with fewer computation stages.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
IRJET - Comparison of Vedic, Wallac Tree and Array MultipliersIRJET Journal
This document compares three multiplication methods: Vedic, Wallace tree, and array multipliers. It implements 8-bit versions of each multiplier in Xilinx and compares their performance in terms of delay, power utilization, and speed. The results show that the Vedic multiplier has the lowest delay and utilizes less power and area than the other multipliers, making it the fastest and most efficient technique for complex mathematical problems according to this research.
IRJET- Realization of Decimal Multiplication using Radix-16 Modified Booth En...IRJET Journal
1) The document presents a decimal multiplication algorithm using a radix-16 modified Booth encoding scheme.
2) The radix-16 modified Booth encoding reduces the number of partial products generated during multiplication, improving the speed of the multiplier.
3) The algorithm was implemented and the RTL schematic and simulation results are presented, confirming the functionality of the decimal multiplication using radix-16 modified Booth encoding.
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...IRJET Journal
1) An area efficient floating point addition unit with error detection logic is proposed using a carry select adder with a binary to excess-1 converter instead of dual ripple carry adders to reduce area.
2) Simulation results show the proposed design reduces area and power compared to general floating point addition units, with a slight increase in delay.
3) The design is implemented using VHDL and tested on a Xilinx simulator.
VEDIVISION – A FAST BCD DIVISION ALGORITHM FACILITATED BY VEDIC MATHEMATICSijcsit
Of the four elementary operations, division is the most time consuming and expensive operation in modern day processors. This paper uses the tricks based on Ancient Indian Vedic Mathematics System to achieve a generalized algorithm for BCD division in a much time efficient and optimised manner than the conventional algorithms in literature. It has also been observed that the algorithm in concern exhibits remarkable results when executed on traditional mid range processors with numbers having size up to 15 digits (50 bits). The present form of the algorithm can divide numbers having 38 digits (127 bits) which can be further enhanced by simple modifications
Multipliers play an important role in today’s digital signal processing (DSP) and various other
applications. Multiplication is the most time consuming process in various signal processing operations like
convolution, circular convolution, auto-correlation and cross-correlation. With advances in technology, many
researchers have tried and are trying to design multipliers which offer either of the following- high speed, low
power consumption, regularity of layout and hence less area or even combination of them in multiplier. However
area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try
to find out the best trade off solution among the both of them. To have features like high speed and low power
consumption multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using
various algorithm in VLSI technology.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
This document discusses the implementation of an unsigned multiplier using a modified carry select adder technique. It begins with an introduction to digital arithmetic operations like multiplication and addition. It then describes the proposed system, which uses a modified carry select adder based multiplier to reduce area over a traditional carry look ahead adder based multiplier, while maintaining similar delay times. The document provides details on the design of regular and modified square root carry select adders used in the multiplier. It discusses how replacing ripple carry adders with binary to excess-1 converters in the modified design can further reduce area and power consumption.
IRJET- Implementation of Ternary ALU using VerilogIRJET Journal
This document describes the design and implementation of a Ternary Arithmetic Logic Unit (TALU) using Verilog. Ternary logic uses three voltage levels (0, 1, Z) instead of the two levels used in binary, providing benefits like reduced gate counts, memory requirements, and faster speeds. The authors constructed truth tables and implemented simplified logic expressions using ternary multiplexers to build combinational circuits like a full adder. Their TALU design achieved 0% utilization of LUTs and slices on the FPGA, with a delay of 6.125ns which is 84.3% of the maximum delay. The document concludes that ternary logic designs require less memory and power than equivalent binary
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
IRJET- A Study on Algorithms for FFT ComputationsIRJET Journal
This document analyzes and compares several algorithms for computing the Fast Fourier Transform (FFT), including Radix-2, Radix-4, and Split Radix algorithms. It examines each algorithm in terms of the amount of computations required, computation speed, and memory requirements. The Radix-4 algorithm requires the fewest floating point additions and multiplications, while the Split Radix algorithm has the fastest computation speed, especially for larger data sizes. However, all three algorithms have similar memory requirements. In general, the choice of best algorithm depends on the specific constraints of the application, such as available memory or need for computational speed.
This document summarizes a survey paper on using intelligent techniques like expert systems, fuzzy logic, genetic algorithms, and neural networks to solve facility layout problems (FLP). FLP involves assigning facilities to locations to minimize costs associated with facility interactions. The paper discusses conventional algorithms and intelligent techniques for FLP, including optimal algorithms like branch and bound, and suboptimal algorithms like construction and improvement heuristics.
An activity diagram visually presents a series of actions or flow of control in a system similar to a flowchart or a data flow diagram. They can also describe the steps in a use case diagram.
Activity diagrams can model the dynamic aspects of a system by showing the flow of control from one activity to the next. They are essentially flowcharts that can model business workflows and operations. Activity diagrams contain activity states, action states, transitions, objects, branches, forks, joins, and swimlanes. Action states are atomic while activity states can be decomposed into further detail. Transitions show the flow of control between states. Branches specify alternate paths. Forks allow concurrent flows while joins synchronize them. Swimlanes group activities by actor or thread.
IRJET- A Review on Single Precision Floating Point Arithmetic Unit of 32 Bit ...IRJET Journal
This document reviews a single precision floating point arithmetic unit that performs operations like addition, subtraction, and multiplication on 32-bit operands according to the IEEE 754 standard. It discusses how floating point units are widely used in areas like scientific computing and signal processing. The review covers the IEEE 754 standard specification for single precision floating point numbers, which uses 1 sign bit, 8 exponent bits, and 23 fraction bits. It also summarizes several previous studies that have designed and optimized reversible floating point arithmetic units to reduce costs like quantum cost, garbage outputs, and constant inputs.
This summary provides an overview of a document describing a teleoperated robot arm and hand system using shared control:
1. The system uses shared control between autonomous control, teleoperation, and simulation modules to coordinate a robot arm, dexterous hand, sensors, and a teleoperated mechanical arm and data glove.
2. Key aspects of the shared control include sensor data sharing between various sensors, multi-agent based sharing to perform complex tasks using different sensors, and human-machine interactive sharing between high-level planning and low-level autonomous control.
3. Experiments showed the system could perform autonomous operations like pushing buttons and twisting objects using vision and force sensors, and the shared control approach was high-
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Silicon Mentor
Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. For more info download this file or visit us at:
http://www.siliconmentor.com/
This document presents a design for an approximate multiplier that is intended for error-tolerant applications. The proposed multiplier divides the input operands into an accurate part and approximate part. The accurate part uses a standard parallel multiplier for the most significant bits, while the approximate part generates the least significant bits using approximate product generators that can produce small errors but reduce area and power consumption compared to a standard design. Experimental results on 8-bit and 16-bit versions of the proposed multiplier show reductions in area, power, and delay of around 50% compared to standard parallel multipliers, at the cost of small losses in accuracy that are acceptable for many applications. The proposed approximate multiplier is well-suited for error-tolerant domains like multimedia and
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...IRJET Journal
This document describes the design of a low power serial-parallel multiplier that uses a modified radix-4 Booth algorithm. It aims to improve performance over a standard serial-parallel Booth multiplier in terms of area, delay, and power. The proposed multiplier generates partial products conditionally, adding only non-zero Booth encodings and skipping zero operations to reduce transitions and increase throughput. It is implemented using FPGA technology to evaluate its utility for applications like digital signal processing and machine learning that require high performance multiplication.
IRJET- Approximate Multiplier and 8 Bit Dadda Multiplier Implemented through ...IRJET Journal
This document discusses the design and implementation of approximate multipliers for image processing applications. It proposes two new 4x4 approximate adders to reduce hardware complexity in a Dadda multiplier architecture. An 8x8 unsigned Dadda tree multiplier is modeled to evaluate the impact of using the proposed adders, which reduce the partial products into fewer columns while maintaining accuracy. Experimental results show the proposed multipliers achieve lower power-delay product compared to other approximate designs for similar precision in applications like JPEG image compression.
A Brief Review of Design of High Speed Low Power Area Efficient MultipliersIRJET Journal
This document reviews different types of multipliers and computing techniques to improve multiplier performance. It discusses array multipliers that use shift-and-add methods and Wallace tree multipliers that use parallel multiplication schemes. It also covers approximate computing techniques that can reduce complexity for error-tolerant applications by truncating partial products. Vedic multiplication and partitioning carry select adder algorithms are presented as well. The document concludes that Booth encoded Wallace tree multipliers have the lowest delay compared to other multipliers and approximate computing provides power savings for applications where exact results are not needed.
The document summarizes a research paper about designing a fast multiplier for FIR filters using a modified Booth encoding algorithm. It begins by introducing FIR filters and the need for high-speed multipliers in DSP systems. It then reviews existing memory-based algorithms like fixed-width multipliers and Booth multipliers. The proposed system is described as using a modified Booth encoding algorithm that reduces the number of partial products generated by half compared to other methods. It works by scanning triplet bit patterns to determine whether the partial product should be 0, +Y, -Y, +2Y, or -2Y. This allows for a high-speed parallel multiplier design with fewer computation stages.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
IRJET - Comparison of Vedic, Wallac Tree and Array MultipliersIRJET Journal
This document compares three multiplication methods: Vedic, Wallace tree, and array multipliers. It implements 8-bit versions of each multiplier in Xilinx and compares their performance in terms of delay, power utilization, and speed. The results show that the Vedic multiplier has the lowest delay and utilizes less power and area than the other multipliers, making it the fastest and most efficient technique for complex mathematical problems according to this research.
IRJET- Realization of Decimal Multiplication using Radix-16 Modified Booth En...IRJET Journal
1) The document presents a decimal multiplication algorithm using a radix-16 modified Booth encoding scheme.
2) The radix-16 modified Booth encoding reduces the number of partial products generated during multiplication, improving the speed of the multiplier.
3) The algorithm was implemented and the RTL schematic and simulation results are presented, confirming the functionality of the decimal multiplication using radix-16 modified Booth encoding.
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...IRJET Journal
1) An area efficient floating point addition unit with error detection logic is proposed using a carry select adder with a binary to excess-1 converter instead of dual ripple carry adders to reduce area.
2) Simulation results show the proposed design reduces area and power compared to general floating point addition units, with a slight increase in delay.
3) The design is implemented using VHDL and tested on a Xilinx simulator.
VEDIVISION – A FAST BCD DIVISION ALGORITHM FACILITATED BY VEDIC MATHEMATICSijcsit
Of the four elementary operations, division is the most time consuming and expensive operation in modern day processors. This paper uses the tricks based on Ancient Indian Vedic Mathematics System to achieve a generalized algorithm for BCD division in a much time efficient and optimised manner than the conventional algorithms in literature. It has also been observed that the algorithm in concern exhibits remarkable results when executed on traditional mid range processors with numbers having size up to 15 digits (50 bits). The present form of the algorithm can divide numbers having 38 digits (127 bits) which can be further enhanced by simple modifications
Multipliers play an important role in today’s digital signal processing (DSP) and various other
applications. Multiplication is the most time consuming process in various signal processing operations like
convolution, circular convolution, auto-correlation and cross-correlation. With advances in technology, many
researchers have tried and are trying to design multipliers which offer either of the following- high speed, low
power consumption, regularity of layout and hence less area or even combination of them in multiplier. However
area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try
to find out the best trade off solution among the both of them. To have features like high speed and low power
consumption multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using
various algorithm in VLSI technology.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
This document discusses the implementation of an unsigned multiplier using a modified carry select adder technique. It begins with an introduction to digital arithmetic operations like multiplication and addition. It then describes the proposed system, which uses a modified carry select adder based multiplier to reduce area over a traditional carry look ahead adder based multiplier, while maintaining similar delay times. The document provides details on the design of regular and modified square root carry select adders used in the multiplier. It discusses how replacing ripple carry adders with binary to excess-1 converters in the modified design can further reduce area and power consumption.
IRJET- Implementation of Ternary ALU using VerilogIRJET Journal
This document describes the design and implementation of a Ternary Arithmetic Logic Unit (TALU) using Verilog. Ternary logic uses three voltage levels (0, 1, Z) instead of the two levels used in binary, providing benefits like reduced gate counts, memory requirements, and faster speeds. The authors constructed truth tables and implemented simplified logic expressions using ternary multiplexers to build combinational circuits like a full adder. Their TALU design achieved 0% utilization of LUTs and slices on the FPGA, with a delay of 6.125ns which is 84.3% of the maximum delay. The document concludes that ternary logic designs require less memory and power than equivalent binary
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
IRJET - Design and Implementation of Double Precision FPU for Optimised SpeedIRJET Journal
This document describes the design and implementation of a double precision floating point unit (FPU) for optimized speed. It discusses the need for high-speed arithmetic operations in applications such as digital signal processing. It presents the architecture of the proposed FPU, which includes blocks for floating point multiplication and addition. It also discusses the implementation of pipelined 64-bit floating point multiplication and addition units using techniques like carry lookahead addition and hybrid multiplication. Simulation results on a FPGA platform show that the proposed pipelined design achieves higher throughput than existing non-pipelined approaches.
A FLOATING POINT DIVISION UNIT BASED ON TAYLOR-SERIES EXPANSION ALGORITHM AND...csandit
Floating point division, even though being an infrequent operation in the traditional sense, is
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algorithm in VLSI technology. The Wallace Tree Multipliers are compared with existing multipliers in terms of
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The aim of this paper is to prove that fuzzy logic algorithm is a suitable control technique for fast processes such as electrical machines. This theory has been experimented on different kinds of electrical machines such as stepping motors, dc motors and induction machines (with 6 phases) and the experimental results show that the proposed fuzzy logic algorithm is the most suitable control technique for electrical machines since this algorithm is not time consuming and it is also robust between plant parameters variations.
This document describes the design and implementation of a 32-bit floating point adder according to the IEEE 754 standard using VHDL. It includes block diagrams of the main components: a pre-adder block to prepare the operands, an adder block to perform the addition or subtraction, and a standardization block to normalize the result. It also provides details on the steps involved, including extracting the sign, exponent and mantissa of the operands, handling special cases like zero, infinity and NaN, aligning the exponents, performing the addition or subtraction, normalizing and rounding the result, and adjusting the exponent.
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Lithological Investigation at Tombia and Opolo Using Vertical Electrical Soun...IJLT EMAS
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Public Health Implications of Locally Femented Milk (Nono) and Antibiotic Sus...IJLT EMAS
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Home textile exports are market driven, which implies that they deal with what the foreign market wants and how the home textile exporter could fulfil it, or product driven, where they deal with what the exporter has to offer and how can an appropriate strategy be applied to find the targeted buyers in the foreign market. The requisites of these are that the exporter must know the export plan, production procedure and export documentations. Exporter also must know his/her operational capacity, organizational nature and structure. An attempt is made in this project to understand and examine the nature and structure of the organization of the S3P exports.
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Design, Develop and Implement an Efficient Polynomial Divider
1. International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume VI, Issue III, March 2017 | ISSN 2278-2540
www.ijltemas.in Page 78
Design, Develop and Implement an Efficient
Polynomial Divider
Purbayan Deb1
, Anindya Sen2
1,2
Department of Electronics and Communication Engineering (VLSI), Heritage Institute of Technology, Kolkata, West Bengal
Abstract- Polynomial Division is a most common numerical
operation experienced in many filters and similar circuits next to
multiplication, addition and subtraction. Due to frequent use of
such components in mobile and other communication
applications, a fast polynomial division would improve overall
speed for many such applications. This project is to design,
develop and implement an efficient polynomial divider
algorithm, along with the circuit. Next its output performance
result is verified using Verilog simulation. A literature survey on
the normal division algorithms currently used by ALU’s to
perform division for large numbers, yielded Booth’s algorithm,
Restoring and Non-restoring algorithm. Verilog simulation of
these algorithms were used to derive efficiency in terms of the
timing characteristics, required chip area and power dissipation.
Initially, performance analysis of the existing algorithms was
done based on the simulated outputs. Later similar analysis with
the updated polynomial divider circuit is performed.
Keywords- Division, Polynomial, Booth’s algorithm, Restoring
algorithm, Non-restoring algorithm, Verilog.
I. INTRODUCTIONS
hroughout the years, mathematicians and engineers have
developed many algorithms to divide numbers. The
ALU which is primarily used for division has gone through
many changes in its design. One of these changes was in its
division algorithms. In a typical computer, an ALU is called
upon to do hundreds of division operations per second.
Divider circuits are used for various purposes like error
correcting codes. So to perform at its peak, the ALU„s
algorithms need to be as efficient as possible. However, some
of these algorithms work better when computing the result of
the operation by hand than using a computer and so these
algorithms are not efficient in every case [1].
The traditional pen and paper algorithm, when converted
to computer algorithm, resulted in the Booth‟s algorithm,
Restoring Division algorithm [5]. Smaller improvements
have been made to the restoring division algorithm, which
resulted in Non-Restoring Division algorithm and many high
radix algorithms, later combinational array divider circuits are
also implemented for the division purpose [6]. In many cases,
division is performed by taking the inverse of the divider and
then multiplying the two numbers.
Division methods are divided in five classes that include
iteration, digit recurrence, very high radix, table look up and
variable latency. Each of these classes of division is
implemented differently in hardware (using multiplication,
subtraction, table look up, etc.).
Some algorithms use multiple classes rather than just one
in particular. This report focuses on subtraction-based
methods, such as restoring and non-restoring division
algorithms, to obtain the final answer in a division
computation. Digit recurrence algorithm is another division
algorithm and they produce one digit of the final quotient per
iteration.SRT (Sweeney Robertson and Tocher) division
algorithm is very commonly use for digit recurrence purpose
[12].
Use of Verilog code, which is a Hardware Descriptive
language (HDL) will be done for the simulation purpose of
the project.
II. MOTIVATION
Despite the recent improvement in division algorithms,
division remains a complex operation and is therefore not
implemented in many low cost or low power ALUs. Division
can add more complexity to the computations since it can
have invalid inputs such as division by zero and can have
multiple machine cycles used in it. The time taken for its
operation is also high and the circuits get more complex if
more precision is needed and so it is avoided by most ALU‟s
[1].
A division operation is an indispensible tool for a high
performance system. A common perception of division is that
it is an infrequent operation whose implementation need not
receive high priority. However, it has been shown that
ignoring its implementation can result in significant system
performance degradation for many applications. Refining
the polynomial division algorithm helps in improving the
precision of the result and reduces the delay to obtain output.
So implementation of a proper divider circuit is very
important in an ALU.
III. OBJECTIVE
The main objective of the project work will be to focus
on using the most optimal division algorithm and to design an
T
2. International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume VI, Issue III, March 2017 | ISSN 2278-2540
www.ijltemas.in Page 79
efficient polynomial divider circuit & simulate its
performance.
To find the most optimal algorithm timing characteristics
and area report generated by the Xilinx tool for various
division algorithms will be compared and analyzed.
IV. TOOL USED
For this project Verilog, HDL is used under Xilinx ISE
Design Suite 13.4 platform.
V. LITERATURE SURVEY
A. Booth’s Algorithm
Fig.1 Flowchart of booth‟s algorithm for division
Division is done by doing shifts and subtractions.
Dividing a number of 2n bits by a number of n bits results in a
quotient of up to 2n bits and a remainder of up to n bits.
At start, the n bits divisor is shifted to the left, while n
0‟s are added to its right. This way the dividend and the
divisor are 2n bits long.
At each step (repeating the following n+1 time), subtract
the divisor from the dividend. If the result is non-negative,
Shift the quotient left and place 1 in the new place.
Else, Shift the quotient left and place 0.
Restore the dividend by adding the divisor to it. Shift the
divisor to the right [2].
At start, the dividend occupies the right half of the
remainder register. The left half of the reminder register is full
with zeros. Shift reminder left 1 position.
At each step, the control subtracts the divisor from the
left half of the remainder register, putting there the result. If
the remainder is negative, it restores it. Then, instead of
shifting the divisor to the right, it shifts the remainder to the
left and inserts 0 or 1, according to the sign of the remainder.
0 if the sign bit is 1 and 1 if the sign bit is 0.
At the end, the remainder register contains the quotient in
its right half and the remainder in its left half [3].
The following example (7/2) will illustrate the division
process of booth‟s algorithm clearly.
TABLE I
Shows Division of 0111 / 0010 by Booth‟s Algorithm
Itera-
tion
Step Quotient Divisor
Remai
nder
0 Initial values 0000
0010
0000
0000
0111
1
1: Rem=Rem-Div 0000
0010
0000
1110
0111
2b: Rem<0=>+Div, sll
Q,Q0=0
0000
0010
0000
0000
0111
3: Shift Div right 0000
0001
0000
0000
0111
2
1: Rem=Rem-Div 0000
0001
0000
1111
0111
2b: Rem<0=>+Div, sll
Q, Q0=0
0000
0001
0000
0000
0111
3: Shift Div right 0000
0000
1000
0000
0111
3
1: Rem=Rem-Div 0000
0000
1000
1111
1111
2b: Rem<0=>+Div, sll
Q, Q0=0
0000
0000
1000
0000
0111
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3: Shift Div right 0000
0000
0100
0000
0111
4
1: Rem=Rem-Div 0000
0000
0100
0000
0011
2a: Rem≥0=> sll Q,
Q0=1
0001
0000
0100
0000
0011
3: Shift Div right 0001
0000
0010
0000
0011
5
1: Rem=Rem-Div 0001
0000
0010
0000
0001
2a: Rem≥0=> sll Q,
Q0=1
0011
0000
0010
0000
0001
3: Shift Div right 0011
0000
0001
0000
0001
B. Restoring Division Algorithm
Digital Recurrence algorithms use subtractive methods to
calculate quotients one digit per iteration. Restoring division
algorithm is based on the digital recurrence algorithm [1].
Fig.2 Flowchart for restoring division algorithm
Restoring division follows the same method as the pen
and paper long division algorithm. In the long division
algorithm, the divisor is compared to the left digits of the
dividend. If the divisor is bigger than the dividend numbers
being compared, then a 0 in appended to the quotient and
divisor is shifted to the right to compare with bigger dividend
digits. If the divisor is smaller than the dividend, then the
divisor being compared is subtracted from the dividend and
the result is stored as remainder, while the number of times
the divisor can go into the dividend is appended to the
quotient [4].
During the next loop, the dividend and the remainder
need to be appended together to form the new dividend. This
process is repeated until the dividend cannot be divided
further by the divisor. The same process is applied in the
Restoring division algorithm.
To decide whether the divisor is bigger than the dividend
bits it is being compared to, it subtracts the divisor from the
dividend bits and stores the result in remainder field. If the
divisor is bigger than the dividend bits, then the result will be
negative.
If the result is negative, then the remainder is wrong and
it must be “restored” to the previous value and a 0 must be
appended to the quotient before the divisor is shifted to the
right (or dividend shifted to the left) and subtraction is tried
again.
If the result is positive, then divisor is bigger than the
dividend bits being compared to and the result is valid.
Therefore, a 1 is appended to the quotient.
Below the algorithm for restoring division method is
explained with an example by dividing 0011 1101 (61), by
01010 (10) and how it works.
Following the Restoring division algorithm discussed
above, the first step is to shift the quotient 1 bit to the left.
Second, subtract the divisor from the left half of the
dividend and update the left half of the quotient with the
answer. This new dividend value now has the remainder and
rest of the quotient appended together.
To avoid destroying the initial dividend value, the
dividend can be copied into the remainder register and use
remainder register as the dividend value.
If the new dividend is less than zero, then shift the
quotient left 1 bit and restore the previous value of the
dividend. Otherwise, shift the quotient left 1 bit and set the
least significant bit to 1. Repeat for procedure 4 times to
evaluate all bits of the dividend [5].
At the end of the procedure, the quotient value will be the
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remainder.
Dividend z: 0011 1101 (61),
Divisor d: 01010 (10)
Quotient : 0110 (6),
Remainder : 0001 (1)
TABLE II
Division of 00111101 / 01010 by Restoring Method
C. Non-Restoring Division Algorithm
The non-restoring divide does not “restore” the
remainder to the correct value but leaves it incorrect until the
next cycle [1]. In the restoring divide algorithm, if we had
restored the partial remainder to its correct value, we would
proceed with the next shift and trial subtraction getting the
result. Instead, because we used the incorrect partial
remainder, a shift and trial subtraction would yields result
which is not the intended. However, an addition would do the
trick.
The non-restoring algorithm can result in a negative
remainder, which is incorrect. Therefore, a correction step is
needed to obtain the correct remainder. The algorithm to
perform non-restoring division is as follows:
Non-restoring divide algorithm [6]:
i. Shift remainder left 1 bit.
ii. If remainder is negative, add divisor to the left half
of
iii. the remainder. Shift quotient left 1 bit.
iv. If remainder is positive, subtract divisor from the left
v. half of the remainder. Shift quotient left 1 bit and
add 1.
vi. Repeat for number of bits in divisor.
vii. Correction step: If remainder is negative, add divisor
to the remainder to obtain the correct value.
Fig.3 Flowchart for non-restoring division algorithm
Here, the dividend is not restored after each unsuccessful
subtraction operation as was in restoring algorithm.
Instead, the following logic is followed:
If the current remainder is positive,
Then Q0 = 1.
Next operation will be shift and subtract
Else (remainder negative),
Then Q0 = 0.
Next operation will be shift and add.
Example: 10 / 4
Quotient = 2, Remainder = 2, A = 0
Q = Dividend = 10 = 1010
B = Divisor = 4 =0100 ,
Iteration P Q
1 Shift z left once: 0111101
Subtract d from left half of z: 11111101
Result is negative. Restore to previous
value: 0111101
0
2 Shift z left once: 111101
Subtracting d from left half of z: 010101
Result is positive. New z is 010101
01
3 Shift z left once: 1010 1
Subtracting d from left half of z: 00001
Result is positive. New z is 00001
011
4 Shift z left once: 0001
Subtracting d from left half of z: 10111
Result is negative: Restore to previous
value: 0001
0110
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- B means 2‟sComplement of B = 4
B =00100
11 011 1‟s Complement of B
+ 1 addition of 1 to 1‟s Complement of B
11100 2‟s Complement of B
If Q (Divisor) register contains 4 bits then Contents of A
register is 4+1=5 bits
TABLE III
Division of 1010 / 0100 by Non-Restoring Method
D. LFSR (Linear Feedback Shift Registers)
Linear Feedback Shift Registers (LFSR) can be used for
polynomial division, among its other uses.
Two example LFSRs are shown in Fig4 & Fig5. Note that
both these structures use D-type flip-flops and linear logic
elements (EOR gates) to realize LFSRs [8]. The basic
difference in these two structures being the circuit of Fig4
uses linear elements interspersed between the flip-flops
whereas the circuit of Fig5 has no linear element appearing
between the flip-flops instead the linear elements appear only
in the feedback path. It is for this reason the realization of
Fig4 is called internal-EOR LFSR and the realization of Fig5
is called external EOR LFSR. A equivalence exists between
the two structures in the sense that knowing the properties of
the first structure one can deduce the properties of the second
structure.
The circuit in Fig4 is better for its high-speed operation
since they don't have multiple adder combination propagation
delays [9].
Fig.4 Internal EOR type LFSR
Fig.5 External EOR type LFSR
Polynomial arithmetic can be performed using this
LFSR circuit. The LFSR here does the shifting operation at
each clock cycle and keeps on generating new patterns based
on the input values. One thing to be noted here during
polynomial division is that all these polynomials are not
usually written with minus signs, but they could be, therefore
a coefficient of –1 is equivalent to coefficient of 1 and
polynomials with co-efficient other than 1 cannot be used as
in digital domain we have only 0 & 1[10].
Fig.6 A basic polynomial division register
VI. METHODOLOGY
A. Preliminary Work
In this project firstly comparison of the restoring and non
Represents EOR gate
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restoring algorithms for division are done and the results are
obtained.
The comparison is on the basis of area analysis, timing,
delay and power consumed. The algorithms are implemented
using Verilog code and done the comparison.
I have done the coding in Xilinx ISE Design Suite 13.4
tool.
B. Proposed Implementation in Polynomial Divider Circuit
Steps to be followed for implementation of polynomial
division-
i. Firstly the circuit is built on basis of the denominator
given.
ii. The input is given serially in the circuit.
iii. The output of each stage is calculated at each clock
cycle.
iv. The process continues until all the bits of input are
given.
v. The quotient is calculated from the outputs of the
final register.
vi. Finally, the remainder is calculated from the output
of all the registers in the final clock cycle.
Below two examples are given to explain the process of
polynomial division-
i) (X3
+X2
+1)/(X2
+1)
Fig.7 Circuit for (X3
+X2
+1)/(X2
+1)
Fig.8 Division using long division method
TABLE IV
LFSR Stages Corresponding to the Input Applied
INPUT D0 D1 OUTPUT STREAM
1 0 0 0
1 1 0 00
0 1 1 001
1 1 1 0011
0 1
Here the final output stream is 0011.
So the quotient is 0*X3
+ 0*X2
+ 1*X1
+ 1*X0
= X+1
The value of D0 and D1 in final cycle is 0 & 1 respectively.
So, remainder is 0*X0
+ 1*X1
=X
Here any numerator can be applied and the output result will
be obtained using the same denominator.
ii) (X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1)
Fig.9 Circuit for (X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1)
TABLE V
LFSR Stages Corresponding to the Input Applied
INPUT D0 D1 D2 D3 D4 OUTPUT
STREAM
1 0 0 0 0 0 0
1 1 0 0 0 0 00
1 1 1 0 0 0 000
1 1 1 1 0 0 0000
0 1 1 1 1 0 00000
1 0 1 1 1 1 000001
0 0 0 0 1 0 000010
1 0 0 0 0 1 0000101
0 0 1 0 1
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Here the final output stream is 0000101.
So the quotient is
0*X6
+ 0*X5
+ 0*X4
+ 0*X3
+ 1*X2
+ 0*X1
+ 1*X0
=X2
+1
The value of D0,D1,D2,D3,D4 in final cycle is 0,0,1,0,1
respectively.
So, remainder is
0*X0
+ 0*X1
+ 1*X2
+ 0*X3
+ 1*X4
= X2
+X4
.
Fig.10 Division using long division method
These are simulated using the Xilinx tool and the results
are compared.
The max power of the denominator can be 9312 as this is
the number of Flip Flops supported by the Xilinx tool.
This division operation can also be performed using
multiplication of LFSR. But that will be a much more time
consuming process.
Example- X2
/X= X
This will be the process if it is done normally using
polynomial division method.
But if multiplication is used it will be, X2
* X-1
= X
So the number of operations needed to be performed in
this method will be more and hence more time will be
consumed [11].
VII. RESULT
Fig.11 Division of 13 by 5 using restoring division
Fig.12 Area analysis for restoring division
Fig.13 Timing analysis for restoring division
Fig.14 Power analysis for restoring division
Fig 11, Fig 12, Fig 13, Fig 14 represents the waveform of
output of the division, area analysis, timing analysis and
power analysis respectively.
Fig.15 Division of 13 by 5 using non-restoring division
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Fig.16 Area analysis for non-restoring division
Fig.17 Timing analysis for non-restoring division
Fig.18 Power analysis for non-restoring division
Fig 15, Fig 16, Fig 17, Fig 18 represents the waveform of
output of the division, area analysis, timing analysis and
power analysis respectively.
Fig.19 (X3
+X2
+1)/(X2
+1) using LFSR
Fig.20 Area analysis for polynomial division of (X3
+X2
+1)/(X2
+1)
Fig.21 Timing analysis for polynomial division of (X3
+X2
+1)/(X2
+1)
Fig.22 Power analysis for polynomial division of (X3
+X2
+1)/(X2
+1)
Fig 19, Fig 20, Fig 21, Fig 22 represents the waveform of
output of the division, area analysis, timing analysis and
power analysis respectively.
Fig23 (X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1) using LFSR
Fig.24 Area analysis for polynomial division of
(X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1)
Fig.25 Timing analysis for polynomial division of
(X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1)
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Fig.26 Power analysis for polynomial division of
(X7
+X6
+X5
+X4
+X2
+1)/(X5
+X4
+X2
+1)
Fig 23, Fig 24, Fig 25, Fig 26 represents the waveform of
output of the division, area analysis, timing analysis and
power analysis respectively.
TABLE VI
Comparison of Timing, Area and Power of Restoring, Non- Restoring and Polynomial Division
Restoring Division Non-Restoring Division Polynomial Division
1101 / 101 1101 / 101 (X3
+X2
+1)/(X2
+1)
(X7
+X6
+X5
+X4
+X2
+1)/
(X5
+X4
+X2
+1)
Timing
Analysis
Maximum input arrival time
after clock-18.650ns
Maximum output required
time after clock-4.283ns
Maximum input arrival
time after clock-14.849ns
Maximum output required
time after clock-4.283ns
Maximum input arrival
time after clock-3.700ns
Maximum output
required time after clock-
4.310ns
Maximum input arrival
time after clock-3.886ns
Maximum output required
time after clock-4.450ns
Area
Analysis
No. of Slice-18
No. of 4 input LUT- 30
No. of Slice-18
No. of 4 input LUT- 33
No. of Slice-1 No. of Slice-3
No. of Slice Flip-Flop-2 No. of Slice Flip-Flop-5
No. of 4 input LUT-2 No. of 4 input LUT-4
Power Analysis Total power- 0.083W Total power- 0.083W Total power- 0.081W Total power- 0.081W
VIII. CONCLUSION
In this paper analysis of various division algorithms are
done. Their timing, area & power comparison are obtained.
From the analysis I have seen that though the number of
LUT utilization in non-restoring algorithm is more but the
timing performance of the non-restoring algorithm is much
better. So from these to algorithm analysis it can be concluded
that the non restoring algorithm is by far better than restoring
algorithm.
Later in the next part a polynomial divider is
implemented using LFSR and the simulation is done using
Verilog. The results obtained are then compared and we see
that the delay is much less in this method. We also see that
more the maximum power of denominator more is the delay.
The power consumed by the polynomial divider circuit is also
bit less. Overall it can be said that by implementing the
polynomial division the delay and area can be minimized a
lot.
As the complexity in designing a polynomial divider
circuit is high, need for more efficient design is very high in
market. Thus seeing the growing needs my project can be
highly beneficial.
IX. FUTURE WORK TO BE DONE
Up to this point research on divider circuits like Booth‟s
algorithm, Restoring algorithm & Non-restoring algorithm are
done and a polynomial divider using LFSR‟s serially is
implemented.
So, the next work will be to implement the LFSRs in
parallel to reduce the time required for execution of the
division method.
ACKNOWLEDGEMENT
The road of knowledge is long and full of obstacles,
but going over those obstacles is what ultimately enlightens
the individual and strengthens ones spirit. I have been very
fortunate to walk through the road of knowledge, not alone,
but accompanied by the brightest and warm hearted individual
I have ever met.
I take this opportunity to thank my project guide Sri
Anindya Sen (Phd) for guiding me in this paper.
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He has been a great source of motivation for me,
which inspired me a lot to take up the project and deliver it in
a nicest possible way.
Finally, I would also like to thank all the faculty
members and staff of Electronics and Communication
Engineering Department for their time to time support and co-
operation, which has helped me a lot.
PURBAYAN DEB
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[5]. Computer Principles And Design In Verilog HDL Yamin Li Hosei
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[7]. Linear Feedback Shift Registers Theory and. Applications. Kewal
K. Saluja. Department of Electrical and Computer Engineering.
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