This paper shows an effective design of combinational circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage outputs in implementing each combinational circuit.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Combinational logic circuits by Tahir YasinTAHIR YASIN
This research paper defines the digital electronics and its one type combinational circuits.
Combinational circuits is based on the Boolean expression so also gives the brief introduction about Boolean algebra and also describes the different forms of circuits and also describes the minimization techniques of combinational logic circuits and some general application of combinational circuit
Follow me on twitter @Tahiryasin971
Email: tahiryasin758@gmail.com
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Combinational logic circuits by Tahir YasinTAHIR YASIN
This research paper defines the digital electronics and its one type combinational circuits.
Combinational circuits is based on the Boolean expression so also gives the brief introduction about Boolean algebra and also describes the different forms of circuits and also describes the minimization techniques of combinational logic circuits and some general application of combinational circuit
Follow me on twitter @Tahiryasin971
Email: tahiryasin758@gmail.com
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the MUX , demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be bypassed to one of its many output data lines.
Demultiplexers are mainly used in Boolean function generators and decoder circuits. Different input/output configuration demultiplexers are available in the form of single integrated circuits (ICs).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
Design and Synthesis of Multiplexer based Universal Shift Register using Reve...IOSRJVSP
Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.Design and Synthesis of Multiplexer based Universal Shift
Register using Reversible Logic
The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the MUX , demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be bypassed to one of its many output data lines.
Demultiplexers are mainly used in Boolean function generators and decoder circuits. Different input/output configuration demultiplexers are available in the form of single integrated circuits (ICs).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Design of Digital Adder Using Reversible LogicIJERA Editor
Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design,
Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them
another main prominent application of reversible logic is Quantum computers where the quantum devices are
essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible
logic components. This makes the reversible logic as a one of the most promising research areas in the past few
decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents
the implementation of Ripple Carry Adder (RCA) circuits using reversible logic gates are discussed.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
Implementation of the Binary Multiplier on CPLD Using Reversible Logic GatesIOSRJECE
In this paper, we present the Implementation of the Binary Multiplier on CPLD using Reversible logic gates. These circuits have been simulated on Active HDL and synthesised on Xilinx web pack 5.1 software
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Key Words:Quantum Computing, Reversible Logic,
Garbage outputs, Constant Inputs.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Low Power Reversible Parallel Binary Adder/SubtractorVLSICS Design
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Similar to Design of Multiplexers, Decoder and a Full Subtractor using Reversible Gates (20)
Lithological Investigation at Tombia and Opolo Using Vertical Electrical Soun...IJLT EMAS
Vertical electrical soundings (VES) was carried out in Opolo and Tombia all in Yenagoa local government area, Bayelsa state, Nigeria to understand the resistivity distribution of its subsurface which serves as a tool in investigating subsurface lithology. All VES sounding were stacked together to generate 1D pseudo tomogram and was subsequently interpreted. The interpreted VES curve results shows that Opolo consists of three layers within the depth of investigation. Sandy clay with mixture of silt make up the first layer (Top layer) with resistance value ranging from 24-63Ωm. The second layer is made up of thick clay with very low resistivity values ranging from 3-19Ωm. The third layer is sandyclay with its resistance value ranging from 26-727Ωm.Tombia also reveals that the area is in three layers within the depth of investigation. Sandy clay with a mixture of fine sand made up the first layer (Top soil) with its resistance values ranging from 40-1194Ωm. The second layer is made up of fine sand with resistivity value ranging from 475-5285Ωm. The third layer is made up of sandy clay/sand with its resistance value ranging from 24-28943Ωm.The results of the 1D pseudo tomogram also reveals that Tombia and Opolo consists of three layers within the depth of investigation and pseudo tomograms serves as a basis tool for interpreting lithology and identifying lithological boundaries for the subsurface
Public Health Implications of Locally Femented Milk (Nono) and Antibiotic Sus...IJLT EMAS
The study is to determine the PH and moisture content
of Nono sold in Port Harcourt , the prevalence of Pseudomonas
aeruginosa in Fura da nono and finally the antibiotic resistance
pattern of Pseudomonas aeruginosa isolated from the fermented
products. nono samples were purchased from Borikiri in
portharcourt township. A total of 20 samples were assessed to
determine their microbiological quality and to conduct antibiotic
susceptibility test. Moisture content and pH of the samples were
also assessed. Enumeration of the total viable bacterial count
(TVBC), Total coliform count (TCC) and Total Pseudomonal
count (TPC) were also assessed to determine the sanitary quality
of the product. The PH ranges between 2.99 to 3.89 while the
moisture content ranges between 80% to 88%. The result
obtained from the microbial culture indicated that a wide array
of microorganism were present in Fura da nono including species
of Bacilu, klebsiella, Pseudomonas Staphylococcus aureus,
Streptococcus, Lactobacillus and Escherichia coli.. The highest
TVBC, TCC and TPC were 9.8x103
cfu/ml, 10x103
cfu/ml and
9.7x103
cfu/ml respectively. Antibiotic susceptibility was
conducted using 12 broad spectrum antibiotics and compared
against a standard provided by the Clinical laboratory standard
institute (CLSI). Gentamycin, Ofloxacin and Levofloxacin
recorded 100% resistance , while Cotrimoxazole, Ciprofloxacin,
Vancomycin, Nitrofurantoin, Norfloxacin and Azithromycin
recorded 100% susceptibility as indicated by the complete clear
zone of inhibition.It was discovered that the absence of
regulatory agencies like National Agency for Food Drug
Administration and Control (NAFDAC) in the regulation of the
quality of the product was the cause of the high contamination,
since there were no quality control measures in its production
line .It was recommended that NAFDAC should provide a
standard operating procedure for local food producers and
should include them in their scope for regulation.
Bioremediation Potentials of Hydrocarbonoclastic Bacteria Indigenous in the O...IJLT EMAS
Hydrocarbon pollution Remediation by Enhanced
Natural Attenuation method was adopted to remediate the
hydrocarbon impacted site in Ogoniland Rivers State, Nigeria .
The research lasted for 6 months. Samples were collected at
monthly intervals . samples were collected intermittently
between Feb 2019 to July 2019 . Mineral salt medium containing
crude oil was used as a sole source of carbon and energy for the
isolation of hydrocarbonoclastic bacteria. Samples were
collected from the four (4) local government that made up
Ogoniland and they includes Khana(k), Gokana (G),Tai (T),
Eleme (E) and transported immediately to the laboratory for
analysis. The microbial and physicochemical properties of the
soil samples varied with the different local government areas.
Seven bacteria genera were isolated from the samples from the
four locations, viz, Pseudomonas, Lactobacter, Micrococcus,
Arthrobacter, Bacillus, Brevibacterium and Mycobacterium
were isolated and identified. the seven isolate were indigenous in
the study area. Nutrient were added to identified plots of
hydrocarbon pollution polluted site within the four local
government and they were able degrade hydrocarbon within a
short of period of time. Reassessment of physicochemical
parameter impacted site was used to judge the bioremediation
potentials of microorganism
Comparison of Concurrent Mobile OS CharacteristicsIJLT EMAS
It is challenging for the mobile industry to supply the best features of the devices with its increasing customer requirements. Among the progress of technologies, the mobile industry is the fastest growing; as it keeps pace with rapidly changing market demands. This paper compares between the currently available mobile devices based on its user interface, security, memory utilization, processor, and device architecture. The mobile products launched from 2015-19 are used for comparison. Current results after comparison with earlier study found that many mobile devices and features became obsolete in a short time span supporting the aggressive growth of mobile industry.
Design of Complex Adders and Parity Generators Using Reversible GatesIJLT EMAS
This paper shows efficient design of an odd and even parity generator, a 4-bit ripple carry adder, and a 2-bit carry look ahead adder using reversible gates. Number of reversible gates used, garbage output, and percentage usage of outputs in implementing each combinational circuit is derived. The CLA used 10 reversible gates with 14 garbage outputs, with 50% percentage performance usage.
Multistage Classification of Alzheimer’s DiseaseIJLT EMAS
Alzheimer’s disease is a type of dementia that destroys
memory and other mental functions. During the progression of
the disease certain proteins called plaques and tangles get
deposited in hippocampus which is located in the temporal lobe
of brain. The disease is not a normal part of aging and gets
worsen over time. Medical imaging techniques like Magnetic
Resonance Imaging (MRI), Computed Tomography (CT) and
Positron Emission Tomography (PET) play significant role in the
disease diagnosis. In this paper, we propose a method for
classifying MRI into Normal Control (NC), Mild Cognitive
Impairment (MCI) and Alzheimer’s Disease(AD). An overall
outline of the methodology includes textural feature extraction,
feature reduction process and classification of the images into
various stages. Classification has been performed with three
classifiers namely Support Vector Machine (SVM), Artificial
Neural Network (ANN) and k-Nearest Neighbours (k-NN)
Design and Analysis of Disc Brake for Low Brake SquealIJLT EMAS
Vibration induced due to friction in disc brake is a
theme of major interest and related to the automotive industry.
Squeal noise generated during braking action is an indication of
a complicated dynamic problem which automobile industries
have faced for decades. For the current study, disc brake of 150
cc is considered. Vibration and sound level for different speed
are measured. Finite element and experimentation for modal
analysis of different element of disc brake and assembly are
carried out. In order to check that precision of the finite element
with those of experimentation, two stages are used both
component level and assembly level. Mesh sensitivity of the disc
brake component is considered. FE updating is utilized to reduce
the relative errors between the two measurements by tuning the
material. Different viscoelastic materials are selected and
constrained layer damping is designed. Constrained layer
damping applied on the back side of friction pads and compared
vibration and sound level of disc brake assembly without
constrained layer damping with disc brake assembly having
constrained layer. It was observed that there were reduction in
vibration and sound level. Nitrile rubber is most effective
material for constrained layer damping.
The aim of this article is to device strategies for
establishing and managing tomato processing industry, which
aims to enhance the taste experiences on different tomato
products for the people. Management needed for a successful
business is analyzed in each and every aspect. The five important
steps in management- planning, organizing, staffing, leading and
controlling are applied in management of the industry. Planning-
In the planning process, activities required to achieve desired
goals are thought about. This process involves the creation and
maintenance of a plan, those include psychological aspects that
require conceptual skills. Organizing- Organizing is a systematic
processing in order to attain objectives of structuring,
integrating, co-ordinating task, and activities. Staffing- Staffing is
the process of acquiring, deploying, and retaining a workforce of
sufficient quantity and quality to create positive impacts on the
organization’s effectiveness. Leading- Communicating,
motivating, inspiring and encouraging employees are key aspects
of process of leading, task of which is towards a higher level of
productivity of organization. Controlling- Controlling measures
the deviation of actual performance from the standard
performance, discovers the causes of such deviations and helps in
taking corrective actions.
This paper deals with the functioning of a Propylene
Recovery Unit (PRU) in a chemical industry and the various
Managerial and Human Resource considerations that need to be
accounted for, in this process. This report discusses various
aspects that are to be considered, before initializing the setup of
PRU, ranging from a Management perspective. Mission and
objective was decided and subsequently the managerial model
was developed. Propylene is an indispensible raw material that
has a variety of end use. A detailed analysis pertaining to
propylene demand in the market along with major sources has
been incorporated in this paper. Emphasis has been placed on
the type of departmentation required. Managerial aspects of
various functions ranging from warehousing to quality control
have also been taken into consideration. Delegations of functional
departments have been defined to prevent redundancy of duties
and major managerial functions of Planning, Organizing,
Staffing, Leading and Controlling has also been discussed.
Internal and External factors that affect the company have been
analyzed through SWOT Analysis and MBO strategies are also
broadly classified. Finally, Total Quality Management and
strategies for adoption of Lean Manufacturing as also touched
upon briefly.
This business model is intended to provide an online
platform connecting the general public customers with the
producers of groceries and food products such as fruits,
vegetables, meat and dairy products. The producers are selected
based on their production methods and their quality. The model
obtains the demand from the customers and the supply is found
from the producers. The prices of the products are fixed
according to the supply and demand. The customers' orders can
be classified into two different categories: 1. Bulk orders and 2.
Recipe based. The orders are obtained in a bulk quantity or for a
certain period of time and the products are delivered
periodically as per the customer's need. This model eliminates
the requirements of conventional storage units and also controls
the quality of the products using scientific devices. This model
reduces the wastage of resources as it enables the customer to
estimate their requirements using the help of recipe based
ordering system and also keeps the price constant for the bulk
orders.
Home textile exports are market driven, which implies that they deal with what the foreign market wants and how the home textile exporter could fulfil it, or product driven, where they deal with what the exporter has to offer and how can an appropriate strategy be applied to find the targeted buyers in the foreign market. The requisites of these are that the exporter must know the export plan, production procedure and export documentations. Exporter also must know his/her operational capacity, organizational nature and structure. An attempt is made in this project to understand and examine the nature and structure of the organization of the S3P exports.
Almost 80% of the population are coffee lovers.
Kaffinite sunshine café is guaranteed to become the daily
necessity for all the coffee addicts. A place with good ambience
where people can escape from their daily stress and cherish with
a morning cup of coffee. Our café offers home style delicious
breakfast and snacks. We focus on finding the most aromatic
and exotic coffee beans. We have our branches in many cities of
Tamil Nadu. We have a romantic ambience which attracts youth.
Our café has spectacular interior designs with stupendous taste
of coffee. We have attached our menu which contains multicuisines
at attractive prices. In this paper, we have done SWOT
analysis of our café to know our strengths and weaknesses. We
have also analyzed our opportunities and threats from the
external environment
Management of a Paper Manufacturing IndustryIJLT EMAS
This project focuses on how a paper manufacturing industry looks like and how it operates. For better understanding purpose, we have taken a hypothetical situation here. We have discussed on various factors that are to be considered before constructing a plant. For example, what kind of proprietorship is suitable for this case? We have developed a SWOT Analysis for the plant, thinking about the pros and cons. This project can be a guide for a person who is willing to start up a new manufacturing plant. This report can be used to streamline your approach to planning by outlining the responsibilities of plant managers and external factors, as well as identifying appropriate resources to assist you with the construction of plant.
Application of Big Data Systems to Airline ManagementIJLT EMAS
The business world is in the midst of the next
revolution following the IT revolution – the Big Data revolution.
The sheer volume of data produced is a major reason for the big
data revolution. Aviation and aerospace are typical areas that
can apply big data systems due to the scale of data produced, not
only by the plane sensors and passengers, but also by the
prospective passengers. Data that need to be considered include,
but are not limited to, aircraft sensor data, passenger data,
weather data, aircraft maintenance data and air traffic data.
This paper aims at identifying areas in aviation where big data
systems can be utilized to enhance operational performances
improve customer relations and thereby aiding the ultimate goal
of increased profits at reduced costs. An improved management
model built on a strong big data infrastructure will reduce
operation costs, improve safety, bring down the cost and time
spent on maintenance and drastically improve customer
relations.
Impact of Organisational behaviour and HR Practices on Employee Retention in ...IJLT EMAS
I. INTRODUCTION
Roads are constituted as the most significant component of
India‟s Logistics Industry, accounting for 60 percent of
the total freight movement in the country. A majority of
players in this industry are small entrepreneurs running their
family businesses. As a result, Man Power Development
Investments that pay off in the longer term, have been
minimised respectively. Moreover, these businesses are
typically controlled severely by the proprietor and his / her
family and consequently, making it unattractive for the
professionals. Poor working conditions, Low pay scales
relative to alternate careers, poor or non-existent Manpower
Policies and prevalence of unscrupulous practices have added
to the segment's woes for seeking employment. Thus, it could
be rightly stated that the Transportation, Logistics,
Warehousing and Packaging Sector is considered an
unattractive career option and fails to attract and retain skilled
manpower. Many Organizations have failed to recognize that
Human Resources play an important role in gaining an
immense advantage in today‟s highly competitive Global
Business Environment. While all aspects of managing Human
Resources is important, Employee Retention continues to be
an essential part of Human Resource Management activity
that help the Organizations to achieve their goals and
objectives.
Sustainable Methods used to reduce the Energy Consumption by Various Faciliti...IJLT EMAS
The purpose of this article is to identify the energy
challenges faced by airports especially with regards to the energy
consumed by the terminal building and suggest suitable energy
conservation techniques based on what has already been
implemented in few airports around the world.
We have identified the various facilities and systems which are
responsible for a major share of the consumption of energy by
airport terminals and we have suggested measures to effectively
overcome these problems.
OVERVIEW OF THE COMPANY
Cake Walk sweets and savories
Cake Walk is India‟s No. 1 confectionery and cake
manufacturer with its products exported to over 20 countries
around the world. They are dedicated to the art of producing
innovative and delicious products for sweet lovers of all ages.
Cake Walk‟s products offer tantalizing experiences that sparks
the imagination in people who eat their candy. Of course, this
has been Cake Walk‟s goal since their inception in 1947.
Today, Cake Walk Candy continues to make some of the best
candy in India. They also are a responsible business venture
and contribute positively to the society with their “Learn to
bake” initiative to encourage households to earn by starting
their own small-scale businesses. Cake Walk products can be
enjoyed by kids and adults alike, and their products come in
an array of flavors, shapes and sizes.
Every individual in our planet is busy in his / her own
world these days. The busy schedules and work preoccupations
of many people hinder them from spending nominal amount of
time with their families.
To address this concern, we have come up with our MACH
Tours and Travels, our motto being, “Breaching the
Boundaries!” which aims at not only giving its customers the best
and most comfortable tour, but also an enjoyable and
memorable experiences.
We differ from our competitors in various ways. For a start, we
emphasize that our profit is not in the income from this business,
but in the satisfaction of our customers. Added to that, we focus
on improving the ease of travel, the luxury of trip, the quality of
time spent and the worth of pay.
There is a variety of customers we come across: some will want
their trip to be extravagant, while some require it to be cost
effective; some need a long vacation, while some choose just a
weekend away.
Our mission: In order to meet the desires of this large range of
people and to include all the factors of a hearty holiday, we have
devised our strategies and planned our processes, thus, setting us
apart from the others.
Our vision: As the main priority, a year from now, we target on
contenting as many customers as possible through our services.
The following sections of this document includes our roles in
planning, decision making, staffing, leading and communicating
in which we highlight various aspects of our organization,
including the pros and cons of travelling with us.
The purpose of this paper is to highlight the general
terms and definitions that falls under the ‘common set’ in the
intersection of the sets Meteorology and Aerospace Engineering.
It begins with the universal explanations for the meteorological
phenomena under the ‘common set’ followed by the
categorization of clouds and their influences on the aerial
vehicles, the instrumentation used in Aeronautics to determine
the required Meteorological quantities, factors affecting aviation,
effects of aviation on the clouds, and the corresponding protocols
involved in deciphering the ‘common set’ elements.
It also talks about the relation between airport construction and
Geology prior to concluding with the uses and successes of
Meteorology in the field of Aerospace.
A Study on Impact of Internal Mobility on Organisational Performance: A Case ...IJLT EMAS
Over a time, manufacturing Industry in India is essentially an outstanding amongst the most well-known enterprises in Indian market. Manufacturing is the producing of goods and a service using labor and other machinery tools this helps to understand the organization performance directly or indirectly has an impact on internal mobility of an employee. Internal mobility mainly tells that relying upon worker's expertise skill and prerequisites with the toss of the employment with organizational commitment and the change in job structure, job design occurs with or without raise in the salary. Organization performance which has many factors which influence the performance but internal mobility is also a supporting factor which has an impact in achieving the vision of the company. This gives an understanding that apart from providing all the necessary facility and good working culture, healthy promotion and transfer employee exit rates are increasing. Thus, internal mobility is most preferable objective to success which implies observable career accomplishments such as promotion, transfer & hierarchical level held and salary. In future to achieve internal mobility, company should adapt the principle of succession management at all ranks, provide transparent discussion of skill and the potential, as well as organizational needs. The reason for this would the favoritism and lack of recognition which is making an employee dissatisfaction towards their organization by this I conclude that the unfair or unethical practices in organization with respect to the internal mobility in the future periods make employee unhappy this is one of the reason to leave an organization which creates a huge impact in the organization performance
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Design of Multiplexers, Decoder and a Full Subtractor using Reversible Gates
1. International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Is
www.ijltemas.in
Design of Multiplexers, Decoder and a Full
Subtractor using Reversible Gates
Soham Bhattacharya
1,2,3
Electronics and Communication Engineering Department, Heritage Institut
Abstract- This paper shows an effective design of
circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full
subtractor using reversible gates. This paper also evaluates
number of reversible gates used and garbage output
implementing each combinational circuit.
Keywords - Reversible Logic Gates, Multiplexer
Subtractor Garbage output
I. INTRODUCTION
n the early 1960, R. Landauer proved that irreversible
computation results in KTln2 joules of energy dissipation
due to the each bit of information loss where K = Boltzmann’s
constant, T = Temperature at which computation is performed
[1]. Later in 1973, C.H. Bennett showed that KTln2 joules of
energy dissipation can be eliminated, if the computation is
performed in a reversible manner [2].
A multiplexer or MUX is a device that selects between
different analog or digital input signals and forwards it to a
single output signal. A MUX of 2n
inputs has n select lines,
which are used to select which input line is to be sent to the
output. A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of 2
unique output lines [3]. A full Subtractor is a combinational
circuit that performs subtraction of two bits, one is minuend
and other is subtrahend. The full subtractor circuit has three
inputs and two outputs. The three inputs A, B and Bin, denote
the minuend, subtrahend and previous borrow respectively.
The two outputs D and Bout represent the difference and
output borrows respectively.
II. REVERSIBLE LOGIC
‘Reversible Computation’ is defined as a model of
computation where computational process at some extent, is
reversible. It means that it can reserve the data as long as it
requires and when needed [4]. Reversible gate is basically
n X n logic gate, where, if ‘n’ inputs are given, we will get ‘n’
outputs. Properties of reversible logic are like it can recover
the state of inputs from the outputs, it follows bijective
mapping i.e. when ‘n’ number of inputs are taken, and one can
get ‘n’ number of outputs from the gates. The circuit obtained
will be acyclic, i.e. feedback will be there but Fan
be more than one. Parameters to determine the complexity and
performance of circuits[5,6] are the number of reversible
gates, garbage output which is the number of unused outputs
I
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Issue II, February 2020 | ISSN 2278-2540
esign of Multiplexers, Decoder and a Full
Subtractor using Reversible Gates
Soham Bhattacharya1
, Sourav Goswami2
, Anindya Sen3
Electronics and Communication Engineering Department, Heritage Institute of Technology, Kolkata, India
design of combinational
2:1, 4:1 multiplexers, 2:4 decoder and a full
This paper also evaluates
garbage outputs in
, Multiplexer, Decoder, Full
n the early 1960, R. Landauer proved that irreversible
in KTln2 joules of energy dissipation
due to the each bit of information loss where K = Boltzmann’s
constant, T = Temperature at which computation is performed
[1]. Later in 1973, C.H. Bennett showed that KTln2 joules of
ed, if the computation is
A multiplexer or MUX is a device that selects between
different analog or digital input signals and forwards it to a
inputs has n select lines,
d to select which input line is to be sent to the
A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of 2n
A full Subtractor is a combinational
ction of two bits, one is minuend
and other is subtrahend. The full subtractor circuit has three
B and Bin, denote
the minuend, subtrahend and previous borrow respectively.
the difference and
‘Reversible Computation’ is defined as a model of
computation where computational process at some extent, is
reversible. It means that it can reserve the data as long as it
hen needed [4]. Reversible gate is basically an
n X n logic gate, where, if ‘n’ inputs are given, we will get ‘n’
Properties of reversible logic are like it can recover
the state of inputs from the outputs, it follows bijective
n’ number of inputs are taken, and one can
get ‘n’ number of outputs from the gates. The circuit obtained
will be acyclic, i.e. feedback will be there but Fan-out will not
Parameters to determine the complexity and
[5,6] are the number of reversible
the number of unused outputs
used in the reversible gates, and quantum cost which is the
cost of the circuit with respect to the cost of a primitive
gate.In the past few decades, the Reversible logic has emerged
as one of the promising research areas find its applications in
various emerging technologies such as Bioinformatics,
Cryptography, Optical computing, Nanotechnology, DNA
computing, and Quantum computing etc
III. REVERSIBLE GATES USED
There are several number of reversible gates used to
implement various complex circuits, but
have used 3X3 NFT GATE to implement multiplexer
2:1 and 4:1), 3X3 TOFFOLI GATE to implement 2:4
and three reversible gates (4X4
FEYNMANN GATE, 3X3 FREDKIN GATE) to implement a
full subtractor using two half subtractor
1. NFT Gate:
It is a 3X3 gate with inputs A, B and C and outputs X, Y and
Z, where X = A XOR B, Y = B’C XOR AC,
AC’.
Fig.1 denotes the basic logic diagram of NFT
2. TOFFOLI Gate:
It is a 3X3 reversible gate with inputs A, B and C and outputs
X, Y and Z, where X = A,
Y = B, Z = (A.B) XOR C [8].
Fig. 2 denotes the basic logic diagram of TOFFOLI
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Page 106
esign of Multiplexers, Decoder and a Full
Subtractor using Reversible Gates
e of Technology, Kolkata, India
and quantum cost which is the
cost of the circuit with respect to the cost of a primitive
n the past few decades, the Reversible logic has emerged
as one of the promising research areas find its applications in
various emerging technologies such as Bioinformatics,
Cryptography, Optical computing, Nanotechnology, DNA
ting etc [7].
REVERSIBLE GATES USED
There are several number of reversible gates used to
implement various complex circuits, but in this paper, we
NFT GATE to implement multiplexers (both
TOFFOLI GATE to implement 2:4 Decoder
4X4 HNG GATE, 2X2
FREDKIN GATE) to implement a
full subtractor using two half subtractors.
It is a 3X3 gate with inputs A, B and C and outputs X, Y and
Z, where X = A XOR B, Y = B’C XOR AC, Z = BC XOR
logic diagram of NFT Gate
It is a 3X3 reversible gate with inputs A, B and C and outputs
logic diagram of TOFFOLI Gate
2. International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Is
www.ijltemas.in
3. HNG Gate:
It is a 4X4 reversible gate with inputs A, B, C and D and
outputs W, X, Y and Z, where W= A, X = B, Y = A XOR B
XOR C XOR D, Z = (A XOR B).C XOR (A.B) XOR D.
Fig. 3 denotes the basic logic diagram of HNG Gate.
4. FEYNMANN Gate:
It is a 2x2 reversible gate with inputs A and B and outputs X
and Y, where X = A and Y = A XOR B.
Fig. 4 denotes the basic logic diagram of FEYNMANN Gate.
5. FREDKIN Gate:
It is a 3X3 reversible gate with inputs A, B and C and outputs
X, Y and Z, where X = A, Y = (A’.B) XOR (A.C), Z = (A’.C)
XOR (A.B).
Fig. 5 denotes the basic logic diagram of FREDKIN
IV. MULTIPLEXER
Multiplexer or ‘MUX’ is a combinational logic circuit, which
is designed for switching of several input lines to a single
common output line by the application of a control signal.
MUX can be of different forms like 2:1, 4:1, 8:1, and 16:1 and
many more. That means, if 2n
input lines are given, one can
get one output line in case of a multiplexer.
The basic logic diagram and truth table of a 2:1 MUX is
shown in Fig. 6(A) and 6(B) respectively.
A. 2:1 MUX:
For a 2:1 MUX, the output line (Y) is given by:
𝑌 = S.I1 + S’.I0 (1)
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Issue II, February 2020 | ISSN 2278-2540
It is a 4X4 reversible gate with inputs A, B, C and D and
outputs W, X, Y and Z, where W= A, X = B, Y = A XOR B
XOR C XOR D, Z = (A XOR B).C XOR (A.B) XOR D.
logic diagram of HNG Gate.
reversible gate with inputs A and B and outputs X
logic diagram of FEYNMANN Gate.
It is a 3X3 reversible gate with inputs A, B and C and outputs
(A’.B) XOR (A.C), Z = (A’.C)
logic diagram of FREDKIN Gate
Multiplexer or ‘MUX’ is a combinational logic circuit, which
is designed for switching of several input lines to a single
common output line by the application of a control signal.
MUX can be of different forms like 2:1, 4:1, 8:1, and 16:1 and
input lines are given, one can
The basic logic diagram and truth table of a 2:1 MUX is
For a 2:1 MUX, the output line (Y) is given by:
Where, I0 and I1 are the input lines, S is the select line and Y
is the output line.
Fig. 6(A)
S I0 I1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Fig. 6(B)
Fig.6: (A) denotes the basic logic diagram of
line, I0 and I1 are the input lines and Y is the output line.
truth table of the same.
B. 4:1 MUX:
The basic logic diagram and truth table of a 4:1 MUX is
shown in Fig. 7(A) and 7(B) respectively.
For a 4:1 MUX, the output line (Y) is given by:
𝑌 = 𝑆0 . 𝑆1 . 𝐼0 + 𝑆0. 𝑆1 . 𝐼1 + 𝑆0
Where, I0, I1, I2 and I3 are input lines, S0 and S1 are select
lines and Y is the output line.
Fig. 7(A)
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Page 107
here, I0 and I1 are the input lines, S is the select line and Y
I1 Y
0 0
1 0
0 1
1 1
0 0
1 1
0 0
1 1
(A) denotes the basic logic diagram of 2:1 MUX, where S is the select
is the output line. (B) denotes the
the same.
The basic logic diagram and truth table of a 4:1 MUX is
shown in Fig. 7(A) and 7(B) respectively.
the output line (Y) is given by:
. 𝑆1. 𝐼2 + 𝑆0. 𝑆1. 𝐼3 (2)
Where, I0, I1, I2 and I3 are input lines, S0 and S1 are select
3. International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Is
www.ijltemas.in
S1 S0
0 0
0 1
1 0
1 1
Fig. 7(B)
Fig.7: (A) denotes the basic logic diagram of 4:1 MUX, where
select lines, I0 to I3 are the input lines and Y is the output line.
the truth table of the same.
C. Multiplexers Using Reversible Gates:
For implementing 2:1 MUX, one 3X3 NFT gate is required
and for implementing 4:1 MUX, three 3X3
required.
The implementation of 2:1 and 4:1 multiplexers is shown in
Fig.8 and 9 respectively.
Fig. 8 denotes the implementation of 2:1 MUX using 3X3
I0, I1 and S are the input lines and Y is the output line.
Fig. 8 shows the implementation of 4:1 MUX using three
where I0 to I3 and S0, S1 are input lines and Y is the output line.
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Issue II, February 2020 | ISSN 2278-2540
Y
I0
I1
I2
I3
, where S0, S1 are the
select lines, I0 to I3 are the input lines and Y is the output line. (B) denotes
Multiplexers Using Reversible Gates:
NFT gate is required
3X3 NFT gates are
The implementation of 2:1 and 4:1 multiplexers is shown in
3X3 NFT Gate, where
and Y is the output line.
the implementation of 4:1 MUX using three 3X3 NFT Gates,
and Y is the output line.
V. DECODER
A Decoder is a combinational circuit
into a set of signals. It has ‘n’ inputs and 2
are simpler to design. Suppose, the numbers of inputs are
then the number of outputs will be 2
Let us take an example of a 2:4 Decoder using reversible
gates.
A. 2:4 Decoder:
In a 2:4 decoder, there are four output lines, such as,
𝐼0 = 𝐴. 𝐵
𝐼1 = 𝐴 . 𝐵
𝐼2 = 𝐴. 𝐵
𝐼3 = 𝐴 . 𝐵′
Where, A and B are the input lines and I0 to I3 are the output
lines.
The basic block diagram and truth table of a 2:4 Decoder
shown in Fig. 9(A) and (B) respectively.
Fig. 9(A)
E A B I0
0 × × 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
Fig. 9(B)
Fig.9: (A) denotes the basic logic diagram of 2:4 Decoder
the input lines and I0 to I3 are the output lines
of the same.
B. 2:4 Decoder Using Reversible Gates:
2:4 decoder can be implemented using four
gates and two 1X1 NOT gates. The diagram is shown in Fig.
10.
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V. DECODER
A Decoder is a combinational circuit which changes a code
into a set of signals. It has ‘n’ inputs and 2n
outputs. Decoders
to design. Suppose, the numbers of inputs are 8,
then the number of outputs will be 28
or 256.
Let us take an example of a 2:4 Decoder using reversible
a 2:4 decoder, there are four output lines, such as,
(3)
(4)
(5)
(6)
Where, A and B are the input lines and I0 to I3 are the output
The basic block diagram and truth table of a 2:4 Decoder is
shown in Fig. 9(A) and (B) respectively.
I1 I2 I3
0 0 0
0 0 0
1 0 0
0 1 0
0 0 1
Fig.9: (A) denotes the basic logic diagram of 2:4 Decoder, where A and B are
and I0 to I3 are the output lines and (B) denotes the truth table
of the same.
2:4 Decoder Using Reversible Gates:
2:4 decoder can be implemented using four 3X3 TOFFOLI
. The diagram is shown in Fig.
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Fig. 10 shows the implementation of 2:4 Decoder using four
Gates and two 1X1 NOT gates, where A, B are the input lines and I0, I1, I
and I3 are the output lines.
VI. FULL SUBTRACTOR
A subtractor can be designed like an adder using same
approach. A full subtractor is a combinational circuit, used to
perform subtraction of three inputs, the minuend, the
subtrahend and borrow in. Two output lines are generated
which are difference and borrow out. A reversible half
subtractor is designed using two TSG gates
subtractor can be designed using two half subtractors.
Difference output and borrow out output can be given as:
𝐷𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒 = 𝐴 𝑋𝑂𝑅 𝐵 𝑋𝑂𝑅 𝐵𝑖𝑛
𝐵𝑜𝑟𝑟𝑜𝑤 𝑜𝑢𝑡 = (𝐴 𝑋𝑂𝑅 𝐵) . 𝐵𝑖𝑛 𝑋𝑂𝑅 (𝐴 . 𝐵)
Where, A, B and Bin are the inputs and Difference and
Borrow out are the outputs.
The block diagram and truth table of a Full Subtractor is
shown in Fig. 11(A) and (B) respectively.
Fig. 11(A)
International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume IX, Issue II, February 2020 | ISSN 2278-2540
the implementation of 2:4 Decoder using four 3X3 TOFFOLI
, B are the input lines and I0, I1, I2
A subtractor can be designed like an adder using same
subtractor is a combinational circuit, used to
, the minuend, the
subtrahend and borrow in. Two output lines are generated
A reversible half
subtractor is designed using two TSG gates in [4]. A full
subtractor can be designed using two half subtractors.
Difference output and borrow out output can be given as:
(7)
) (8)
Where, A, B and Bin are the inputs and Difference and
The block diagram and truth table of a Full Subtractor is
A B Bin
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Fig. 11(B)
Fig.11: (A) denotes the basic block diagram of Full Subtractor, where A, B,
and Bin are the input lines, and Diff denotes difference output line, and Bout
denotes the borrow out output line. (B) denotes the truth table of the same
B. Full Subtractor Using Reversible Gates:
A full subtractor circuit can be implemented using three
reversible gates, such as 4X4 HNG gate,
gate and 3X3 FREDKIN gate in Fig.12.
Fig. 12 shows the implementation of Full Subtractor using reversible gates,
where A, B and Bin are the input lines and Diff denotes the Difference output
line and Borrow denotes the borrow output
VII. PERFORMANCE ANALYSIS
METHODS
GARBAGE
OUTPUTS
2:1 MUX 2
4:1 MUX 8
2:4 DECODER 8
FULL SUBTRACTOR 4
Fig. 13 shows the performance details of number of
the above implementations.
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Diff Bout
0 0
1 1
1 1
0 1
1 0
0 0
0 0
1 1
Fig. 11(B)
Fig.11: (A) denotes the basic block diagram of Full Subtractor, where A, B,
and Diff denotes difference output line, and Bout
denotes the borrow out output line. (B) denotes the truth table of the same.
Full Subtractor Using Reversible Gates:
A full subtractor circuit can be implemented using three
NG gate, 2X2 FEYNMANN
FREDKIN gate in Fig.12.
the implementation of Full Subtractor using reversible gates,
Diff denotes the Difference output
line and Borrow denotes the borrow output line.
VII. PERFORMANCE ANALYSIS
GARBAGE
OUTPUTS
NO. OF
REVERSIBLE
GATES
1
3
6
3
Fig. 13 shows the performance details of number of gates, garbage outputs of
the above implementations.
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The table of Fig. 13 shows the performance of the
implemented device using reversible gates in terms of number
of gates and the garbage outputs.
VIII. CONCLUSION
In this paper, 2:1 and 4:1 multiplexers, 2:4 decoder and a full
subtractor has been implemented using reversible gates in an
efficient way. For the designing of 2:1 and 4:1 multiplexers,
numbers of gates used are 1 and 3. Garbage outputs are 2 and
8 respectively. For the designing of 2:4 decoder, the number
of gates used and garbage outputs are 6 and 8 respectively and
in case of a full subtractor, number of gates used are 3 and
garbage outputs are 4. So, one can implement these
combinational circuits using these reversible gates from the
details shown in the table.
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[3] M.Morris Mano.: Digital Design. Prentice Hall Publisher (2001)
[4] Soham Bhattacharya, Anindya Sen "Power and Delay Analysis of
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