The document summarizes a research paper about designing a fast multiplier for FIR filters using a modified Booth encoding algorithm. It begins by introducing FIR filters and the need for high-speed multipliers in DSP systems. It then reviews existing memory-based algorithms like fixed-width multipliers and Booth multipliers. The proposed system is described as using a modified Booth encoding algorithm that reduces the number of partial products generated by half compared to other methods. It works by scanning triplet bit patterns to determine whether the partial product should be 0, +Y, -Y, +2Y, or -2Y. This allows for a high-speed parallel multiplier design with fewer computation stages.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
A Spurious-Power Suppression technique for a Low-Power MultiplierIOSR Journals
Abstract: This paper presents the design exploration of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. Keywords-Booth encoder; low power; spurious power suppression technique(SPST); SPST-Adder
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
A Spurious-Power Suppression technique for a Low-Power MultiplierIOSR Journals
Abstract: This paper presents the design exploration of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. Keywords-Booth encoder; low power; spurious power suppression technique(SPST); SPST-Adder
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
Efficient Layout Design of CMOS Full SubtractorIJEEE
Arithmetic circuits and for that matter Combinational circuit design is very important part of VLSI design process. The pertinent issues involved are layout area and power consumption. The main aim of this paper is to design a full subtractor using 90 nm technology. The proposed full subtractor has been designed and simulated using DSCH 3.1 auto-generated design and using Microwind 3.1 simulation software for semi-custom design. The results obtained show that the semi-custom design is area efficient than the auto-generated design. On the other hand, power consumption in the later is more as compared to the auto- generated design.
SURVEY ON POLYGONAL APPROXIMATION TECHNIQUES FOR DIGITAL PLANAR CURVESZac Darcy
Polygon approximation plays a vital role in abquitious applications like multimedia, geographic and object
recognition. An extensive number of polygonal approximation techniques for digital planar curves have
been proposed over the last decade, but there are no survey papers on recently proposed techniques.
Polygon is a collection of edges and vertices. Objects are represented using edges and vertices or contour
points (ie. polygon). Polygonal approximation is representing the object with less number of dominant
points (less number of edges and vertices). Polygon approximation results in less computational speed and
memory usage. This paper deals with comparative study on polygonal approximation techniques for digital
planar curves with respect to their computation and efficiency.
A Novel Cosine Approximation for High-Speed Evaluation of DCTCSCJournals
This article presents a novel cosine approximation for high-speed evaluation of DCT (Discrete Cosine Transform) using Ramanujan Ordered Numbers. The proposed method uses the Ramanujan ordered number to convert the angles of the cosine function to integers. Evaluation of these angles is by using a 4th degree Polynomial that approximates the cosine function with error of approximation in the order of 10^-3. The evaluation of the cosine function is explained through the computation of the DCT coefficients. High-speed evaluation at the algorithmic level is measured in terms of the computational complexity of the algorithm. The proposed algorithm of cosine approximation increases the overhead on the number of adders by 13.6%. This algorithm avoids floating-point multipliers and requires N/2log2N shifts and (3N/2 log2 N)- N + 1 addition operations to evaluate an N-point DCT coefficients thereby improving the speed of computation of the coefficients .
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
A Fast Floating Point Double Precision Implementation on FpgaIJERA Editor
In the modern day digital systems, floating point units are an important component in many signal and image
processing applications. Many approaches of the floating point units have been proposed and compared with
their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for
floating point operations, single and double. In the proposed architecture double precision floating point unit is
used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high
speed adder, which is shared among other operations and can perform operations independently as a separate
unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing
technique which allows performing the operations with the minimum usage of the resources while computing
the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results
show the 23% improvement in the speed of the designed circuit
Area Efficient 4-Bit Full Adder Design using CMOS 90 nm Technology IJEEE
To any digital circuit reduction of surface area is one of the important parameter. Very large scale integration VLSI provides the way to reduce the silicon area. In this paper area efficient design of 4 bit full adder is developed. Adder is one important element in computer arithmetic. It uses for the addition of binary numbers. To design 4-bit full adder two different methods are used in this paper. First is fully auto CMOS design and second is semicustom design. In first fully automatic CMOS design schematic and layout of 4- bit full adder are developed. In second semicustom design method layout of 4-bit full adder is developed by using number of fringers. The layouts of both techniques are simulated using 90nm technology. It can be observed from the simulated results that semicustom layout results in 72% reduction of silicon area as compared to full automatic CMOS design.
Design, Develop and Implement an Efficient Polynomial DividerIJLT EMAS
Polynomial Division is a most common numerical
operation experienced in many filters and similar circuits next to
multiplication, addition and subtraction. Due to frequent use of
such components in mobile and other communication
applications, a fast polynomial division would improve overall
speed for many such applications. This project is to design,
develop and implement an efficient polynomial divider
algorithm, along with the circuit. Next its output performance
result is verified using Verilog simulation. A literature survey on
the normal division algorithms currently used by ALU’s to
perform division for large numbers, yielded Booth’s algorithm,
Restoring and Non-restoring algorithm. Verilog simulation of
these algorithms were used to derive efficiency in terms of the
timing characteristics, required chip area and power dissipation.
Initially, performance analysis of the existing algorithms was
done based on the simulated outputs. Later similar analysis with
the updated polynomial divider circuit is performed.
Model reduction of unstable systems based on balanced truncation algorithm IJECEIAES
Model reduction of a system is an approximation of a higher-order system to a lower-order system while the dynamic behavior of the system is almost unchanged. In this paper, we will discuss model order reduction (MOR) strategies for unstable systems, in which the method based on the balanced truncation algorithm will be focused on. Since each MOR algorithm has its strengths and weakness, practical applications should be suitable for each specific requirement. Simulation results will demonstrate the correctness of the algorithms.
A hybrid bacterial foraging and modified particle swarm optimization for mode...IJECEIAES
This paper study the model reduction procedures used for the reduction of large-scale dynamic models into a smaller one through some sort of differential and algebraic equations. A confirmed relevance between these two models exists, and it shows same characteristics under study. These reduction procedures are generally utilized for mitigating computational complexity, facilitating system analysis, and thence reducing time and costs. This paper comes out with a study showing the impact of the consolidation between the Bacterial-Foraging (BF) and Modified particle swarm optimization (MPSO) for the reduced order model (ROM). The proposed hybrid algorithm (BF-MPSO) is comprehensively compared with the BF and MPSO algorithms; a comparison is also made with selected existing techniques.
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. Here the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision are considered. In this multiple constant multiplication/accumulation (MCMA) is used to reduce the area, which reduces the cost and power dissipation and hardware resources also reduced. The MCMA module is realized by accumulating all the partial products (PPs) where unnecessary PP bits (PPBs) are removed without affecting the final precision of the outputs. The bit widths of all the filter coefficients are minimized using non uniform quantization with unequal word lengths in order to reduce the hardware cost while still satisfying the specification of the frequency response.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Efficient Layout Design of CMOS Full SubtractorIJEEE
Arithmetic circuits and for that matter Combinational circuit design is very important part of VLSI design process. The pertinent issues involved are layout area and power consumption. The main aim of this paper is to design a full subtractor using 90 nm technology. The proposed full subtractor has been designed and simulated using DSCH 3.1 auto-generated design and using Microwind 3.1 simulation software for semi-custom design. The results obtained show that the semi-custom design is area efficient than the auto-generated design. On the other hand, power consumption in the later is more as compared to the auto- generated design.
SURVEY ON POLYGONAL APPROXIMATION TECHNIQUES FOR DIGITAL PLANAR CURVESZac Darcy
Polygon approximation plays a vital role in abquitious applications like multimedia, geographic and object
recognition. An extensive number of polygonal approximation techniques for digital planar curves have
been proposed over the last decade, but there are no survey papers on recently proposed techniques.
Polygon is a collection of edges and vertices. Objects are represented using edges and vertices or contour
points (ie. polygon). Polygonal approximation is representing the object with less number of dominant
points (less number of edges and vertices). Polygon approximation results in less computational speed and
memory usage. This paper deals with comparative study on polygonal approximation techniques for digital
planar curves with respect to their computation and efficiency.
A Novel Cosine Approximation for High-Speed Evaluation of DCTCSCJournals
This article presents a novel cosine approximation for high-speed evaluation of DCT (Discrete Cosine Transform) using Ramanujan Ordered Numbers. The proposed method uses the Ramanujan ordered number to convert the angles of the cosine function to integers. Evaluation of these angles is by using a 4th degree Polynomial that approximates the cosine function with error of approximation in the order of 10^-3. The evaluation of the cosine function is explained through the computation of the DCT coefficients. High-speed evaluation at the algorithmic level is measured in terms of the computational complexity of the algorithm. The proposed algorithm of cosine approximation increases the overhead on the number of adders by 13.6%. This algorithm avoids floating-point multipliers and requires N/2log2N shifts and (3N/2 log2 N)- N + 1 addition operations to evaluate an N-point DCT coefficients thereby improving the speed of computation of the coefficients .
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
A Fast Floating Point Double Precision Implementation on FpgaIJERA Editor
In the modern day digital systems, floating point units are an important component in many signal and image
processing applications. Many approaches of the floating point units have been proposed and compared with
their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for
floating point operations, single and double. In the proposed architecture double precision floating point unit is
used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high
speed adder, which is shared among other operations and can perform operations independently as a separate
unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing
technique which allows performing the operations with the minimum usage of the resources while computing
the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results
show the 23% improvement in the speed of the designed circuit
Area Efficient 4-Bit Full Adder Design using CMOS 90 nm Technology IJEEE
To any digital circuit reduction of surface area is one of the important parameter. Very large scale integration VLSI provides the way to reduce the silicon area. In this paper area efficient design of 4 bit full adder is developed. Adder is one important element in computer arithmetic. It uses for the addition of binary numbers. To design 4-bit full adder two different methods are used in this paper. First is fully auto CMOS design and second is semicustom design. In first fully automatic CMOS design schematic and layout of 4- bit full adder are developed. In second semicustom design method layout of 4-bit full adder is developed by using number of fringers. The layouts of both techniques are simulated using 90nm technology. It can be observed from the simulated results that semicustom layout results in 72% reduction of silicon area as compared to full automatic CMOS design.
Design, Develop and Implement an Efficient Polynomial DividerIJLT EMAS
Polynomial Division is a most common numerical
operation experienced in many filters and similar circuits next to
multiplication, addition and subtraction. Due to frequent use of
such components in mobile and other communication
applications, a fast polynomial division would improve overall
speed for many such applications. This project is to design,
develop and implement an efficient polynomial divider
algorithm, along with the circuit. Next its output performance
result is verified using Verilog simulation. A literature survey on
the normal division algorithms currently used by ALU’s to
perform division for large numbers, yielded Booth’s algorithm,
Restoring and Non-restoring algorithm. Verilog simulation of
these algorithms were used to derive efficiency in terms of the
timing characteristics, required chip area and power dissipation.
Initially, performance analysis of the existing algorithms was
done based on the simulated outputs. Later similar analysis with
the updated polynomial divider circuit is performed.
Model reduction of unstable systems based on balanced truncation algorithm IJECEIAES
Model reduction of a system is an approximation of a higher-order system to a lower-order system while the dynamic behavior of the system is almost unchanged. In this paper, we will discuss model order reduction (MOR) strategies for unstable systems, in which the method based on the balanced truncation algorithm will be focused on. Since each MOR algorithm has its strengths and weakness, practical applications should be suitable for each specific requirement. Simulation results will demonstrate the correctness of the algorithms.
A hybrid bacterial foraging and modified particle swarm optimization for mode...IJECEIAES
This paper study the model reduction procedures used for the reduction of large-scale dynamic models into a smaller one through some sort of differential and algebraic equations. A confirmed relevance between these two models exists, and it shows same characteristics under study. These reduction procedures are generally utilized for mitigating computational complexity, facilitating system analysis, and thence reducing time and costs. This paper comes out with a study showing the impact of the consolidation between the Bacterial-Foraging (BF) and Modified particle swarm optimization (MPSO) for the reduced order model (ROM). The proposed hybrid algorithm (BF-MPSO) is comprehensively compared with the BF and MPSO algorithms; a comparison is also made with selected existing techniques.
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. Here the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision are considered. In this multiple constant multiplication/accumulation (MCMA) is used to reduce the area, which reduces the cost and power dissipation and hardware resources also reduced. The MCMA module is realized by accumulating all the partial products (PPs) where unnecessary PP bits (PPBs) are removed without affecting the final precision of the outputs. The bit widths of all the filter coefficients are minimized using non uniform quantization with unequal word lengths in order to reduce the hardware cost while still satisfying the specification of the frequency response.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
VLSI Implementation of High Speed & Low Power Multiplier in FPGAIOSR Journals
Abstract : We known that different multipliers consume most of the power in DSP computations, FIR filters.
Hence, it is very important factor for modern DSP systems to built low-power multipliers to minimize the power
dissipation. In this paper, we presents high speed & low power Row Column bypass multiplier design
methodology that inserts more number of zeros in the multiplicand thereby bypass the number of zero in row &
Column as well as reduce power consumption. The bypassing of zero activity of the component used in the
process of multiplication, depends on the input bit data. This means if the input bit data is zero, corresponding
row and column of adders need not be addition & transfer bit in next row and column adder circuit. If
multiplicand having more zeros, higher power reduction can be achieved. At last stage of Row & column bypass
multiplier having ripple carry adder which are increase time to generate carry bit to transfer next adder
circuit. To reduce this problem by using Carry bypass adder in place of ripple carry adder, then new
modification of Row &column multiplier having high speed in comparison to simple row & column bypass
multiplier, , the experimental results show that our proposed multiplier reduces power dissipation & High
speed overhead on the average for 4x4, 8x8 and 16x16 multiplier.
Keywords: Low Power, Row & Column bypass Multiplier, Carry bypassing techniques, FPGA, Xilinx
Comparative Design of Regular Structured Modified Booth MultiplierVLSICS Design
Multiplication is a crucial function and plays a vital role for practically any DSP system. Several DSP
algorithms require different types of multiplications, specifically modified booth multiplication algorithm.
In this paper, a simple approach is proposed for generating last partial product row for reducing extra
sign (negative bit) bit to achieve more regular structure. As compared to the conventional multipliers these
proposed modified Booth’s multipliers can achieve improved reduction in area 5.9%, power 3.2%, and
delay 0.5% for 8 x 8 multipliers. We can also observe that achievable improvement for 16 x 16 multiplier
in area, power, delay are 4.0%, 2.3%, 0.3% respectively. These multipliers are implemented using verilog
HDL and synthesized by using synopsis design compiler with an Artisan TSMC 90nm Technology
ER Publication,
IJETR, IJMCTR,
Journals,
International Journals,
High Impact Journals,
Monthly Journal,
Good quality Journals,
Research,
Research Papers,
Research Article,
Free Journals, Open access Journals,
erpublication.org,
Engineering Journal,
Science Journals,
Optimized FIR filter design using Truncated Multiplier TechniqueIJMER
In this paper we have proposed an efficient way of FIR filter design using truncated multiplier technique. The Multiplication operation is performed using Multiple Constant Multiplication Accumulation Truncation (MCMAT) technique. The proposed multiplier design is based on the Wallace tree compressor (WTC). As a result it offers significant improvements in area, delay and power when compared with normal Carry Propagation Addition (CPA). Usually the product of two numbers appears as output in the form of LSB and MSB. The LSB part is truncated and compressed using MCMAT technique. The proposed design produces truncation error which is not more than 1 ulp (unit of least position). While implementing the proposed method experimentally, there is no need of any error compensation circuits and the final output is precised. Hence the area can be saved and the power is also reduced.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSPVLSICS Design
Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...IJERA Editor
With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, the multiplication is an essential arithmetic operation for common DSP applications, such as filtering, convolution, fast Fourier Transform (FFT) etc. To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. This paper presents an approach to reduce power consumption of 2’s compliment multiplier design, in which switching activities are reduced through dynamic by passing of partial products.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
#vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore#blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #blackmagicforlove #blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #Amilbabainuk #amilbabainspain #amilbabaindubai #Amilbabainnorway #amilbabainkrachi #amilbabainlahore #amilbabaingujranwalan #amilbabainislamabad
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. 57
G. Rajesh Babu and C. N. Marimuthu, “Fast multiplier for FIR filters,” International Journal of Scientific and Technical Advancements,
Volume 2, Issue 1, pp. 57-61, 2016.
International Journal of Scientific and Technical Advancements
ISSN: 2454-1532
Fast Multiplier for FIR Filters
G. Rajesh Babu1
, C. N. Marimuthu2
1
Assistant Professor, ECE, SVS College of Engineering, Coimbatore
2
Professor, ECE, Nandha Engineering College, Erode
Email address: rajeshbabu.g@gmail.com
Abstract—RTMCMA (Rounded Truncated Multiple Constant Multiplication and Accumulation) in direct FIR structure is used in FIR filter
design. The proposed technique is n/2 number of partial product achieved via two’s complement method. The Modified Booth Encoding
algorithm is most important algorithm for truncated multiplier and multiplier take important role in high performance system to reduce
power, area and delay optimized is very important in high performance system and DSP system. Truncation error is not more than 1 ulp
(unit of least position). So there is no need of error compensation circuits and the final output will be precised.
Keywords—FIR; booth multiplier.
I. INTRODUCTION
n Microprocessor and DSP high performance systems
uses 70% instructions perform addition and
multiplication. There is need of high speed multiplier.
Low power design directly reduces the operation time in most
of the portable devices. Low power VLSI design has reducing
the power consumption of multiplication algorithms with
having high-speed structures and appropriate performance.
II. REVIEW OF MEMORY BASED ALGORITHMS
Fixed Width Multipliers
Fixed-width design of signed-digit redundant multipliers
that are frequently adopted in high-speed applications. Here
consider the fixed-width multiplier design where the Modified
Booth Encoded (MBE) partial products are represented by
binary signed digits with digit set {+1, 0, +1}. The advantages
of the MBE redundant multiplier are the reduced number of
partial products and the carry-free partial product addition in
the tree structure. Besides, using redundant representations can
avoid the sign extension problem. In order to reduce the
truncation errors and make the error compensation circuit. The
influence of the digits in the minor group can be approximated
by a simple combination of the digits in the major group,
leading to a very simple compensation circuit.
Fast Parallel Multiplier-Accumulator
The parallel multiplier presents a dependence graph (DG)
to visualize and describe the Modified Booth Algorithm
(MBA). Booth multiplier, and the accumulator sections to
ensure the fastest possible implementation. This multiplier
independent of data word size and easy to designing optimum
structures with minimal delay. The pipelined parallel MAC
design is three times faster than other parallel MAC schemes
that are based on the MBA.
Booth Multiplier
Booth multiplication produce the product of two binary
numbers like X and Y, which are having m and n number of
bits(m and n are equal) using 2’s complement representation.
Procedure for implementing the booth algorithm.
1. Making booth table: In booth table there are four
columns, one column for multiplier, second for
previous first LSB of multiplier and other two columns
for partial product accumulator (P). From two
numbers, choose multiplier (X) and multiplicand (Y).
Take 2’s complement of multiplicand (Y). Load X
value in the table. Load 0 for X-1 value. Load 0 in U
and V which will have product of X & Y at the end of
the operation.
2. Booth algorithm requires a detailed inspection of the
multiplier bits for shifting of the partial product (P).
Before shifting, the multiplicand may be added to P,
subtracted from the P, or left unchanged based on the
following rules:1. {Xi Xi-1} is {0 0} Shift only, {Xi
Xi-1} is {1 1} Shift only, {Xi Xi-1} is {0 1} Add Y to
U and shift, {Xi Xi-1} is {1 0} Minus Y from U and
shift.
3. Concatenate U and V and shift arithmetic right shift
which preserves the sign bit of 2’s complement number.
4. Circularly right shift X.
Repeat the same steps until nth bit completed.
III. EXISTING SYSTEM
A parallel tree multiplier designing steps are Partial
Product (PP) generation, PP reduction, and final carry
propagate addition. In deletion operation removes all the
avoidable partial product bits which are shown by the light
gray dots figure 1. Deletion error should be in the range −0.5
ulp ≤ ED≤ 0. From column 3 onwards deletion starts while
first two of partial product bits are kept. After the deletion of
partial product bits, perform column-by-column reduction
method.
When the reduction operation is over, perform the
truncation, which will further remove the first row of (n-1) bits
from column 1 to column (n-1). It will produce the truncation
error which is in the range of −0.5 ulp ≤ ET≤ 0. So the
adjusted truncation error is −0.25 ulp ≤ T≤0.25 ulp. here add a
bias constant of 0.25 ulp for rounding. All the operations
performed finally the PP bits are added to generate final
product. Rounding error is in the form of - 0.5 ulp ≤ ER≤0.5
ulp. The faithfully rounded truncated multiplier, total error is
in range of –ulp< E=(ED+ET+ER) ≤ulp.
I
2. 58
G. Rajesh Babu and C. N. Marimuthu, “Fast multiplier for FIR filters,” International Journal of Scientific and Technical Advancements,
Volume 2, Issue 1, pp. 57-61, 2016.
International Journal of Scientific and Technical Advancements
ISSN: 2454-1532
Fig. 1. Deletion, reduction, truncation, and rounding plus final addition.
Fig. 2. Multiplication/Accumulation using Individual and Combined PP
Compression.
Fig. 3. Existing Truncated Multiplier designs.
3. 59
G. Rajesh Babu and C. N. Marimuthu, “Fast multiplier for FIR filters,” International Journal of Scientific and Technical Advancements,
Volume 2, Issue 1, pp. 57-61, 2016.
International Journal of Scientific and Technical Advancements
ISSN: 2454-1532
Deletion is performed in Stage 1 to remove the PP bits,
whereas the magnitude of the total deletion error is no more
than 2−P−1. The truncation error is less than 1 ulp, so the
accuracy of the final result is improved.
Parallel multipliers are produce product with the 2n
number of bits and rounded to n number of bits to avoid
growth in word size. Figure 2 shows the difference of
individual multiplications and combined multiplication for A
× B + C × D.
PP Truncation and Compression:
The MCMA module is realized by combining all the partial
products (PPs) where unnecessary PP bits (PPBs) are removed
without affecting the final accuracy outputs. Figure 3 shows
the bit widths of all the filter coefficients are minimized using
non uniform quantization with different word lengths in order
to reduce the hardware cost
This architecture of MCMA with truncation (MCMAT)
that removes unnecessary PPBs. The white circles in the L-
shape block represent the undeletable PPBs. The deletion of
the PPBs is represented by black circles. Figure 4 shows the
simulation results of existing and proposed method and figure
5 shows Power summary of existing method.
Fig. 4. Simulation result of existing truncated multiplier.
The existing truncated multiplication simulation result is
obtained by using ModelSim. The input parameters are forced
for signed multiplication is X=10101010; Y=01010101; and
product result is, Z=00110101; by using rounded truncated
multiplication scheme.
Fig. 5. Power summary of existing method.
Drawback of the truncated multiplier method has more
area, delay and consumes more power.
IV. PROPOSED SYSYTEM - MODIFIED BOOTH MULTIPLIER
Modified Booth (MB) is a prevalent form used in
multiplication. It is a redundant signed-digit radix-4 en-coding
technique. Figure 6 shows block Diagram of Modified Booth
Multiplier.
Drawback of the truncated multiplier method has more
area, delay and consumes more power.
Fig. 6. Block diagram of modified booth multiplier.
Its main advantage is that it reduces by half the number of
partial products in multiplication comparing to any other
radix-2 representation. Let us consider the multiplication of
2’s complement numbers and with each number consisting of
n=2k bits. Figure 7 shows the Add end Generation for
Modified Booth Multiplier.
Fig. 7. Add end generation for modified booth multiplier.
4. 60
G. Rajesh Babu and C. N. Marimuthu, “Fast multiplier for FIR filters,” International Journal of Scientific and Technical Advancements,
Volume 2, Issue 1, pp. 57-61, 2016.
International Journal of Scientific and Technical Advancements
ISSN: 2454-1532
One of the solutions of realizing high speed multipliers is
to enhance parallelism which helps to decrease the number of
subsequent calculation stages. The original version of the
Booth algorithm (Radix-2) had two drawbacks.
They are:
The number of add subtract operations and the number of
shift operations becomes variable and becomes inconvenient
in designing parallel multipliers.
The algorithm becomes inefficient when there are isolated
1’s.
These problems are overcome by using modified Radix4
Booth algorithm which scan strings of three bits with the
algorithm given below:
1. Extend the sign bit 1 position if necessary to ensure that
n is even.
2. Append a 0 to the right of the LSB of the multiplier.
3. According to the value of each vector, each Partial
Product will he 0, +y , -y, +2y or -2y. The negative
values of y are made by taking the 2’s complement. The
multiplication of y is done by shifting y by one bit to
the left. Thus, in any case, in designing a n-bit parallel
multipliers, only n/2 partial products are generated.
The modified Booth’s algorithm starts by appending a zero
to the right of X2 (multiplier LSB). Table I shows triplets are
taken beginning at position X-1 and continuing to the MSB
with one bit overlapping between adjacent triplets. If the
number of bits in X (excluding x-1) is odd, the sign (MSB) is
extended one position to ensure that the last triplet contains 3
bits.
TABLE I. Modified Booth Algorithm
Xi Xi-4 Xi-2 Operation Comments
0 0 0 +0 String of zeros
0 1 0 +A A single 1
1 0 0 -2A Beginning of 1’s
1 1 0 -A Beginning of 1’s
0 0 1 +A End of 1’s
0 1 1 +2A End of 1’s
1 0 1 -A A single 0
1 1 1 +0 String of zeros
The low-cost implementations of FIR filters based on the
direct structure in figure with faithfully rounded truncated
multipliers. The MB-RTMCMA module is realized by
accumulating all the partial products (PPs) where unnecessary
PP bits (PPBs) are removed without affecting the final
precision of the outputs.
The bit widths of all the filter coefficients are minimized
using non-uniform quantization with unequal word lengths in
order to reduce the hardware cost while still satisfying the
specification of the frequency response. Figure 8 and 9 shows
the simulation result of FIR filter and proposed truncated
multiplier respectively.
Fig. 8. Simulation result of FIR filter.
Fig. 9. Simulation result of proposed truncated multiplier.
V. EXPERIMENTAL RESULTS AND COMPARISON OF
TRUNCATED MULTIPLIERS
Figure 10 shows the comparison of gate count, power and
delay in bar chart. Table II gives the detailed description of
proposed method is better than existing method.
Fig. 10. Bar chart of existing method and proposed method.
TABLE II. Comparison.
S. No. Description Existing method Proposed method
1 Gate delay 26.51ns 2.63ns
2 Gate count 570 100
3 Power 65mw 55mw
5. 61
G. Rajesh Babu and C. N. Marimuthu, “Fast multiplier for FIR filters,” International Journal of Scientific and Technical Advancements,
Volume 2, Issue 1, pp. 57-61, 2016.
International Journal of Scientific and Technical Advancements
ISSN: 2454-1532
VI. CONCLUSION
RTMCMA leads to the smallest area cost, delay and power
consumption. Partial products are generated directly with the
help of booth encoding table. Further booth encoding table is
converted into combination circuits which results into n/2+1
PP rows ,further direct 2’s complement technique are
implement to reduce n/2+1rows to n/2 ,that shows the results
of gate count used for Modified Booth Rounded truncated
multiplier and is less than Rounded truncated multiplier.
Similarly power analysis results show that proposed Modified
Booth Rounded Truncated Multiplier consume less power than
existing Rounded Truncated Multiplier.
REFERENCES
[1] M. M. Peiro, E. I. Boemo, and L. Wanhammar, “Design of high-speed
multiplierless filters using a nonrecursive signed COMMAON
subexpression algorithm,” IEEE Transactions on Circuits and Systems
II, Analog and Digital Signal Processing, vol. 49, no. 3, pp. 196–203,
2002.
[2] F. Xu, C. H. Chang, and C. C. Jong, “Design of low-complexity FIR
filters based on signed-powers-of-two coefficients with reusable
common subexpressions,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1898–
1907, 2007.
[3] Y. J. Yu and Y. C. Lim, “Design of linear phase FIR filters in
subexpression space using mixed integer linear programming,” IEEE
Transactions on Circuits and Systems I, Regular Papers, vol. 54, no. 10,
pp. 2330–2338, 2007.
[4] P. K. Meher, “New approach to look-up-table design and memory-based
realization of FIR digital filter,” IEEE Transactions on Circuits and
Systems I, Regular Papers, vol. 57, no. 3, pp. 592–603, 2010.
[5] P. K. Meher, S. Candrasekaran, and A. Amira, “FPGA realization of FIR
filters by efficient and flexible systolization using distributed
arithmetic,” IEEE Transactions on Signal Processing, vol. 56, no. 7, pp.
3009–3017, 2008.
[6] S. Hwang, G. Han, S. Kang, and J.-S. Kim, “New distributed arithmetic
algorithm for low-power FIR filter implementation,” IEEE Signal
Processing Letters, vol. 11, no. 5, pp. 463–466, 2004.
[7] C.-H. Chang, J. Chen, and A. P. Vinod, “Information theoretic approach
to complexity reduction of FIR filter design,” IEEE Transactions on
Circuits and Systems I, Regular Papers, vol. 55, no. 8, pp. 2310–2321,
2008.
[8] H.-J. Ko and S.-F. Hsiao, “Design and application of faithfully rounded
and truncated multipliers with combined deletion, reduction, truncation,
and rounding,” IEEE Transactions on Circuits and Systems II, Express
Briefs, vol. 58, no. 5, pp. 304–308, 2011.
[9] J. M. Jou, S. R.Kuang, and R. D. Chen, “Design of low-error fixed-
width multipliers for DSP applications,” IEEE Transactions Circuits and
Systems II, Analog and Digital Signal Processing, vol. 46, no. 6, pp.
836–842, 1999.
[10] L. Van, S. Wang, and W. Feng, “Design of the lower error fixed-width
multiplier and its application,” IEEE Transactions Circuits and Systems
II, Analog and Digital Signal Processing, vol. 47, no. 10, pp. 1112–
1118, 2000.
[11] Y. Takahashi and M. Yokoyama, “New cost-effective VLSI
implementation of multiplierless FIR _lter using common subexpression
elimination,” in Proceedings ISCAS 2005, Kobe, Japan, pp. 845.848,
2005.
[12] Y. C. Lim and S. R. Parker, “FIR filter design over a discrete power-of-
two coefficient space,” IEEE Transactions on Acoustics Speech and
Signal Processing, vol. ASSP-31, no. 6, pp. 583–591, 1983.
[13] Y. C. Lim and S. R. Parker, “Discrete coefficient FIR digital filter
design based upon an LMS criteria,” IEEE Transactions on Circuits and
Systems, vol. CAS-30, no. 10, pp. 723–739, 1983.
[14] Y. C. Lim et al., “Signed power-of-two term allocation scheme for the
design of digital filters,” IEEE Transactions on Circuits and Systems II,
Analog and Digital Signal Processing, vol. 46, no. 5, pp. 577–584, 1999.