This document discusses decoders, encoders, and multiplexers. It provides examples of a 3-input, 8-output decoder, a 2-input, 4-output decoder with an enable, an octal-binary encoder, and a 4-input, 1-output multiplexer. It also briefly describes magnitude comparators.

1. Digital Logic Design
1
Decoder & Encoder
Prof. Shehzad Ali

2. Decoder
 Discrete quantities of information are represented in digital
systems by binary codes.
 A binary code of n bits is capable of representing up to 2n distinct
elements of coded information.
 Is a combinational circuit that converts the binary information
from n input lines to a maximum of 2n unique output lines.
 If the n-bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.
 Called n-to-m-line decode, where m <= 2n minterms of n input
variables.
Decoder

3. Decoder
 Inputs = 3.
 Outputs = 8 (minterms)
Example
Consider three-to-eight-line decoder circuit
Truth Table
Example:
Binary – to –octal
decoder
ONLY one output can be
active at any time

4. Decoder
Logic Diagram

5. Decoder
 A decoder with one or more enable (E) inputs.
 Control the circuit operation.
 E =0, Decoder is disabled.
 E =1, Decoder is enabled.

6. Decoder
Design a two-to-four-line decoder with an enable input.
Truth table
D3D2D1D0BAE
0000XX0
0001001
0010101
0100011
1000111

7. Decoder
Design a two-to-four-line decoder with an enable input.
Logic Diagram

8. Encoder
 Is a digital circuit that performs the inverse operation of a
decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
Example
Design an octal-binary encoder

9. Multiplexer
 Multiplexer is a combinational circuit that selects a binary
information from one of many input lines and directs it to a single
output line.
 The selection of a particular input line is controlled by a set of
selection lines.
• 2n input lines and n selection lines whose bit combinations determine
which input is selected.
 Also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
 The size of a multiplexer is specified by the number 2n of its
data input lines and the single output line.

10. Multiplexer
Example
Design a 2 –to-1 line MUX
 Data Inputs = 21=1
 Selection Input= 1
 Output = 1
YS
0
I00
I11
Function Table

11. Multiplexer
Example
Design a 4 –to-1 line MUX
 Data Inputs = 22 =4
 Selection Input= 2
 Output = 1
Function Table

12. Multiplexer
Example
Design a 4 –to-1 line MUX

13. 13

14. 14

15. Digital Circuits
Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two
numbers, A and B, and determines their relative magnitudes. The
outcome of the comparison is specified by three binary variables that
indicate whether A > B, A = B, or A < B.
The comparison of two numbers
◦ outputs: A>B, A=B, A<B
Design Approaches
◦ the truth table
◦ 2
2n
entries - too complex for large n
15