The document discusses digital circuits including combinational and sequential circuits. It describes various combinational logic circuits such as half adders, full adders, comparators, multiplexers, encoders, decoders. It also discusses sequential circuits and how they employ memory elements. Arithmetic circuits, binary adders, subtractors, and BCD to 7-segment decoders are explained in detail through diagrams and examples.
1. The document discusses combinational logic circuits and describes various types including half adders, full adders, decoders, encoders, multiplexers, and comparators.
2. It provides truth tables and logic expressions to define the functions of these circuits. Diagrams of logic gate implementations are also shown.
3. Examples of specific combinational circuits are analyzed in detail like a 4-bit magnitude comparator, priority encoders, decoders, and a BCD to decimal decoder. Their applications in digital systems are also mentioned.
This document provides an overview of switching theory unit 2, which covers combinational logic circuits and their design procedures. It discusses various combinational logic components like adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. It provides block diagrams, truth tables, and logic expressions for designing these components. The key topics covered include the characteristics of combinational circuits, the 4-step design procedure for any combinational circuit, implementation of full adders and subtractors, working of multiplexers and demultiplexers of different sizes, and working of encoders and decoders.
A multiplexer is a digital circuit with multiple inputs and a single output. It selects one of the inputs using select lines and only allows one output at a time. A multiplexer can have 2, 4, 8, or more inputs depending on the number of select lines used. It is commonly used to route data within a computer from multiple sources to a single destination. Decoders are digital circuits that convert binary codes to activate a single output line. Common decoders include 2-to-4, 3-to-8, and 4-to-16 line decoders. Decoders are used whenever a specific combination of input levels needs to activate a single output. CMOS logic uses both n-type and p-type MOS
Bca 2nd sem-u-1.4 digital logic circuits, digital componentRai University
This document discusses combinational logic circuits and their design. It covers topics like combinational vs sequential logic, common combinational circuits like adders and decoders, and how to design combinational logic circuits through truth tables and K-maps. Examples of specific combinational circuits like full adders, magnitude comparators, decoders and multiplexers are described in detail through diagrams and explanations.
B.sc cs-ii-u-1.4 digital logic circuits, digital componentRai University
This document discusses combinational logic circuits and their analysis and design. It covers common combinational circuits like adders, decoders, encoders, and multiplexers. It provides examples of designing a half adder, full adder, magnitude comparator, and various decoders. Combinational logic circuits are analyzed using truth tables and K-maps to derive Boolean functions.
This document discusses decoders, encoders, and multiplexers. It provides examples of a 3-input, 8-output decoder, a 2-input, 4-output decoder with an enable, an octal-binary encoder, and a 4-input, 1-output multiplexer. It also briefly describes magnitude comparators.
This document provides information about Dr. Krishnanaik Vankdoth and his background and qualifications. It then discusses digital logic design topics like digital circuits, combinational logic, sequential circuits, logic gates, truth tables, adders, decoders, encoders, multiplexers and demultiplexers. Example circuits are provided and the functions of components like full adders, parallel adders, magnitude comparators are explained through diagrams and logic equations.
The document discusses digital circuits including combinational and sequential circuits. It describes various combinational logic circuits such as half adders, full adders, comparators, multiplexers, encoders, decoders. It also discusses sequential circuits and how they employ memory elements. Arithmetic circuits, binary adders, subtractors, and BCD to 7-segment decoders are explained in detail through diagrams and examples.
1. The document discusses combinational logic circuits and describes various types including half adders, full adders, decoders, encoders, multiplexers, and comparators.
2. It provides truth tables and logic expressions to define the functions of these circuits. Diagrams of logic gate implementations are also shown.
3. Examples of specific combinational circuits are analyzed in detail like a 4-bit magnitude comparator, priority encoders, decoders, and a BCD to decimal decoder. Their applications in digital systems are also mentioned.
This document provides an overview of switching theory unit 2, which covers combinational logic circuits and their design procedures. It discusses various combinational logic components like adders, subtractors, multiplexers, demultiplexers, encoders, and decoders. It provides block diagrams, truth tables, and logic expressions for designing these components. The key topics covered include the characteristics of combinational circuits, the 4-step design procedure for any combinational circuit, implementation of full adders and subtractors, working of multiplexers and demultiplexers of different sizes, and working of encoders and decoders.
A multiplexer is a digital circuit with multiple inputs and a single output. It selects one of the inputs using select lines and only allows one output at a time. A multiplexer can have 2, 4, 8, or more inputs depending on the number of select lines used. It is commonly used to route data within a computer from multiple sources to a single destination. Decoders are digital circuits that convert binary codes to activate a single output line. Common decoders include 2-to-4, 3-to-8, and 4-to-16 line decoders. Decoders are used whenever a specific combination of input levels needs to activate a single output. CMOS logic uses both n-type and p-type MOS
Bca 2nd sem-u-1.4 digital logic circuits, digital componentRai University
This document discusses combinational logic circuits and their design. It covers topics like combinational vs sequential logic, common combinational circuits like adders and decoders, and how to design combinational logic circuits through truth tables and K-maps. Examples of specific combinational circuits like full adders, magnitude comparators, decoders and multiplexers are described in detail through diagrams and explanations.
B.sc cs-ii-u-1.4 digital logic circuits, digital componentRai University
This document discusses combinational logic circuits and their analysis and design. It covers common combinational circuits like adders, decoders, encoders, and multiplexers. It provides examples of designing a half adder, full adder, magnitude comparator, and various decoders. Combinational logic circuits are analyzed using truth tables and K-maps to derive Boolean functions.
This document discusses decoders, encoders, and multiplexers. It provides examples of a 3-input, 8-output decoder, a 2-input, 4-output decoder with an enable, an octal-binary encoder, and a 4-input, 1-output multiplexer. It also briefly describes magnitude comparators.
This document provides information about Dr. Krishnanaik Vankdoth and his background and qualifications. It then discusses digital logic design topics like digital circuits, combinational logic, sequential circuits, logic gates, truth tables, adders, decoders, encoders, multiplexers and demultiplexers. Example circuits are provided and the functions of components like full adders, parallel adders, magnitude comparators are explained through diagrams and logic equations.
This document discusses combinational circuit design and provides examples of various combinational logic circuits. It begins with an introduction that defines combinational and sequential circuits. The remainder of the document provides details on specific combinational logic circuits including half adders, full adders, subtractors, encoders, decoders, multiplexers, comparators, and code converters. Worked examples are provided for each circuit type using truth tables, Karnaugh maps, and logic diagrams. Applications of decoders for implementing functions like a full adder are also described.
Combinational circuits are digital circuits whose outputs depend only on the current inputs. They do not have internal memory and include common components like multiplexers, decoders, and adders. A combinational circuit with n inputs can have up to 2^n possible output combinations. Common combinational circuits discussed in the document include half adders, full adders, decoders, and multiplexers along with their truth tables and applications. Sequential circuits differ in that their outputs depend on both current and previous inputs due to internal memory elements like latches and flip-flops.
The truth table is not complete because it is missing the encoding for when no inputs are active. A complete truth table would include a row for all zero inputs to specify the output in that case.
The output equations are:
A0 = D7
A1 = D6 + D5 + D4 + D3
A2 = D2 + D1 + D0
This encodes the highest priority input on the lowest two bits, with the next two highest priorities on the middle bit, and any active input setting the highest bit.
This document provides an overview of combinational logic circuits and their analysis and design. It discusses common combinational circuits like adders, comparators, decoders, and multiplexers. It also covers the design of a 4-bit full adder, magnitude comparator, decoders, and multiplexers. The document is from a course on microprocessor architecture and covers combinational logic as an introduction to microprocessors.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
An encoder is a combinational circuit that performs the reverse operation of a decoder. It has up to 2N input lines and N output lines, and produces a binary code equivalent to the active input. A 4-to-2 encoder has four inputs and two outputs, where only one input can be '1' at a time to produce the respective binary code at the output. There are two main types of encoders: binary encoders and priority encoders. Decoders convert digital signals to analog signals and have N inputs and 2N outputs. Multiplexers have n select lines to choose one of several input signals to send to a single output, while demultiplexers take a single serial input and switch it to one
This presentation introduces digital logic circuits such as encoders, decoders, multiplexers, demultiplexers and logic gates. It is presented by a group consisting of 5 members whose names and student IDs are listed. The topics covered include the definitions of complements, combinational logic circuits, encoder and decoder functions, how multiplexers and demultiplexers work, and the truth tables of common logic gates.
B sc cs i bo-de u-iii combitional logic circuitRai University
This document provides an overview of digital electronics, focusing on logic circuits and combinational logic circuits. It discusses the basics of combinational logic, including standard combinational circuits like adders, subtractors, and multiplexers. It also covers the analysis and design of combinational logic, including examples like a magnitude comparator. Finally, it discusses common combinational logic components like decoders, multiplexers, and full adders.
This document covers decoders, multiplexers, and three-state gates. It defines decoders as having multiple input lines and fewer output lines, with m=2^n outputs. Multiplexers are circuits that select one of several data inputs and direct it to a single output, with 2^M select lines for M inputs. Three-state gates can output high, low, or high impedance states.
This document discusses magnitude comparators and decoders. A magnitude comparator is a circuit that compares two input numbers in binary form and determines if one is greater than, less than, or equal to the other. Magnitude comparators are used in CPUs. Decoders are circuits that convert binary input into unique output lines. Common types include 2-to-4 decoders, 3-to-8 decoders used for 7-segment displays, and 4-to-10 decoders. Decoders have applications in memory systems, I/O selection, and displaying decimal numbers.
This chapter discusses methods for implementing combinational logic functions using circuits. It covers topics such as decoding, encoding, enabling functions, priority encoders, multiplexers, and implementing combinational functions using decoders and OR gates, multiplexers, ROMs, PLAs, PALs, and lookup tables. Implementation examples are provided for decoders, encoders, priority encoders, and multiplexers. The chapter also describes how to expand decoders and multiplexers to handle more inputs and outputs.
This chapter discusses combinational logic functions and circuits. It covers topics such as functions of single and multiple variables, decoding, encoding, selecting, and implementing combinational functions using decoders and OR gates, multiplexers, ROMs, PLAs, PALs, and lookup tables. Expansion techniques for decoders and multiplexers are also presented.
This document provides an overview of combinational logic circuits including half adders, full adders, half subtractors, full subtractors, multiplexers, demultiplexers, encoders, decoders, binary coded decimal adders, arithmetic logic units, and the differences between serial adders and parallel adders. Combinational logic circuits have outputs that are a function of the present inputs only. Common combinational logic elements and their applications are described.
This document discusses various combinational logic circuits including encoders, decoders, and multiplexers. It provides objectives for constructing and verifying binary to gray code converters, gray to binary converters, two to four line decoders, seven segment decoders, priority encoders, and two to one and four to one line multiplexers. It also defines combinational circuits, discusses code conversion procedures for gray codes, different types of decoders including one to two line and two to four line decoders, and applications of multiplexers and demultiplexers. Finally, it contrasts the key differences between combinational and sequential logic circuits.
This document discusses various combinational logic circuits including half adders, full adders, multiplexers, encoders, decoders, priority encoders, and gray code converters. It provides truth tables and logic expressions for each circuit, and shows how to design the logic circuit using K-map simplification of the output expressions. Combinational circuits such as half adders, full adders, and multiplexers are used to perform arithmetic and switching functions. Encoders and decoders convert between binary and coded representations. Priority encoders and gray code converters provide unambiguous codes and minimize bit changes.
This document discusses multiplexers and demultiplexers. It begins by explaining the principles of multiplexing and demultiplexing, which involve routing digital information from multiple inputs to a single output line (multiplexing) and redistributing the information back to multiple outputs (demultiplexing). The document then describes the architecture and operation of multiplexers and demultiplexers, including 2-to-1 and 4-to-1 examples. It also discusses common applications such as data routing and sharing resources.
This document discusses decoders, which are circuits that take a binary input and activate one of multiple outputs. It provides examples of 2-to-4 and 3-to-8 decoders and their truth tables. Decoders are constructed using AND gates, with the number of gates equal to the number of outputs. Larger decoders can be built in parallel, balanced, or tree configurations, with balanced decoders requiring the fewest components.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
This document discusses combinational circuit design and provides examples of various combinational logic circuits. It begins with an introduction that defines combinational and sequential circuits. The remainder of the document provides details on specific combinational logic circuits including half adders, full adders, subtractors, encoders, decoders, multiplexers, comparators, and code converters. Worked examples are provided for each circuit type using truth tables, Karnaugh maps, and logic diagrams. Applications of decoders for implementing functions like a full adder are also described.
Combinational circuits are digital circuits whose outputs depend only on the current inputs. They do not have internal memory and include common components like multiplexers, decoders, and adders. A combinational circuit with n inputs can have up to 2^n possible output combinations. Common combinational circuits discussed in the document include half adders, full adders, decoders, and multiplexers along with their truth tables and applications. Sequential circuits differ in that their outputs depend on both current and previous inputs due to internal memory elements like latches and flip-flops.
The truth table is not complete because it is missing the encoding for when no inputs are active. A complete truth table would include a row for all zero inputs to specify the output in that case.
The output equations are:
A0 = D7
A1 = D6 + D5 + D4 + D3
A2 = D2 + D1 + D0
This encodes the highest priority input on the lowest two bits, with the next two highest priorities on the middle bit, and any active input setting the highest bit.
This document provides an overview of combinational logic circuits and their analysis and design. It discusses common combinational circuits like adders, comparators, decoders, and multiplexers. It also covers the design of a 4-bit full adder, magnitude comparator, decoders, and multiplexers. The document is from a course on microprocessor architecture and covers combinational logic as an introduction to microprocessors.
The document provides an overview of various data processing circuits including multiplexers, demultiplexers, decoders, encoders, adders, flip-flops and other logic gates. It describes the basic functionality and implementation of different types of multiplexers and demultiplexers with varying number of inputs and outputs. Decoder circuits like 1-of-16 decoder are explained along with their truth tables. Different arithmetic building blocks such as half adder, full adder and arithmetic logic unit are covered. The document also discusses flip-flops like RS, D, JK and their edge-triggered variations. Finally, it provides details on binary coded decimal representation.
An encoder is a combinational circuit that performs the reverse operation of a decoder. It has up to 2N input lines and N output lines, and produces a binary code equivalent to the active input. A 4-to-2 encoder has four inputs and two outputs, where only one input can be '1' at a time to produce the respective binary code at the output. There are two main types of encoders: binary encoders and priority encoders. Decoders convert digital signals to analog signals and have N inputs and 2N outputs. Multiplexers have n select lines to choose one of several input signals to send to a single output, while demultiplexers take a single serial input and switch it to one
This presentation introduces digital logic circuits such as encoders, decoders, multiplexers, demultiplexers and logic gates. It is presented by a group consisting of 5 members whose names and student IDs are listed. The topics covered include the definitions of complements, combinational logic circuits, encoder and decoder functions, how multiplexers and demultiplexers work, and the truth tables of common logic gates.
B sc cs i bo-de u-iii combitional logic circuitRai University
This document provides an overview of digital electronics, focusing on logic circuits and combinational logic circuits. It discusses the basics of combinational logic, including standard combinational circuits like adders, subtractors, and multiplexers. It also covers the analysis and design of combinational logic, including examples like a magnitude comparator. Finally, it discusses common combinational logic components like decoders, multiplexers, and full adders.
This document covers decoders, multiplexers, and three-state gates. It defines decoders as having multiple input lines and fewer output lines, with m=2^n outputs. Multiplexers are circuits that select one of several data inputs and direct it to a single output, with 2^M select lines for M inputs. Three-state gates can output high, low, or high impedance states.
This document discusses magnitude comparators and decoders. A magnitude comparator is a circuit that compares two input numbers in binary form and determines if one is greater than, less than, or equal to the other. Magnitude comparators are used in CPUs. Decoders are circuits that convert binary input into unique output lines. Common types include 2-to-4 decoders, 3-to-8 decoders used for 7-segment displays, and 4-to-10 decoders. Decoders have applications in memory systems, I/O selection, and displaying decimal numbers.
This chapter discusses methods for implementing combinational logic functions using circuits. It covers topics such as decoding, encoding, enabling functions, priority encoders, multiplexers, and implementing combinational functions using decoders and OR gates, multiplexers, ROMs, PLAs, PALs, and lookup tables. Implementation examples are provided for decoders, encoders, priority encoders, and multiplexers. The chapter also describes how to expand decoders and multiplexers to handle more inputs and outputs.
This chapter discusses combinational logic functions and circuits. It covers topics such as functions of single and multiple variables, decoding, encoding, selecting, and implementing combinational functions using decoders and OR gates, multiplexers, ROMs, PLAs, PALs, and lookup tables. Expansion techniques for decoders and multiplexers are also presented.
This document provides an overview of combinational logic circuits including half adders, full adders, half subtractors, full subtractors, multiplexers, demultiplexers, encoders, decoders, binary coded decimal adders, arithmetic logic units, and the differences between serial adders and parallel adders. Combinational logic circuits have outputs that are a function of the present inputs only. Common combinational logic elements and their applications are described.
This document discusses various combinational logic circuits including encoders, decoders, and multiplexers. It provides objectives for constructing and verifying binary to gray code converters, gray to binary converters, two to four line decoders, seven segment decoders, priority encoders, and two to one and four to one line multiplexers. It also defines combinational circuits, discusses code conversion procedures for gray codes, different types of decoders including one to two line and two to four line decoders, and applications of multiplexers and demultiplexers. Finally, it contrasts the key differences between combinational and sequential logic circuits.
This document discusses various combinational logic circuits including half adders, full adders, multiplexers, encoders, decoders, priority encoders, and gray code converters. It provides truth tables and logic expressions for each circuit, and shows how to design the logic circuit using K-map simplification of the output expressions. Combinational circuits such as half adders, full adders, and multiplexers are used to perform arithmetic and switching functions. Encoders and decoders convert between binary and coded representations. Priority encoders and gray code converters provide unambiguous codes and minimize bit changes.
This document discusses multiplexers and demultiplexers. It begins by explaining the principles of multiplexing and demultiplexing, which involve routing digital information from multiple inputs to a single output line (multiplexing) and redistributing the information back to multiple outputs (demultiplexing). The document then describes the architecture and operation of multiplexers and demultiplexers, including 2-to-1 and 4-to-1 examples. It also discusses common applications such as data routing and sharing resources.
This document discusses decoders, which are circuits that take a binary input and activate one of multiple outputs. It provides examples of 2-to-4 and 3-to-8 decoders and their truth tables. Decoders are constructed using AND gates, with the number of gates equal to the number of outputs. Larger decoders can be built in parallel, balanced, or tree configurations, with balanced decoders requiring the fewest components.
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Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
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Understanding Inductive Bias in Machine LearningSUTEJAS
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1. SRI RAMAKRISHNA ENGINEERING COLLEGE
Presentation by
Mr.R.Chandru
Assistant Professor(Sr.G)
Department of ECE
Department of Electronics and Communication Engineering
[Educational Service : SNR Sons Charitable Trust]
[Autonomous Institution, Accredited by NAAC with ‘A’ Grade]
[Approved by AICTE and Permanently Affiliated to Anna University, Chennai]
[ISO 9001:2015 Certified and all eligible programmes Accredited by NBA]
VATTAMALAIPALAYAM, N.G.G.O. COLONY POST, COIMBATORE – 641 022.
10-03-2023 1
DIGITAL LOGIC CIRCUITS
3. Decoder
• A decoder is a logic circuit that accepts a set of inputs that represents a
binary number and activates only the output that corresponds to the input
number.
• In other words, a decoder circuit looks at its inputs, determines which
binary number is present there, and activates the one output that
corresponds to that number ;all other outputs remain inactive.
• A decoder is a combinational circuit that converts binary information from
n input lines to a maximum of 2^n unique output lines.
10-03-2023 3
4. Binary Decoder (2 : 4 decoder)
• A binary decoder has n bit binary input and a one activated output out of 2^n
outputs. A binary decoder is used when it is necessary to activate exactly one of
2^n outputs based on an n-bit input value.
• Here the 2 inputs are decoded into 4 outputs, each output representing one of
the minterms of the two input variables.
Truth Table of 2:4 decoder
• As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs
(Y0 – Y3), is active for a given input.
10-03-2023 4
5. Binary Decoder (2 : 4 decoder)
• The output Y0 is active,ie.,Y0= 1 when inputs
A= B= 0,
Y1 is active when inputs, A= 0 and B= 1,
Y2 is active, when input A= 1 and B= 0,
Y3 is active, when inputs A= B= 1.
10-03-2023 5
7. 3-to-8 Line Decoder
• A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7).
Based on the 3 inputs one of the eight outputs is selected.
• The three inputs are decoded into eight outputs, each output representing
one of the minterms of the 3-input variables.
• This decoder is used for binary-to-octal conversion.
Truth Table of 3:8 decoder
10-03-2023 7
9. Example
Construct a 3-to-8 decoder using two 2-to-4 decoders
• Two 2-to-4 line decoders are combined to build a 3-to-8 line decoder.
• The two least significant bits (i.e. A1 and A0) are connected to both decoders.
• Most significant bit (A2) is connected to the enable input of one decoder.
• The complement of most significant bit (A2) is connected to the enable of the
other decoder.
• When A2 = 0, upper decoder is enabled, while the lower is disabled.
• Thus, the outputs of the upper decoder correspond to minterms D0 through
D3.
• When A2 = 1, upper decoder is disabled, while the lower is enabled. Thus, the
outputs of the lower decoder correspond to minterms D4 through D7.
10-03-2023 9
12. Applications
• Decoders are widely used in the memory system of a
computer where they respond to the address code
generated by the central processor to activate a particular
memory location.
• Each memory IC contains many registers that can store
binary numbers (data).
• Each register needs to have its own unique address to
distinguish it from all the other registers.
• A decoder is built into the memory IC’s circuitry and allows
a particular storage register to be activated when a unique
combination of inputs (i.e., its address) is applied.
10-03-2023 12
13. BCD-TO-7-SEGMENT DECODER/DRIVERS
• Most digital equipment has some means for displaying
information in a form that can be understood readily by
the user or operator.
• This information is often numerical data but can also be
alphanumeric (numbers and letters).
• One of the simplest and most popular methods for
displaying numerical digits uses a 7-segment
configuration to form the decimal characters 0 through
9 and sometimes the hex characters A through F.
10-03-2023 13
17. Analysis and design of combinational
logic circuits:
2.3 Encoders
10-03-2023 17
18. Encoder
• An encoder is a digital circuit that performs the inverse operation of a decoder.
Hence, the opposite of the decoding process is called encoding.
• An encoder is a combinational circuit that converts binary information from
2^n input lines to a maximum of n unique output lines.
• It has 2^n input lines, only one which 1 is active at any time and n output lines.
• It encodes one of the active inputs to a coded binary output with n bits. In an
encoder, the number of outputs is less than the number of inputs.
10-03-2023 18
19. Octal-to-Binary Encoder (8x3 encoder)
• It has eight inputs (one for each of the octal digits) and the three outputs that
generate the corresponding binary number. It is assumed that only one input
has a value of 1 at any given time.
Truth Table
• The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table.
10-03-2023 19
20. Octal-to-Binary Encoder (8x3 encoder)
• Output z is equal to 1, when the input octal digit is 1 or 3 or 5 or 7. Output y is 1 for
octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or7.
• These conditions can be expressed by the following output Boolean functions:
z= D1+ D3+ D5+ D7
y= D2+ D3+ D6+ D7
x= D4+ D5+ D6+ D7
• The encoder can be implemented with three OR gates.
• If two inputs are active simultaneously, the output produces an undefined combination.
• For example, if D3 and D6 are 1 simultaneously, the output of the encoder may be 111.
This does not represent either D6 or D3.
• To resolve this problem, encoder circuits must establish an input priority to ensure that
only one input is encoded.
• If we establish a higher priority for inputs with higher subscript numbers and if D3 and
D6 are 1 at the same time, the output will be 110 because D6 has higher priority than
D3.
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22. Octal-to-Binary Encoder (8x3 encoder)
• Another problem in the octal-to-binary encoder is that
an output with all 0‘s is generated when all the inputs
are 0; this output is same as when D0 is equal to 1.
• The discrepancy can be resolved by providing one more
output to indicate that atleast one input is equal to 1.
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23. Priority Encoder
• A priority encoder is an encoder circuit that includes the priority function.
• In priority encoder, if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
• In addition to the two outputs x and y, the circuit has a third output, V (valid
bit indicator).
• It is set to 1 when one or more inputs are equal to 1.
• If all inputs are 0, there is no valid input and V is equal to 0.
• The higher the subscript number, higher the priority of the input.
• Input D3, has the highest priority. So, regardless of the values of the other
inputs, when D3 is 1, the output for xy is 11.
• D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0.
• The output for D1 is generated only if higher priority inputs are 0, and so on
down the priority levels.
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24. Priority Encoder
• Truth Table:
• Although the above table has only five rows, when each don‘t care condition is
replaced first by 0 and then by 1, we obtain all 16 possible input combinations.
• For example, the third row in the table with X100 represents minterms 0100
and 1100.
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25. Priority Encoder
• The don‘t care condition is replaced by 0 and 1 as shown in the table below:
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29. Analysis and design of combinational
logic circuits:
2.4 Multiplexers
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30. Multiplexer (Data Selector)
• A multiplexer or MUX, is a combinational circuit with more than one input line,
one output line and more than one selection line.
• A multiplexer selects binary information present from one of many input lines,
depending upon the logic status of the selection inputs, and routes it to the
output line.
• Normally, there are 2^n input lines and n selection lines whose bit
combinations determine which input is selected.
• The multiplexer is often labelled as MUX in block diagrams.
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31. Multiplexer (Data Selector)
• A multiplexer is also called a data selector, since it selects one of many inputs
and steers the binary information to the output line.
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32. 2x1 Multiplexer
The circuit has two data input lines, one output line and one selection line, S.
• When S= 0, the upper AND gate is enabled and I0 has a path to the output.
• When S=1, the lower AND gate is enabled and I1 has a path to the output.
Logic Diagram Truth Table
• The multiplexer acts like an electronic switch that selects one of the two
sources.
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33. 4 x 1 Multiplexer
• A 4-to-1-line multiplexer has four (2^n) input lines, two (n) select lines and one
output line.
• It is the multiplexer consisting of four input channels and information of one of
the channels can be selected and transmitted to an output line according to
the select inputs combinations.
• Selection of one of the four input channel is possible by two selection inputs.
• Each of the four inputs I0 through I3, is applied to one input of AND gate.
• Selection lines S1 and S0 are decoded to select a particular AND gate
• The outputs of the AND gate are applied to a single OR gate that provides the
1-line output.
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34. 4 x 1 Multiplexer
Logic Diagram Truth Table
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35. 4 x 1 Multiplexer
• To demonstrate the circuit operation, consider the case when S1S0= 10.
• The AND gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2.
• The other three AND gates have atleast one input equal to 0, which makes their outputs
equal to 0.
• The OR output is now equal to the value of I2, providing a path from the selected input to
the output.
• The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0.S1‘.S0‘.
• The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1.S1‘.S0.
• The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2.S1.S0‘.
• The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3.S1.S0.
• When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
• As in decoder, multiplexers may have an enable input to control the operation of the unit.
• When the enable input is in the inactive state, the outputs are disabled, and when it is in the
active state, the circuit functions as a normal multiplexer.
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36. 8 x 1 Multiplexer
• There are 8 input lines, 1 output line and 3 select lines.
• The selection of the particular input line is controlled by three select lines
Logic Diagram Truth Table
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37. Implementation of Boolean Function
using MUX
• Any Boolean or logical expression can be easily implemented using a
multiplexer.
• If a Boolean expression has (n+1) variables, then n of these variables can be
connected to the select lines of the multiplexer.
• The remaining single variable along with constants 1 and 0 is used as the input
of the multiplexer.
• For example, if C is the single variable, then the inputs of the multiplexers are
C, C‘, 1 and 0.
• By this method any logical expression can be implemented.
• In general, a Boolean expression of (n+1) variables can be implemented using a
multiplexer with 2^n inputs.
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38. Analysis and design of combinational
logic circuits:
2.5 Demultiplexers
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39. Demultiplexer
• Demultiplex means one into many.
• Demultiplexing is the process of taking information from one
input and transmitting the same over one of several outputs.
• A demultiplexer is a combinational logic circuit that receives
information on a single input and transmits the same information
over one of several (2^n) output lines.
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40. Demultiplexer
• The circuit has one input signal, n select signals
and 2^n output signals.
• The select inputs determine to which output the
data input will be connected.
• the serial data is changed to parallel data, i.e.,
the input caused to appear on one of the n
output lines, the demultiplexer is also called a
data distributer or a serial-to-parallel converter.
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41. 1-to-4 Demultiplexer
• A 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to
Y3) and two select inputs (S1 and S0).
• The input variable Din has a path to all four outputs, but the input
information is directed to only one of the output lines.
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43. 1-to-4 Demultiplexer
• From the truth table, it is clear that the data input, Din is connected to the output
Y0, when S1= 0 and S0= 0 and the data input is connected to output Y1 when S1= 0
and S0= 1.
• Similarly, the data input is connected to output Y2 and Y3 when S1= 1 and S0= 0
and when S1= 1 and S0= 1, respectively.
• Also, from the truth table, the expression for outputs can be written as follows,
Y0= S1’S0’Din
Y1= S1’S0Din
Y2= S1S0’Din
Y3= S1S0 Din
• Now, using the above expressions, a 1-to-4 demultiplexer can be implemented
using four 3-input AND gates and two NOT gates.
• Here, the input data line Din, is connected to all the AND gates. The two select lines
S1, S0 enable only one gate at a time and the data that appears on the input line
passes through the selected gate to the associated output line.
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45. 1-to-8 Demultiplexer
• A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and
three select inputs (S2, S1 and S0).
• It distributes one input line to eight output lines based on the select inputs.
Truth table of 1-to-8 demultiplexer
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46. 1-to-8 Demultiplexer
• From the truth table, it is clear that the data input is connected with one of
the eight outputs based on the select inputs.
• Now from this truth table, the expression for eight outputs can be written as
follows:
• Using the above expressions, the logic diagram of a 1-to-8 demultiplexer can
be drawn.
• Here, the single data line, Din is connected to all the eight AND gates, but only
one of the eight AND gates will be enabled by the select input lines.
• For example, if S2S1S0= 000, then only AND gate-0 will be enabled and
thereby the data input, Din will appear at Y0.
• Similarly, the different combinations of the select inputs, the input Din will
appear at the respective output.
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48. Analysis and design of combinational
logic circuits:
2.6 Code Converters
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49. Code Converters
• A code converter is a logic circuit that changes data presented in
one type of binary code to another code of binary code. The
following are some of the most commonly used code converters:
Binary-to-Gray code
Gray-to-Binary code
BCD-to-Excess-3
Excess-3-to-BCD
Binary-to-BCD
BCD-to-binary
Gray-to-BCD
BCD-to-Gray
8 4 -2 -1 to BCD converter
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50. The 8421 BCD Code
10-03-2023 50
Converting from decimal
to 8421 BCD code
Converting from BCD to decimal
51. The Excess-3 Code
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Converting a decimal number to the excess-3 code
• The 8421 and excess-3 codes are but two of many BCD codes used in
digital electronics.
• The 8421 code is by far the most widely used BCD code.
53. The Gray Code
The important
characteristic of the
Gray code is that only
one bit changes as you
count from top to
bottom.
The Gray code cannot
be used in arithmetic
circuits.
The Gray code is used
for input and output
devices in digital
systems.
10-03-2023 53
54. The ASCII Code
The ASCII code is widely used to send information to and from
microcomputers.
The standard ASCII code is a 7-bit code used in transferring coded
information from keyboards and to computer displays and
printers.
The abbreviation ASCII (pronounced “ask-ee”) stands for the
American Standard Code for Information Interchange.
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55. 1.Binary to Gray code Converters
• The gray code is often used in digital systems because it has the advantage that
only one bit in the numerical representation changes between successive
numbers.
Truth Table
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61. Gray to Binary Code Converters
• From the K-map
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62. Gray to Binary Code Converters
• The expressions can be implemented using EX-OR gates as,
Logic diagram of 4-bit gray-to-binary converter
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63. 3.BCD –to-Excess-3 Converters
• Excess-3 is a modified form of a BCD number. The excess-3 code can be derived
from the natural BCD code by adding 3 to each coded number.
• For example, decimal 12 can be represented in BCD as 0001 0010. Now adding 3 to
each digit we get excess-3 code as 0100 0101 (12 in decimal).
• With this information the truth table for BCD to Excess-3 code converter can be
determined as,
Truth Table
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64. BCD –to-Excess-3 Converters
• From the truth table, the logic expression for the Excess-
3 code outputs can be written as,
E3= Σm (5, 6, 7, 8, 9) + Σd (10, 11, 12, 13, 14, 15)
E2= Σm (1, 2, 3, 4, 9) + Σd (10, 11, 12, 13, 14, 15)
E1= Σm (0, 3, 4, 7, 8) + Σd (10, 11, 12, 13, 14, 15)
E0= Σm (0, 2, 4, 6, 8) + Σd (10, 11, 12, 13, 14, 15)
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67. 4.BCD –to-Binary Converters
• The steps involved in the BCD-to-binary conversion process are as follows:
1. The value of each bit in the BCD number is represented by a binary equivalent
or weight.
2. All the binary weights of the bits that are 1‘s in the BCD are added.
3. The result of this addition is the binary equivalent of the BCD number.
• Two-digit decimal values ranging from 00 to 99 can be represented in BCD by
two 4-bit code groups. For example, 19 is represented as,
• The left-most four-bit group represents 10 and right-most four-bit group
represents 9. The binary representation for decimal 19 is 19 = 11001.
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81. Problem
10-03-2023 81
The minimal function that can detect a ‘divisible by 3’ 8421 BCD code digit
(representation is D8 D4 D2 D1 ) is given by_________
![SRI RAMAKRISHNA ENGINEERING COLLEGE
Presentation by
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Department of ECE
Department of Electronics and Communication Engineering
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DIGITAL LOGIC CIRCUITS](https://image.slidesharecdn.com/session2-230310134929-26be7dd0/85/SESSION-2-ppt-1-320.jpg)
