SlideShare a Scribd company logo
DIGITAL COMPUTER FUNDAMENTALS
Presented by
G.Vinothini M.sc.,M.phil.,
Department of Information Techonology,
Bon Secours College for Women,
Thanjavur.
COMBINATIONAl LOGIC CIRCUITS
Combinational logic is used in computer circuits to
perform Boolean algebra on input signals and on stored data.
Practical computer circuits normally contain a mixture of
combinational and sequential logic. For example, the part of
an arithmetic logic unit, or ALU, that does mathematical
calculations is constructed using combinational logic. Other
circuits used in computers, such as half adders, full adders, half
subtractors, full
subtractors, multiplexers, demultiplexers, encoders and decoder
s are also made by using combinational logic.
• The Add micro-operation requires registers that can hold the data and the
digital components that can perform the arithmetic addition.
• A Binary Adder is a digital circuit that performs the arithmetic sum of two
binary numbers provided with any length.
• A Binary Adder is constructed using full-adder circuits connected in
series, with the output carry from one full-adder connected to the input
carry of the next full-adder.
BINARY ADDERS:
HALF ADDERS AND FULL ADDERS:
• An adder is a digital logic circuit in electronics that
implements addition of numbers.
• Adders are classified into two types: half adder and
full adder. The half adder circuit has two inputs: A
and B, which add two input digits and generate a
carry and sum. The full adder circuit has three
inputs: A and C, which add the three input
numbers and generate a carry and sum.
BCD ADDERS:
BCD adder A 4-bit binary adder that is
capable of adding two 4-bit words having
a BCD (binary-coded decimal) format. The
result of the addition is a BCD-format 4-bit
output word, representing the decimal sum of
the addend and augend, and a carry that is
generated if this sum exceeds a decimal value
of 9.
BINARY SUBTRACTIONS:
Binary Subtraction. Binary subtraction is also
similar to that of decimal subtraction with the
difference that when 1 is subtracted from 0, it
is necessary to borrow 1 from the next higher
order bit and that bit is reduced by 1
HALF AND FULL
SUBTRACTIONS:Subtractor circuits take two binary numbers
as input and subtract one binary number
input from the other binary number input.
MULTIPLEXER (4:1) :
4x1 Multiplexer has four data inputs
I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y. The block
diagram of 4x1 Multiplexer.
1 TO 4 LINES DEMULTIPLEXER:
The input data goes to any one of the
fouroutputs at a given time for a
particular combination of select lines.
Thisdemultiplexer is also called as a 2-
to-4 demultiplexer which means that two
selectlines and 4 output lines.
A decoder is a circuit that changes a code
into a set of signals. It is called
a decoderbecause it does the reverse of
encoding, but we will begin our study of
encoders
anddecoders with decoders because they
are simpler to design.
DECODERS:
DECODERS : BCD TO DECIMAL
BCD-to-Decimal decoders include the
TTL 7442 or the CMOS 4028. Generally
a decoders output code normally has
more bits than its input code and
practical “binary decoder” circuits
include, 2-to-4, 3-to-8 and 4-to-16 line
configurations.
BCD TO SEVEN SEGMENTS:
A BCD to Seven Segment decoder is a
combinational logic circuit that accepts a
decimal digit in BCD (input) and generates
appropriate outputs for
the segments todisplay the input decimal
digit.
ENCODERS:
A simple encoder or simply an encoder in digital electronics is
a one-hot to binary converter. That is, if there are 2ⁿ input lines,
and at most only one of them will ever be high, the binary code
of this 'hot' line is produced on the n-bit output lines.
ENCODERS: 4:2 LINES
digital encoders produce outputs of 2-bit, 3-
bit or 4-bit codes depending upon the
number of data input lines. An “n-bit”
binary encoder has 2n input lines and n-bit
output lines with common types that
include4-to-2, 8-to-3 and 16-to-4 line
ENCODERS: OCTAL TO BINARY
The octal-to-binary encoder consists of eight
inputs, one for each of the eight digits, and three
outputs that generate the
corresponding binary number. It is constructed with
OR gates whose inputs can be determined from the
truth table given in Table 2. The low-order output bit z
is 1 if the input octal digit is odd.
FLOATING POINT NUMBER
SYSTEM:
The term floating point refers to the fact that
a number's radix point (decimal point, or, more commonly
in computers, binary point) can "float"; that is, it can be
placed anywhere relative to the significant digits of
thenumber.
RANGE OF STORED NUMBERS:
Number of bits Formula Range
8 2
8
- 1 0 - 255
16 2
16
- 1 0 - 65,535
24 2
24
- 1 0 - 16,777,215
32 2
32
- 1 0 - 4, 294,967,295
DCF-Combinational circuit

More Related Content

What's hot

Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
saravana kumaar
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
chauhankapil
 
Combinational logic
Combinational logicCombinational logic
Combinational logic
Ezeokafor Chibueze
 
2 bit comparator (Digital Electronics)
2 bit comparator (Digital Electronics)2 bit comparator (Digital Electronics)
2 bit comparator (Digital Electronics)
Shail Nakum
 
4-bit camparator
4-bit camparator4-bit camparator
4-bit camparator
Bilal Amjad
 
halfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUXhalfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUX
U Reshmi
 
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
Arti Parab Academics
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
Shailendra Gohil
 
Bca 2nd sem-u-1.4 digital logic circuits, digital component
Bca 2nd sem-u-1.4 digital logic circuits, digital componentBca 2nd sem-u-1.4 digital logic circuits, digital component
Bca 2nd sem-u-1.4 digital logic circuits, digital component
Rai University
 
digital logic circuits, digital component
 digital logic circuits, digital component digital logic circuits, digital component
digital logic circuits, digital component
Rai University
 
Switching theory Unit 1
Switching theory Unit 1Switching theory Unit 1
Switching theory Unit 1
SURBHI SAROHA
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
Then Murugeshwari
 
B sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lcktB sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lckt
MahiboobAliMulla
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
Hareem Aslam
 
Combinational logic circuits
Combinational logic circuitsCombinational logic circuits
Combinational logic circuits
AswiniT3
 
Combinational Logic Circuits
Combinational Logic CircuitsCombinational Logic Circuits
Combinational Logic Circuits
Prof. Swapnil V. Kaware
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
DeepikaDG1
 
Combinational logic circuits by Tahir Yasin
Combinational logic circuits by Tahir YasinCombinational logic circuits by Tahir Yasin
Combinational logic circuits by Tahir Yasin
TAHIR YASIN
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
Nabarun Chakraborty
 

What's hot (20)

Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Combinational logic
Combinational logicCombinational logic
Combinational logic
 
2 bit comparator (Digital Electronics)
2 bit comparator (Digital Electronics)2 bit comparator (Digital Electronics)
2 bit comparator (Digital Electronics)
 
4-bit camparator
4-bit camparator4-bit camparator
4-bit camparator
 
halfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUXhalfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUX
 
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
FYBSC IT Digital Electronics Unit IV Chapter I Multiplexer, Demultiplexer, AL...
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Bca 2nd sem-u-1.4 digital logic circuits, digital component
Bca 2nd sem-u-1.4 digital logic circuits, digital componentBca 2nd sem-u-1.4 digital logic circuits, digital component
Bca 2nd sem-u-1.4 digital logic circuits, digital component
 
digital logic circuits, digital component
 digital logic circuits, digital component digital logic circuits, digital component
digital logic circuits, digital component
 
Switching theory Unit 1
Switching theory Unit 1Switching theory Unit 1
Switching theory Unit 1
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
 
B sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lcktB sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lckt
 
Stld
StldStld
Stld
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Combinational logic circuits
Combinational logic circuitsCombinational logic circuits
Combinational logic circuits
 
Combinational Logic Circuits
Combinational Logic CircuitsCombinational Logic Circuits
Combinational Logic Circuits
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
 
Combinational logic circuits by Tahir Yasin
Combinational logic circuits by Tahir YasinCombinational logic circuits by Tahir Yasin
Combinational logic circuits by Tahir Yasin
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 

Similar to DCF-Combinational circuit

Logic gates
Logic gatesLogic gates
Logic gates
kajal kumari
 
Digital Logic Design
Digital Logic Design Digital Logic Design
Digital Logic Design
Vaagdevi College of Engineering
 
Digital Electronics-Unit II.pdf
Digital Electronics-Unit II.pdfDigital Electronics-Unit II.pdf
Digital Electronics-Unit II.pdf
Kannan Kanagaraj
 
Lect 1 unit 2.pdf
Lect 1 unit 2.pdfLect 1 unit 2.pdf
Lect 1 unit 2.pdf
saijalvishwakarma12
 
Chapter-04.pdf
Chapter-04.pdfChapter-04.pdf
Chapter-04.pdf
ssuserf7cd2b
 
Unit 4 combinational circuit
Unit 4 combinational circuitUnit 4 combinational circuit
Unit 4 combinational circuit
Kalai Selvi
 
Chapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSIChapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSI
Er. Nawaraj Bhandari
 
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptxDLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
SaveraAyub2
 
DLD Chapter-4.pdf
DLD Chapter-4.pdfDLD Chapter-4.pdf
DLD Chapter-4.pdf
TamiratDejene1
 
Decoder encoder
Decoder   encoderDecoder   encoder
Decoder encoder
shahzad ali
 
Encoder-and-decoder.pptx
Encoder-and-decoder.pptxEncoder-and-decoder.pptx
Encoder-and-decoder.pptx
KamranAli649587
 
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design ) CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
Sefat Ahammed Shovo
 
Chapter 5_combinational logic (EEEg4302).pdf
Chapter 5_combinational logic (EEEg4302).pdfChapter 5_combinational logic (EEEg4302).pdf
Chapter 5_combinational logic (EEEg4302).pdf
TamiratDejene1
 
Chapter 4 combinational circuit
Chapter 4 combinational circuit Chapter 4 combinational circuit
Chapter 4 combinational circuit
GulAhmad16
 
Combinational and sequential logic
Combinational and sequential logicCombinational and sequential logic
Combinational and sequential logic
Deepak John
 
Unit 3 combinational circuits
Unit 3  combinational circuitsUnit 3  combinational circuits
Unit 3 combinational circuits
AmrutaMehata
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
kusuma11
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
kusuma11
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
kusuma11
 

Similar to DCF-Combinational circuit (20)

Logic gates
Logic gatesLogic gates
Logic gates
 
Digital Logic Design
Digital Logic Design Digital Logic Design
Digital Logic Design
 
Digital Electronics-Unit II.pdf
Digital Electronics-Unit II.pdfDigital Electronics-Unit II.pdf
Digital Electronics-Unit II.pdf
 
Lect 1 unit 2.pdf
Lect 1 unit 2.pdfLect 1 unit 2.pdf
Lect 1 unit 2.pdf
 
Chapter-04.pdf
Chapter-04.pdfChapter-04.pdf
Chapter-04.pdf
 
Unit 4 combinational circuit
Unit 4 combinational circuitUnit 4 combinational circuit
Unit 4 combinational circuit
 
Chapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSIChapter 5: Cominational Logic with MSI and LSI
Chapter 5: Cominational Logic with MSI and LSI
 
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptxDLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
 
DLD Chapter-4.pdf
DLD Chapter-4.pdfDLD Chapter-4.pdf
DLD Chapter-4.pdf
 
Decoder encoder
Decoder   encoderDecoder   encoder
Decoder encoder
 
Encoder-and-decoder.pptx
Encoder-and-decoder.pptxEncoder-and-decoder.pptx
Encoder-and-decoder.pptx
 
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design ) CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
CHAPTER 6: Function of Combination Logic From Flyod ( Digital Logic Design )
 
Chapter 5_combinational logic (EEEg4302).pdf
Chapter 5_combinational logic (EEEg4302).pdfChapter 5_combinational logic (EEEg4302).pdf
Chapter 5_combinational logic (EEEg4302).pdf
 
Chapter 4 combinational circuit
Chapter 4 combinational circuit Chapter 4 combinational circuit
Chapter 4 combinational circuit
 
11.ppt
11.ppt11.ppt
11.ppt
 
Combinational and sequential logic
Combinational and sequential logicCombinational and sequential logic
Combinational and sequential logic
 
Unit 3 combinational circuits
Unit 3  combinational circuitsUnit 3  combinational circuits
Unit 3 combinational circuits
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
 
Digital electronics nandhini kusuma
Digital electronics nandhini kusumaDigital electronics nandhini kusuma
Digital electronics nandhini kusuma
 

More from vinothinisureshbabu

SYNCHRONIZATION
SYNCHRONIZATIONSYNCHRONIZATION
SYNCHRONIZATION
vinothinisureshbabu
 
Adobe page maker
Adobe page makerAdobe page maker
Adobe page maker
vinothinisureshbabu
 
Operating systems
Operating systems Operating systems
Operating systems
vinothinisureshbabu
 
Sequenential circuit-dcf
Sequenential circuit-dcfSequenential circuit-dcf
Sequenential circuit-dcf
vinothinisureshbabu
 
DCF- Logic gates and circuit
DCF- Logic gates and circuitDCF- Logic gates and circuit
DCF- Logic gates and circuit
vinothinisureshbabu
 
Digital computer fundamentals
Digital computer fundamentalsDigital computer fundamentals
Digital computer fundamentals
vinothinisureshbabu
 
Os - device management
Os - device managementOs - device management
Os - device management
vinothinisureshbabu
 
Introduction to ms access
Introduction to ms accessIntroduction to ms access
Introduction to ms access
vinothinisureshbabu
 
computer organization and architecture
computer organization and architecturecomputer organization and architecture
computer organization and architecture
vinothinisureshbabu
 
Programming in c
Programming in cProgramming in c
Programming in c
vinothinisureshbabu
 

More from vinothinisureshbabu (11)

SYNCHRONIZATION
SYNCHRONIZATIONSYNCHRONIZATION
SYNCHRONIZATION
 
Adobe page maker
Adobe page makerAdobe page maker
Adobe page maker
 
Operating systems
Operating systems Operating systems
Operating systems
 
Sequenential circuit-dcf
Sequenential circuit-dcfSequenential circuit-dcf
Sequenential circuit-dcf
 
DCF - K map
DCF - K mapDCF - K map
DCF - K map
 
DCF- Logic gates and circuit
DCF- Logic gates and circuitDCF- Logic gates and circuit
DCF- Logic gates and circuit
 
Digital computer fundamentals
Digital computer fundamentalsDigital computer fundamentals
Digital computer fundamentals
 
Os - device management
Os - device managementOs - device management
Os - device management
 
Introduction to ms access
Introduction to ms accessIntroduction to ms access
Introduction to ms access
 
computer organization and architecture
computer organization and architecturecomputer organization and architecture
computer organization and architecture
 
Programming in c
Programming in cProgramming in c
Programming in c
 

Recently uploaded

Pushing the limits of ePRTC: 100ns holdover for 100 days
Pushing the limits of ePRTC: 100ns holdover for 100 daysPushing the limits of ePRTC: 100ns holdover for 100 days
Pushing the limits of ePRTC: 100ns holdover for 100 days
Adtran
 
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
James Anderson
 
20 Comprehensive Checklist of Designing and Developing a Website
20 Comprehensive Checklist of Designing and Developing a Website20 Comprehensive Checklist of Designing and Developing a Website
20 Comprehensive Checklist of Designing and Developing a Website
Pixlogix Infotech
 
Building RAG with self-deployed Milvus vector database and Snowpark Container...
Building RAG with self-deployed Milvus vector database and Snowpark Container...Building RAG with self-deployed Milvus vector database and Snowpark Container...
Building RAG with self-deployed Milvus vector database and Snowpark Container...
Zilliz
 
RESUME BUILDER APPLICATION Project for students
RESUME BUILDER APPLICATION Project for studentsRESUME BUILDER APPLICATION Project for students
RESUME BUILDER APPLICATION Project for students
KAMESHS29
 
Communications Mining Series - Zero to Hero - Session 1
Communications Mining Series - Zero to Hero - Session 1Communications Mining Series - Zero to Hero - Session 1
Communications Mining Series - Zero to Hero - Session 1
DianaGray10
 
UiPath Test Automation using UiPath Test Suite series, part 6
UiPath Test Automation using UiPath Test Suite series, part 6UiPath Test Automation using UiPath Test Suite series, part 6
UiPath Test Automation using UiPath Test Suite series, part 6
DianaGray10
 
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
Neo4j
 
Generative AI Deep Dive: Advancing from Proof of Concept to Production
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionGenerative AI Deep Dive: Advancing from Proof of Concept to Production
Generative AI Deep Dive: Advancing from Proof of Concept to Production
Aggregage
 
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
Neo4j
 
A tale of scale & speed: How the US Navy is enabling software delivery from l...
A tale of scale & speed: How the US Navy is enabling software delivery from l...A tale of scale & speed: How the US Navy is enabling software delivery from l...
A tale of scale & speed: How the US Navy is enabling software delivery from l...
sonjaschweigert1
 
20240607 QFM018 Elixir Reading List May 2024
20240607 QFM018 Elixir Reading List May 202420240607 QFM018 Elixir Reading List May 2024
20240607 QFM018 Elixir Reading List May 2024
Matthew Sinclair
 
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
Neo4j
 
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfObservability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
Paige Cruz
 
Monitoring Java Application Security with JDK Tools and JFR Events
Monitoring Java Application Security with JDK Tools and JFR EventsMonitoring Java Application Security with JDK Tools and JFR Events
Monitoring Java Application Security with JDK Tools and JFR Events
Ana-Maria Mihalceanu
 
UiPath Test Automation using UiPath Test Suite series, part 5
UiPath Test Automation using UiPath Test Suite series, part 5UiPath Test Automation using UiPath Test Suite series, part 5
UiPath Test Automation using UiPath Test Suite series, part 5
DianaGray10
 
20240605 QFM017 Machine Intelligence Reading List May 2024
20240605 QFM017 Machine Intelligence Reading List May 202420240605 QFM017 Machine Intelligence Reading List May 2024
20240605 QFM017 Machine Intelligence Reading List May 2024
Matthew Sinclair
 
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Albert Hoitingh
 
Removing Uninteresting Bytes in Software Fuzzing
Removing Uninteresting Bytes in Software FuzzingRemoving Uninteresting Bytes in Software Fuzzing
Removing Uninteresting Bytes in Software Fuzzing
Aftab Hussain
 
Mind map of terminologies used in context of Generative AI
Mind map of terminologies used in context of Generative AIMind map of terminologies used in context of Generative AI
Mind map of terminologies used in context of Generative AI
Kumud Singh
 

Recently uploaded (20)

Pushing the limits of ePRTC: 100ns holdover for 100 days
Pushing the limits of ePRTC: 100ns holdover for 100 daysPushing the limits of ePRTC: 100ns holdover for 100 days
Pushing the limits of ePRTC: 100ns holdover for 100 days
 
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...
 
20 Comprehensive Checklist of Designing and Developing a Website
20 Comprehensive Checklist of Designing and Developing a Website20 Comprehensive Checklist of Designing and Developing a Website
20 Comprehensive Checklist of Designing and Developing a Website
 
Building RAG with self-deployed Milvus vector database and Snowpark Container...
Building RAG with self-deployed Milvus vector database and Snowpark Container...Building RAG with self-deployed Milvus vector database and Snowpark Container...
Building RAG with self-deployed Milvus vector database and Snowpark Container...
 
RESUME BUILDER APPLICATION Project for students
RESUME BUILDER APPLICATION Project for studentsRESUME BUILDER APPLICATION Project for students
RESUME BUILDER APPLICATION Project for students
 
Communications Mining Series - Zero to Hero - Session 1
Communications Mining Series - Zero to Hero - Session 1Communications Mining Series - Zero to Hero - Session 1
Communications Mining Series - Zero to Hero - Session 1
 
UiPath Test Automation using UiPath Test Suite series, part 6
UiPath Test Automation using UiPath Test Suite series, part 6UiPath Test Automation using UiPath Test Suite series, part 6
UiPath Test Automation using UiPath Test Suite series, part 6
 
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
GraphSummit Singapore | Enhancing Changi Airport Group's Passenger Experience...
 
Generative AI Deep Dive: Advancing from Proof of Concept to Production
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionGenerative AI Deep Dive: Advancing from Proof of Concept to Production
Generative AI Deep Dive: Advancing from Proof of Concept to Production
 
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
GraphSummit Singapore | Neo4j Product Vision & Roadmap - Q2 2024
 
A tale of scale & speed: How the US Navy is enabling software delivery from l...
A tale of scale & speed: How the US Navy is enabling software delivery from l...A tale of scale & speed: How the US Navy is enabling software delivery from l...
A tale of scale & speed: How the US Navy is enabling software delivery from l...
 
20240607 QFM018 Elixir Reading List May 2024
20240607 QFM018 Elixir Reading List May 202420240607 QFM018 Elixir Reading List May 2024
20240607 QFM018 Elixir Reading List May 2024
 
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
GraphSummit Singapore | Graphing Success: Revolutionising Organisational Stru...
 
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfObservability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdf
 
Monitoring Java Application Security with JDK Tools and JFR Events
Monitoring Java Application Security with JDK Tools and JFR EventsMonitoring Java Application Security with JDK Tools and JFR Events
Monitoring Java Application Security with JDK Tools and JFR Events
 
UiPath Test Automation using UiPath Test Suite series, part 5
UiPath Test Automation using UiPath Test Suite series, part 5UiPath Test Automation using UiPath Test Suite series, part 5
UiPath Test Automation using UiPath Test Suite series, part 5
 
20240605 QFM017 Machine Intelligence Reading List May 2024
20240605 QFM017 Machine Intelligence Reading List May 202420240605 QFM017 Machine Intelligence Reading List May 2024
20240605 QFM017 Machine Intelligence Reading List May 2024
 
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
 
Removing Uninteresting Bytes in Software Fuzzing
Removing Uninteresting Bytes in Software FuzzingRemoving Uninteresting Bytes in Software Fuzzing
Removing Uninteresting Bytes in Software Fuzzing
 
Mind map of terminologies used in context of Generative AI
Mind map of terminologies used in context of Generative AIMind map of terminologies used in context of Generative AI
Mind map of terminologies used in context of Generative AI
 

DCF-Combinational circuit

  • 1. DIGITAL COMPUTER FUNDAMENTALS Presented by G.Vinothini M.sc.,M.phil., Department of Information Techonology, Bon Secours College for Women, Thanjavur.
  • 2. COMBINATIONAl LOGIC CIRCUITS Combinational logic is used in computer circuits to perform Boolean algebra on input signals and on stored data. Practical computer circuits normally contain a mixture of combinational and sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does mathematical calculations is constructed using combinational logic. Other circuits used in computers, such as half adders, full adders, half subtractors, full subtractors, multiplexers, demultiplexers, encoders and decoder s are also made by using combinational logic.
  • 3. • The Add micro-operation requires registers that can hold the data and the digital components that can perform the arithmetic addition. • A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers provided with any length. • A Binary Adder is constructed using full-adder circuits connected in series, with the output carry from one full-adder connected to the input carry of the next full-adder. BINARY ADDERS:
  • 4. HALF ADDERS AND FULL ADDERS: • An adder is a digital logic circuit in electronics that implements addition of numbers. • Adders are classified into two types: half adder and full adder. The half adder circuit has two inputs: A and B, which add two input digits and generate a carry and sum. The full adder circuit has three inputs: A and C, which add the three input numbers and generate a carry and sum.
  • 5. BCD ADDERS: BCD adder A 4-bit binary adder that is capable of adding two 4-bit words having a BCD (binary-coded decimal) format. The result of the addition is a BCD-format 4-bit output word, representing the decimal sum of the addend and augend, and a carry that is generated if this sum exceeds a decimal value of 9.
  • 6. BINARY SUBTRACTIONS: Binary Subtraction. Binary subtraction is also similar to that of decimal subtraction with the difference that when 1 is subtracted from 0, it is necessary to borrow 1 from the next higher order bit and that bit is reduced by 1
  • 7. HALF AND FULL SUBTRACTIONS:Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input.
  • 8. MULTIPLEXER (4:1) : 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block diagram of 4x1 Multiplexer.
  • 9. 1 TO 4 LINES DEMULTIPLEXER: The input data goes to any one of the fouroutputs at a given time for a particular combination of select lines. Thisdemultiplexer is also called as a 2- to-4 demultiplexer which means that two selectlines and 4 output lines.
  • 10. A decoder is a circuit that changes a code into a set of signals. It is called a decoderbecause it does the reverse of encoding, but we will begin our study of encoders anddecoders with decoders because they are simpler to design. DECODERS:
  • 11. DECODERS : BCD TO DECIMAL BCD-to-Decimal decoders include the TTL 7442 or the CMOS 4028. Generally a decoders output code normally has more bits than its input code and practical “binary decoder” circuits include, 2-to-4, 3-to-8 and 4-to-16 line configurations.
  • 12. BCD TO SEVEN SEGMENTS: A BCD to Seven Segment decoder is a combinational logic circuit that accepts a decimal digit in BCD (input) and generates appropriate outputs for the segments todisplay the input decimal digit.
  • 13. ENCODERS: A simple encoder or simply an encoder in digital electronics is a one-hot to binary converter. That is, if there are 2ⁿ input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit output lines.
  • 14. ENCODERS: 4:2 LINES digital encoders produce outputs of 2-bit, 3- bit or 4-bit codes depending upon the number of data input lines. An “n-bit” binary encoder has 2n input lines and n-bit output lines with common types that include4-to-2, 8-to-3 and 16-to-4 line
  • 15. ENCODERS: OCTAL TO BINARY The octal-to-binary encoder consists of eight inputs, one for each of the eight digits, and three outputs that generate the corresponding binary number. It is constructed with OR gates whose inputs can be determined from the truth table given in Table 2. The low-order output bit z is 1 if the input octal digit is odd.
  • 16. FLOATING POINT NUMBER SYSTEM: The term floating point refers to the fact that a number's radix point (decimal point, or, more commonly in computers, binary point) can "float"; that is, it can be placed anywhere relative to the significant digits of thenumber.
  • 17.
  • 18. RANGE OF STORED NUMBERS: Number of bits Formula Range 8 2 8 - 1 0 - 255 16 2 16 - 1 0 - 65,535 24 2 24 - 1 0 - 16,777,215 32 2 32 - 1 0 - 4, 294,967,295