Memory organization is a classification of memory or a class presentation of memory in which the memory is categorized or sub divided according to their work.
Control Units : Microprogrammed and Hardwired:control unitabdosaidgkv
The document discusses control units in CPUs. There are two main methods for implementing control units: hardwired and microprogrammed. A hardwired control unit generates control signals through circuitry using logic gates, while a microprogrammed control unit generates control signals by executing a stored microprogram. Overall, hardwired control units are faster but less flexible, while microprogrammed control units are slower but more flexible and modifiable.
In these slides the registration organization and stack organization have discussed in detail. Stack organization is discussed with the aid of animation to let the user understand it in a better and easy way.
An instruction tells the CPU to perform an operation by storing bits of code in memory that are read into the instruction register. Instructions are executed in three phases: fetching the instruction from memory, decoding what operation it specifies, and then executing it, which may involve reading an effective address or performing an input/output operation. Memory reference, register reference, and input/output instructions allow the CPU to access different parts of the computer's architecture during the instruction cycle.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
The document discusses address sequencing in a microprogram control unit. It begins by defining key terms like control address register, which stores the initial address of the first microinstruction. It then explains that the next address generator is responsible for selecting the next address from control memory based on the current microinstruction. Microinstructions are stored in control memory in groups that make up routines corresponding to each machine instruction. The document also discusses control memory, hardwired control vs microprogrammed control, and examples of next address generation and status bits.
Interrupts allow input/output devices to alert the processor when they are ready. When an interrupt request occurs, the processor saves its context and jumps to an interrupt service routine. It then acknowledges the interrupt and restores its context before returning to the original instruction. Processors have mechanisms for prioritizing interrupts and enabling/disabling them to avoid infinite loops or unintended requests.
Control Units : Microprogrammed and Hardwired:control unitabdosaidgkv
The document discusses control units in CPUs. There are two main methods for implementing control units: hardwired and microprogrammed. A hardwired control unit generates control signals through circuitry using logic gates, while a microprogrammed control unit generates control signals by executing a stored microprogram. Overall, hardwired control units are faster but less flexible, while microprogrammed control units are slower but more flexible and modifiable.
In these slides the registration organization and stack organization have discussed in detail. Stack organization is discussed with the aid of animation to let the user understand it in a better and easy way.
An instruction tells the CPU to perform an operation by storing bits of code in memory that are read into the instruction register. Instructions are executed in three phases: fetching the instruction from memory, decoding what operation it specifies, and then executing it, which may involve reading an effective address or performing an input/output operation. Memory reference, register reference, and input/output instructions allow the CPU to access different parts of the computer's architecture during the instruction cycle.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
The document discusses address sequencing in a microprogram control unit. It begins by defining key terms like control address register, which stores the initial address of the first microinstruction. It then explains that the next address generator is responsible for selecting the next address from control memory based on the current microinstruction. Microinstructions are stored in control memory in groups that make up routines corresponding to each machine instruction. The document also discusses control memory, hardwired control vs microprogrammed control, and examples of next address generation and status bits.
Interrupts allow input/output devices to alert the processor when they are ready. When an interrupt request occurs, the processor saves its context and jumps to an interrupt service routine. It then acknowledges the interrupt and restores its context before returning to the original instruction. Processors have mechanisms for prioritizing interrupts and enabling/disabling them to avoid infinite loops or unintended requests.
Booth's algorithm is a method for multiplying two signed or unsigned integers in binary representation more efficiently than straightforward algorithms. It uses fewer additions and subtractions by representing the multiplicand as 2's complement numbers. The algorithm loads the multiplicand and multiplier into registers, initializes a third register to 0, and performs bitwise shifts and arithmetic operations (addition/subtraction of the multiplicand) on the registers based on the values of bits from the multiplier. This process builds up the product one bit at a time in a third register.
This document discusses computer arithmetic and floating point representation. It begins with an introduction to computer arithmetic and covers topics like addition, subtraction, multiplication, division and their algorithms. It then discusses floating point representation which uses scientific notation to represent real numbers. Key aspects covered include single and double precision formats, normalized and denormalized numbers, overflow and underflow, and biased exponent representation. Examples are provided to illustrate floating point addition and multiplication. The document also discusses floating point instructions in MIPS and the need for accurate arithmetic in floating point operations.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
General register organization (computer organization)rishi ram khanal
This document discusses the organization of a CPU and its registers. It includes tables that encode the register selection fields and ALU operations. It also provides examples of micro-operations for the CPU, showing the register selections, ALU operations, and control words. Key registers discussed include the accumulator, instruction register, address register, and program counter.
Memory is organized in a hierarchy with different levels providing trade-offs between speed and cost.
- Cache memory sits between the CPU and main memory for fastest access.
- Main memory (RAM) is where active programs and data reside and is faster than auxiliary memory but more expensive.
- Auxiliary memory (disks, tapes) provides backup storage and is slower than main memory but larger and cheaper.
Virtual memory manages this hierarchy through address translation techniques like paging that map virtual addresses to physical locations, allowing programs to access more memory than physically available. When data is needed from auxiliary memory a page fault occurs and page replacement algorithms determine what data to remove from main memory.
A datapath is a collection of functional units like ALUs and registers that perform data processing along with a control unit to form the CPU. There are three general steps to datapath design: 1) determine instruction classes, 2) design components for each class, and 3) combine the components. Common datapaths include load/store which uses memory addressing and branch/jump which uses instruction addressing. The ALU performs operations like addition and subtraction. The main control unit identifies instruction fields and controls the datapath. Multiplication can be done with combinational or sequential circuits while division similarly uses subtraction and shifting. Floating point uses separate exponent and mantissa fields.
Direct memory access (DMA) allows certain hardware subsystems to access computer memory independently of the central processing unit (CPU). During DMA transfer, the CPU is idle while an I/O device reads from or writes directly to memory using a DMA controller. This improves data transfer speeds as the CPU does not need to manage each memory access and can perform other tasks. DMA is useful when CPU cannot keep up with data transfer speeds or needs to work while waiting for a slow I/O operation to complete.
IPC allows processes to communicate and share resources. There are several common IPC mechanisms, including message passing, shared memory, semaphores, files, signals, sockets, message queues, and pipes. Message passing involves establishing a communication link and exchanging fixed or variable sized messages using send and receive operations. Shared memory allows processes to access the same memory area. Semaphores are used to synchronize processes. Files provide durable storage that outlives individual processes. Signals asynchronously notify processes of events. Sockets enable two-way point-to-point communication between processes. Message queues allow asynchronous communication where senders and receivers do not need to interact simultaneously. Pipes create a pipeline between processes by connecting standard streams.
This method of checking the signal in the system for processing is called Polling Method. In this method, the problem is that the processor has to waste number of clock cycles just for checking the signal in the system, by this processor will become busy unnecessarily. If any signal came for the process, processor will take some time to process the signal due to the polling process in action. So system performance also will be degraded and response time of the system will also decrease.
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
The document discusses instruction execution in a computer processor. It describes how a processor executes instructions by fetching them from memory using the program counter. The instruction is placed in the instruction register and decoded by the control unit. The control unit then selects components like the ALU to carry out operations. Common components involved in instruction execution are the program counter, memory address register, instruction register, memory buffer register, control unit, arithmetic logic unit, and accumulator. The execution cycle involves fetching the instruction from memory address, decoding it, and then executing the instruction.
The document discusses addressing modes in computers. It defines addressing modes as the different ways of specifying the location of an operand in an instruction. It describes 10 common addressing modes including implied, immediate, register, register indirect, auto increment/decrement, direct, indirect, relative, indexed, and base register addressing modes. It provides examples of instructions for each addressing mode and explains how the effective address is calculated. Addressing modes allow for versatility in programming through features like pointers, loop counters, data indexing, and program relocation while reducing the number of bits needed in instruction addresses.
(Ref : Computer System Architecture by Morris Mano 3rd edition) : Microprogrammed Control unit, micro instructions, micro operations, symbolic and binary microprogram.
The Pentium processor introduced in 1993 features a superscalar architecture that allows multiple instructions to be executed simultaneously. It has separate 8KB instruction and data caches and a 64-bit data bus. The Pentium uses dynamic branch prediction and out-of-order execution to further improve performance through superscalar design.
1) Data transfer instructions move data between processor registers and memory without changing the data. Common instructions include load, store, move, exchange, input, and output.
2) Data manipulation instructions perform arithmetic, logical, and bitwise operations on data to provide computational capabilities. Examples include add, subtract, multiply, divide, and, or, xor.
3) Program control instructions alter the program flow by branching, jumping, calling subroutines, handling interrupts, and returning from subroutines. Status bits track results of operations.
The instruction cycle describes the process a computer follows to execute each machine language instruction. It involves 4 phases: 1) Fetch - the instruction is fetched from memory and placed in the instruction register. 2) Decode - the instruction is analyzed and decoded. 3) Execute - the processor executes the instruction by performing the specified operation. 4) The program counter is then incremented to point to the next instruction, and the cycle repeats. Each phase involves transferring data between the program counter, instruction register, memory, and other components via a common bus under the control of a timing unit. The instruction specifies the operation to be performed, such as a memory reference, register operation, or I/O access.
Basic Computer Organization and Design
.....................................................................
The basic computer design represents all of the major concepts in CPU design without overwhelming students with the complexity of a modern commercial CPU.
An instruction format specifies an operation code and operands. There are three main types of instruction formats: three address instructions specify memory addresses for two operands and one destination; two address instructions specify two memory locations or registers with the destination assumed to be the first operand; and one address instructions use a single accumulator register for all data manipulation. Addressing modes further specify how the address field of an instruction is interpreted to determine the effective address of an operand. Common addressing modes include immediate, register, register indirect, auto-increment/decrement, direct, indirect, relative, indexed, and base register addressing.
A database is simply an organized collection of related data, typically stored on disk, and accessible by possibly many concurrent users. Databases are generally separated into application areas.
A Database Management System (DBMS) is a set of programs that manages any number of databases.
Booth's algorithm is a method for multiplying two signed or unsigned integers in binary representation more efficiently than straightforward algorithms. It uses fewer additions and subtractions by representing the multiplicand as 2's complement numbers. The algorithm loads the multiplicand and multiplier into registers, initializes a third register to 0, and performs bitwise shifts and arithmetic operations (addition/subtraction of the multiplicand) on the registers based on the values of bits from the multiplier. This process builds up the product one bit at a time in a third register.
This document discusses computer arithmetic and floating point representation. It begins with an introduction to computer arithmetic and covers topics like addition, subtraction, multiplication, division and their algorithms. It then discusses floating point representation which uses scientific notation to represent real numbers. Key aspects covered include single and double precision formats, normalized and denormalized numbers, overflow and underflow, and biased exponent representation. Examples are provided to illustrate floating point addition and multiplication. The document also discusses floating point instructions in MIPS and the need for accurate arithmetic in floating point operations.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
General register organization (computer organization)rishi ram khanal
This document discusses the organization of a CPU and its registers. It includes tables that encode the register selection fields and ALU operations. It also provides examples of micro-operations for the CPU, showing the register selections, ALU operations, and control words. Key registers discussed include the accumulator, instruction register, address register, and program counter.
Memory is organized in a hierarchy with different levels providing trade-offs between speed and cost.
- Cache memory sits between the CPU and main memory for fastest access.
- Main memory (RAM) is where active programs and data reside and is faster than auxiliary memory but more expensive.
- Auxiliary memory (disks, tapes) provides backup storage and is slower than main memory but larger and cheaper.
Virtual memory manages this hierarchy through address translation techniques like paging that map virtual addresses to physical locations, allowing programs to access more memory than physically available. When data is needed from auxiliary memory a page fault occurs and page replacement algorithms determine what data to remove from main memory.
A datapath is a collection of functional units like ALUs and registers that perform data processing along with a control unit to form the CPU. There are three general steps to datapath design: 1) determine instruction classes, 2) design components for each class, and 3) combine the components. Common datapaths include load/store which uses memory addressing and branch/jump which uses instruction addressing. The ALU performs operations like addition and subtraction. The main control unit identifies instruction fields and controls the datapath. Multiplication can be done with combinational or sequential circuits while division similarly uses subtraction and shifting. Floating point uses separate exponent and mantissa fields.
Direct memory access (DMA) allows certain hardware subsystems to access computer memory independently of the central processing unit (CPU). During DMA transfer, the CPU is idle while an I/O device reads from or writes directly to memory using a DMA controller. This improves data transfer speeds as the CPU does not need to manage each memory access and can perform other tasks. DMA is useful when CPU cannot keep up with data transfer speeds or needs to work while waiting for a slow I/O operation to complete.
IPC allows processes to communicate and share resources. There are several common IPC mechanisms, including message passing, shared memory, semaphores, files, signals, sockets, message queues, and pipes. Message passing involves establishing a communication link and exchanging fixed or variable sized messages using send and receive operations. Shared memory allows processes to access the same memory area. Semaphores are used to synchronize processes. Files provide durable storage that outlives individual processes. Signals asynchronously notify processes of events. Sockets enable two-way point-to-point communication between processes. Message queues allow asynchronous communication where senders and receivers do not need to interact simultaneously. Pipes create a pipeline between processes by connecting standard streams.
This method of checking the signal in the system for processing is called Polling Method. In this method, the problem is that the processor has to waste number of clock cycles just for checking the signal in the system, by this processor will become busy unnecessarily. If any signal came for the process, processor will take some time to process the signal due to the polling process in action. So system performance also will be degraded and response time of the system will also decrease.
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
The document discusses instruction execution in a computer processor. It describes how a processor executes instructions by fetching them from memory using the program counter. The instruction is placed in the instruction register and decoded by the control unit. The control unit then selects components like the ALU to carry out operations. Common components involved in instruction execution are the program counter, memory address register, instruction register, memory buffer register, control unit, arithmetic logic unit, and accumulator. The execution cycle involves fetching the instruction from memory address, decoding it, and then executing the instruction.
The document discusses addressing modes in computers. It defines addressing modes as the different ways of specifying the location of an operand in an instruction. It describes 10 common addressing modes including implied, immediate, register, register indirect, auto increment/decrement, direct, indirect, relative, indexed, and base register addressing modes. It provides examples of instructions for each addressing mode and explains how the effective address is calculated. Addressing modes allow for versatility in programming through features like pointers, loop counters, data indexing, and program relocation while reducing the number of bits needed in instruction addresses.
(Ref : Computer System Architecture by Morris Mano 3rd edition) : Microprogrammed Control unit, micro instructions, micro operations, symbolic and binary microprogram.
The Pentium processor introduced in 1993 features a superscalar architecture that allows multiple instructions to be executed simultaneously. It has separate 8KB instruction and data caches and a 64-bit data bus. The Pentium uses dynamic branch prediction and out-of-order execution to further improve performance through superscalar design.
1) Data transfer instructions move data between processor registers and memory without changing the data. Common instructions include load, store, move, exchange, input, and output.
2) Data manipulation instructions perform arithmetic, logical, and bitwise operations on data to provide computational capabilities. Examples include add, subtract, multiply, divide, and, or, xor.
3) Program control instructions alter the program flow by branching, jumping, calling subroutines, handling interrupts, and returning from subroutines. Status bits track results of operations.
The instruction cycle describes the process a computer follows to execute each machine language instruction. It involves 4 phases: 1) Fetch - the instruction is fetched from memory and placed in the instruction register. 2) Decode - the instruction is analyzed and decoded. 3) Execute - the processor executes the instruction by performing the specified operation. 4) The program counter is then incremented to point to the next instruction, and the cycle repeats. Each phase involves transferring data between the program counter, instruction register, memory, and other components via a common bus under the control of a timing unit. The instruction specifies the operation to be performed, such as a memory reference, register operation, or I/O access.
Basic Computer Organization and Design
.....................................................................
The basic computer design represents all of the major concepts in CPU design without overwhelming students with the complexity of a modern commercial CPU.
An instruction format specifies an operation code and operands. There are three main types of instruction formats: three address instructions specify memory addresses for two operands and one destination; two address instructions specify two memory locations or registers with the destination assumed to be the first operand; and one address instructions use a single accumulator register for all data manipulation. Addressing modes further specify how the address field of an instruction is interpreted to determine the effective address of an operand. Common addressing modes include immediate, register, register indirect, auto-increment/decrement, direct, indirect, relative, indexed, and base register addressing.
A database is simply an organized collection of related data, typically stored on disk, and accessible by possibly many concurrent users. Databases are generally separated into application areas.
A Database Management System (DBMS) is a set of programs that manages any number of databases.
In 80386 Microprocessor , the physical memory is organized as a sequence bytes.
The model of memory organization seen by applications programmers is determined by systems-software designers.
An array is the data structure that contains a collection of similar type data elements and It is better and convenient way of storing the data of same data type with same size.
The document provides an overview of the TCP/IP protocol suite. It describes how TCP/IP uses a layered approach with different protocols at each layer to handle different aspects of communication. The layers include the physical layer, data link layer, network layer, transport layer, and application layer. Each layer provides a specific functionality and works together with the other layers to enable communication between devices on the internet.
State-Of-The Art Machine Learning Algorithms and How They Are Affected By Nea...inside-BigData.com
Machine learning algorithms are increasingly being used across many domains and are affected by technology trends. Deep learning techniques have achieved human-level performance in tasks like speech recognition and face recognition. Training machine learning models requires massive parallelism and computational resources that are well-suited to GPU and multi-core architectures. Reduced precision computation can accelerate training but may impact convergence. Specialized hardware continues to evolve for both training and inference.
This document discusses Remote Direct Memory Access (RDMA) and how it allows for more efficient data transfer between applications compared to traditional methods. It explains that RDMA bypasses the operating system by allowing applications and network cards to directly exchange data through a shared memory area called a Virtual Interface. The sender application fills this shared memory with data, and the network card then directly transmits it without CPU intervention, reducing latency and increasing throughput. RDMA is enabled by technologies like Virtual Interface Architecture and hardware such as Fibre Channel and Ethernet network interface cards that support it.
Whenever we need to transfer XML file, we need to ensure about its quality and its error-freeness. This can be achieved through DTD (Document Type Definition).
DHCP was created by the Dynamic Host Configuration Working Group of the Internet Engineering Task Force. It is a method for assigning Internet Protocol (IP) addresses permanently or to individual computers in an organization’s network.
High speed computing was implemented in supercomputer for scientific research. HPC clusters provide the most efficient, flexible, cost effective computing environments for HPC simulations.
The document discusses maxima and minima of functions of two independent variables. It defines a relative minimum or maximum point of a function f(x,y) and explains how to determine the stationary points by simultaneously solving the partial derivatives of f with respect to x and y. The working rule outlined finds the extreme values by checking the signs of the second order partial derivatives at the stationary points. An example of finding the maxima of f(x,y)=x^2+y^2+12x+22y is provided to illustrate the process.
This document discusses computer system architecture and memory hierarchies. It covers three key points:
1. Computer systems use a memory hierarchy with multiple tiers like registers, caches, main memory, and secondary storage to meet the high bandwidth demands of processors. This takes advantage of locality of reference by storing frequently used data in faster but smaller memory.
2. Each level in the memory hierarchy has trade-offs between speed, cost, size, and persistence. For example, caches are faster but smaller than main memory, and disks are slower but larger and more persistent than RAM.
3. Caching is a general principle that can be applied between any two levels of memory, like buffer caches between RAM and disks, to
Wireless sensor network is a distributed system consisting of a large number of low-cost wireless sensor nodes equipped with a small processor with limited memory, RF trans-receiver, antenna, sensing elements and are powered with small batteries and solar cells.
The process of reducing a given DFA to its minimal form is called as minimization of DFA. DFA minimization is also called as Optimization of DFA and uses partitioning algorithm.
NLP is a tool for computers to analyse, comprehend, and derive meaning from natural language in an intelligent and useful way. Natural language processing helps computers communicate with humans in their own language and scales other language-related tasks.
Smart computing involves connecting devices like appliances, phones, and infrastructure to the internet and each other. This allows them to become aware of their environment and each other's status, enabling new functionalities. For example, a smart fridge can sense when supplies are low and automatically place an order. Key aspects of smart computing include awareness, analysis of data, evaluating alternatives, taking appropriate actions, and ensuring accountability of the system. While smart computing provides benefits, it also raises issues regarding data privacy, security, and standardization that must be addressed.
As a student, you should be developing work ethic and etiquette skill sets to prepare you for the work environment. Developing professional habits and manners is more important now than ever before.
Writing skills include all the knowledge and abilities related to expressing yourself through the written word. Here you can find activities to practise your writing skills.
Professional communication in written form requires skill and expertise. And whether you're starting a new job, introducing yourself at a networking event or pitching for new work, here are some things to consider ...
Servlets work on the server-side. Servlets are capable of handling complex requests obtained from the web-server. There are many (competing) server-side technologies available: Java-based (servlet, JSP, JSF, Struts, Spring, Hibernate), ASP, PHP, CGI Script, and many others.
This document discusses Jenkins, an open source automation server that can be used to automate tasks related to building, testing, and deploying software. It describes how Jenkins can be installed via native packages, Docker, or by running its Java files. The document also explains what a Jenkins pipeline is and provides examples of declarative and scripted pipeline syntax to define build, test, and deploy stages. Finally, it discusses concepts like nodes, stages, and steps that are used in continuous development with Jenkins.
Cloud computing enables ubiquitous and on-demand access to shared pools of configurable computing resources. It is composed of essential characteristics like rapid provisioning and release of resources with minimal management effort. There are three main service models - Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). The document also discusses the different types of cloud including public, private, and hybrid clouds. Using cloud computing provides advantages to enterprises like setting up a virtual office and saving costs compared to purchasing their own systems and equipment.
Data science, Know as data-driven science, is also an interdisciplinary field of scientific methods, processes, algorithms, and systems to extract knowledge or insights from data in various forms, either structured or unstructured, similar to data mining.
The document discusses the different types of artificial intelligence. It describes memory-less AI, limited memory AI, theory of mind AI, and self-consciousness AI based on how closely they can simulate human intelligence. It also outlines narrow or weak AI, general or strong AI, and super AI based on the scope of tasks they can perform. Memory-less AI can respond to predefined inputs without learning, while limited memory AI can learn from experiences. Current research is focused on developing general AI that can mimic human intelligence and theory of mind AI that understands emotions and beliefs.
All these acronyms are often loosely used in the field of technology. It is important to understand that all these acronyms are part of Artificial Intelligence (AI) umbrella.
Sentiment Analysis has become a hot-trend topic of scientific and market research; it is a natural language processing technique used to determine whether data is positive, negative or neutral.
The theory of computation is a branch of computer science and mathematics combined. It deals with how efficiently problems can be solved on a model of computation, using an algorithm.
The popular object-oriented languages are Java, C#, PHP, Python, C++, etc. The main aim of object-oriented programming is to implement real-world entities.
Power BI is a business analytics service by Microsoft. BI
Microsoft Power BI is a suite of business intelligence (BI), reporting, and data visualization products and services for individuals and teams. You can access your data from anywhere with the Power BI app.
AVL tree Named after their inventor Adelson, Velski & Landis, is a self-balancing Binary Search Tree (BST) where the difference between heights of left and right subtrees cannot be more than one for all nodes.
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1. Memory Organization
Prof. Bailappa. Bhovi
Department of Computer Engineering
Hope Foundation’s
International Institute of Information Technology, (I²IT).
www.isquareit.edu.in
Tel - +91 20 22933441
2. UNIT-2:
Internal memory organization
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
3. Memory- Basic Concepts
• Data transfer between the processor and the memory takes
place through the two registers
– MAR and MBR or MDR
• MAR: The address from which data has to be read/write from
memory
• MBR: The data contents send by memory after supplying
address by MAR
• Memory Speed measurement
– Memory Access Time
– Memory Cycle Time
• Memory cycle time(Access time + Recovery time )
– Memory Cycle time for Semiconductor memories ranges 10
to 100 ns
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
4. Semiconductor Memory Types
Memory Type Category Erasure
Write
Mechanism
Volatility
Random-access
memory (RAM)
Read-write
memory
Electrically,
byte-level
Electrically Volatile
Read-only
memory (ROM) Read-only
memory
Not possible
Masks
Nonvolatile
Programmable
ROM (PROM)
Electrically
Erasable PROM
(EPROM)
Read-mostly
memory
UV light, chip-
level
Electrically
Erasable PROM
(EEPROM)
Electrically,
byte-level
Flash memory
Electrically,
block-level
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
5. Static RAM
• Memories that consists of circuits capable of
retaining their state as long as power is applied
• Bits stored as on/off switches
• Complex construction (density less)
so larger per bit and more expensive
• Faster operations, used for cache memory
Dynamic RAM
• Bits stored as charge in capacitors charges leak
so need refreshing even when powered
• Simpler construction
• Smaller per bit so less expensive
• Address line active when bit read or written
• Slower operations, used for main memory
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
6. Memory Chip Organization
One dimensional Selection method
Each row of memory cell(array of memory cells) forms one word of memory
Toaddress this mem,a decoder is reqd.Each location can be identified using A0-A3 bits.
For any location, its corresponding data can be identified at b0-b7 data lines
Pins reqd for memory: 4(address lines) + 8 (data lines)+1(CS)+1(R/W)+2(Vcc ,Gnd)=16
16 rows X 8 columns = 128 bits.
8 bit/chip organization
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
7. Two dimensional Selection method
• Memory organised as matrix of cells, each of which stores a bit
• A particular cell is selected using row and column decoder
• Row decoder selects a particular row
• Column decoder selects a particular Column
• Cheaper to implement
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
8. Organization of a 1K 1 Memory Chip
(Two dimensional Selection method )
Pins reqd for memory: 10(address lines) + 1 (data line)+1(CS)+1(R/W)+2(Vcc,Gnd)=15
This design is called 1 bit/chip organization (more preferred )
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
9. Memory Organization Issues
• A 16Mbit chip can be organized as 1M of 16 bit words (One dimension Selection method )
i.e. 1M x 16 = 220 x 16 (20 address lines+16 datalines)
=36 pins require to address and data + 4 pins (R/W, CS, PS, G)=40
• It can be organized as 4K x 512 x 8 (Two and half dimension Selection method )
i.e. 4k rows X 512 columns X 8(each column contains 8 bits)
=(12+9) address lines+ 8 data lines
=29 pins are required to address and data + 4 pins(R/W, CS, PS, G)=33
• It can be organized as 2048 x 2048 x 4 bit array(Two and half dimension Selection method )
e. 2k rows X 2k columns X 4(each column contains 4 bits)
=(11+11) address lines+ 4 data lines
=26 pins are required to address and data + 4 pins(R/W, CS, PS, G)= 30
• Row address and column address can be multiplexed
• Same 11 lines can be utilised for representing row as well as columns
• 11 pins to address (211=2048) + 4 pins for data output + 4 pins = 19 pins
• Adding one more pin doubles range of values .(capacity increase 4 times)
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
10. 16 Mbit DRAM Organization
Row decoder- Toselect a row from 2k rows
RAS-Row address selector ,CAS – Column address selector
• On 11 bit address lines,1st row address will appear so that row is identified
• Next on same 11 bit address lines, column address will appear so that column is identified
• Thus location once identified, can transfer its 4 bits to D1-D4 th’ Data o/p buffer for Read opn
• And for a write opn D1-D4 has data which is transferred th’ i/p buffer to identified location
• Adv: Pins reduced to half ,Disadv : More time
2048 x 2048 x 4 = 16Mb (Two and half dimension
Selection method )
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
11. Synchronous DRAM (SDRAM)
• Synchronized with processor clock
• After Read command, data appears after a latency of 2 clock pulses
• This 2 clk cycle wait can be utilized by the processor for activities
that does not need the system bus, e.g. ALU operations
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
12. DDR SDRAM Read Timing
• Dual Data rate(DDR) :Each cycle provides 2 bytes of data
• Data transfer rate double as compared to SDRAM
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
13. External memory
• Semiconductor memory can not be used to
store large amount of information or data
– Due to high per bit cost of it!
• Large storage requirements is full filled by
– Magnetic disks, Optical disks and Magnetic tapes
– Called as secondary storage
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
14. Disk Connection to the System Bus
• Disk controller acts as a interface between system bus and the
disk drive (handles the speed or data transfer rate mismatch)
• Single disk controller can control more than 1 disk
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
15. Data Organization on Disk
• Hard disk divided into tracks and sectors
• Concentric rings called tracks
– Gaps between tracks
– Same number of bits per track
– Constant angular velocity
• Tracks divided into sectors
• Minimum block size is one sector-512
bytes can be read/written at a time
• Individual tracks and sectors addressable
• For reading particular info, the head has
to move desired track and then the disk
has to rotate so that desired sector
comes under the head
• Direct + sequential access method
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
16. Multi Zone Recording Disks
Single – zone recording disc Multi Zone Recording Disks
• Linear distance of innermost track is less than
that of outermost track
• Density of bits more in inner sectors/tracks.
• For outer tracks we are wasting recording space
in CAV(Constant angular velocity ) system
• Solution : Multi Zone Recording Disks
• Better space utilization
• Linear length of sector is same
• More sectors as we go outwards
• For each zone the recording/reading
speed will be different
i.e. Zone wise velocity will be different
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
17. Multiple Platters Tracks and Cylinders
C
y
l
i
n
d
e
r
• For each surface separate head is there
• Set of tracks having same relative distance w.r.t center form a cylinder
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
18. Capacity
• Capacity generally express in units of gigabytes (GB),
where 1 GB =10^9 Byte
• Capacity is determined by these technology factors:
– Recording density (bits/inch): number of bits that can be
squeezed into a 1 inch segment of a track.
– Track density (tracks/inch): number of tracks that can be
squeezed into a 1 inch radial segment.
– Areal density (bits/sq.inch): product of recording and track
density.
• Modern disks partition tracks into disjoint
subsets called recording zones(multiple zone
disc)
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
19. Computing Disk Capacity
• Capacity =(# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x (#
platters/disk)
• Example:
– 512 bytes/sector, 300 sectors/track (average)
– 20,000 tracks/surface, 2 surfaces/platter
– 5 platters/disk
– Capacity = 512 x 300 x 20000 x 2 x 5 = 30.72GB
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
20. Computing Disk Capacity
• Capacity =(# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x (#
platters/disk)
• Example:
– 512 bytes/sector, 200 sectors/track (average)
– 50,000 tracks/surface, 2 surfaces/platter
– 3 platters/disk.
– Find the capacity.
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
21. Disk Performance Parameters
• Access time for disc is greater than that for cache/main memory or
semiconductor memory.
• Seek time (Ts)
– Time require to positioned the head on the desired track
(in ms due to mechanical system)
• Rotational delay
– Time require to positioned desired sector under r/w head
(for each sector rotation is different, thus consider average rotation)
• Transfer time
-- Time required for reading /recording disk
• The Total average access time is: Ta= Ts+
1/2r + b/rN
– Here Tsis Average seek time
– r is rotation speed in revolution per second
– b number of bytes to be transferred
– N number of bytes on a track
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
22. Performance Improvement in
Secondary Storage
• In general multiple components improves the performance
• Similarly multiple disks should reduce access time?
– Arrays of disks operates independently and in parallel
– Also used as standby if one or more disk fails
– Used where response time is critical
• Justification
– With multiple disks separate I/O requests can be handled
in parallel
– A single I/O request can be executed in parallel, if the
requested data is distributed across multiple disks
• Researchers @ University of California-Berkeley proposed the
RAID (1988)
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
23. RAID
• Redundant Array of Independent Disks
• Seven levels in common use
• Not a hierarchy
• Characteristics
1. Set of physical disks viewed as single logical drive
by operating system
2. Data distributed across physical drives
3. Can use redundant capacity to store parity
information
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
24. Data Mapping in RAID 0
No redundancy
Data striped across all
disks Round Robin striping
• Data is distributed across the disk in strips :0,1,2,3
• Work distributed among 4 disks
Increased Speed
• Multiple data requests probably not on same disk
• Disks seek in parallel
• A set of data is likely to be striped across multiple disks
Draw Backs:
• Not a "True" RAID because it is NOT fault-tolerant
• The failure of just one drive will result in all data in an array being lost
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
25. RAID 1
Mirrored Disks ,Data is striped across disks
2 copies of each stripe on separate disks
In case hard disk fails, parallel disk can work
Read from either and Write to both
If N is no.of data disk ,then Redundency-2N
Recovery is simple
• Swap faulty disk & re-mirror
• No down time
Draw back
• Highest disk overhead of all RAID types (For any write,2 copies are to be made
• Expensive
• Any write should be done on two disks
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
26. Data Mapping in RAID 2
Lots of redundancy
Expensive: Good for erroneous disk
If N is no.of data disk ,then Redundancy- logN
Use parallel access technique
• Very small size strips
• Error correcting code is calculated across corresponding bits on each data disks
• Multiple parity disks store Hamming code error correction in corresponding
positions
Some parity info of data is stored so that if any disk fails, then data can be recovered.
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
27. Data Mapping in RAID 3
Similar to RAID 2
• Bit interleaved parity used
• Only one redundant disk, no matter how large the array
• Simple parity bit for each set of corresponding bits
• Data on failed drive can be reconstructed from surviving data and parity information
e.g. For ith bit, parity will be stored as: X4(i) = X3 (i) xor X2(i) xor X1 (i) xor X0 (i)
• If X2 disc is failed ,its data can be recovered as follows: Xoring X4 (i) xor
X2(i) on both sides of equation ,we get: X2(i) = X3 (i) xor X1 (i) xor X0
(i) xor X4(i)
X0 X1 X2 X3 X4
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
28. RAID 4
• Make use of independent access with block level striping
• Good for high I/O request rate due to large strips
• Bit by bit parity calculated across stripes on each disk
• Parity stored on parity disk
• If N is no.of data disk ,then N+1 are total disk reqd.
• If any disk gets modified, then Parity disk will get modified
simultaneously ,thus a long queue can be there for writing parity
info. corresponding to the blocks
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
29. RAID 5
• Parity disc distributed along each disk(No.of disk are same)
• Round robin allocation for parity stripe
• It avoids RAID 4 bottleneck at parity disk
• Commonly used in network servers
• Drawback
– Disk failure has a medium impact on throughput
– Difficult to rebuild in the event of a disk failure (as
compared to RAID level 1)
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
30. RAID 6
• Two parity calculations are distributed along the disk
• Stored in separate blocks on different disks
• If 2 disk fail, then also data can be recovered
• If N is no.of data disk ,then N+2 are total disk reqd.
• High data availability
– Three disks need to fail for data loss
– Significant write penalty
• Drawback
– Controller overhead to compute parity is very high
Hope Foundation’s International Institute of Information Technology, I²IT, P-14 Rajiv Gandhi Infotech Park, Hinjawadi, MIDC Phase I,
Pune - 411 057 www.isquareit.edu.in | info@isquareit.edu.in | Tel +9120 22933441 / 2 /3
31. THANK YOU
For further information please contact
Bailappa Bhovi
Department of Computer Engineering
Hope Foundation’s
International Institute of Information Technology, I²IT
P-14, Rajiv Gandhi Infotech Park, MIDC Phase 1, Hinjawadi,
Pune – 411 057
Phone - +91 20 22933441
www.isquareit.edu.in | bailappab@isquareit.edu.in|
info@isquareit.edu.in