The 8086 microprocessor has a 16-bit architecture and was designed by Intel between 1976-1978. It has a 20-bit address bus allowing access to 1MB of memory. The 8086 gave rise to the x86 architecture and was used in the original IBM PC. The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit. The BIU handles data and address transactions on the buses for the EU. It contains an instruction queue, segment registers, and instruction pointer. The EU contains general registers, an ALU, and flag register for performing arithmetic and logical operations.

1. Presentation On
8086 MICROPROCESSOR ARCHITECTURE

2. Daffodil International University
Submitted To:
Mahbuba Maliha Mourin
Lecturer
Daffodil International University
Submitted By:
Nirnay Mukharjee – 143 – 15 – 4421

3. History of 8086
microprocessor
 The 8086 is a 16-bit microprocessor chip designed by Intel
between early 1976 and mid-1978.
 The Intel 8088, released in 1979.
 The processor used in the
original IBM PC.
 The 8086 gave rise to the x86
architecture Intel's most successful
processors.
which eventuallybecame

4. Features of Intel– 8086
microprocessor
• It is a 16-bitmicroprocessor.
• 8086has a 20bitaddress buscan
access up to220 memory locations (1MB).
• It can support upto64K I/O ports.
• It provides 16-bitregisters
• It has multiplexedaddress and databusAD0-AD15 and
A16 – A19.

5. Internal Architecture
of8086
• The8086 CPUlogic hasbeen partitioned into two functional units
namely BusInterface Unit (BIU) and Execution Unit (EU)

6. Internal Architecture
of8086
TheBIU handles all
transactions of data and
addresses on the buses forEU
Themajor reason for this
separation is to increasethe
processing speed of the
processor

7. 20-bit physical
address
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Physical address= segment x1Oh+ offset
9

8. Bus Interface
Unit
• TheBIU has
• Instruction stream bytequeue
• Aset of segmentregisters
• Instruction pointer

9. BIU – Instruction Byte
Queue
• 8086 instructions vary from 1 to 6bytes
• Therefore fetch and execution are taking place concurrently in order
toimprove the performance of the microprocessor
• TheBIUfeeds the instruction stream to the execution unit througha
6 byte prefetch queue

10. Segment
Registers
• CS - points at the segment containingthe
current program.
• DS - generally points at segmentwhere
variables are defined.
• ES - extrasegment register, it's up to acoder
to define itsusage.
• SS - points at the segment containingthe
stack.

11. Instruction
pointer
• IP - the instructionpointer:
1. Always points to next instruction tobe executed
2. Offset address relative to CS
• IP register always works together with CS
segment register and it points tocurrently
executing instruction.

12. Execution
Unit
• General registers
• Arithmetic and Logical Unit (ALU)
• Flagregister

13. General
registers

14. Flag
register

15. Arithmetic and Logical
Unit
• An arithmetic logic unit (ALU)represents the fundamental building
block of the central processing unit of acomputer.AnALUis adigital
circuit used to perform arithmetic and logicoperations.

16. Thank You