The document discusses memory organization and interfacing for the 8086 microprocessor. It describes how the 8086's 20-bit address bus is used to address 1MB of memory in two banks - an even bank using address lines A0 and D0-D7, and an odd bank using the complement of A0 and D8-D15. It provides examples of byte and word transfers to even and odd addresses, and compares the cycles, lines, and control signals used. Address decoding techniques like absolute, linear, and block decoding are also summarized. An example is given to interface 32KB of RAM using absolute decoding.

1. MICROPROCESSOR
SYSTEMS
Week-7
INTERFACING

2. Memory Organization of 8086
• 8086 has a 20 bit address bus and hence it can
address 2^20 or 1,048,576 addresses
• Each location one byte is stored
• Two consecutive memory locations are required
for a word to store
• Both memory read and memory write
operations require more than one machine cycle
• Memory organization is required to complete
memory read and memory write operations to
be completed with one machine cycle

3. Memory Organization of 8086
• Memory is divided into two parts (banks)
• Each bank will have 524,288
bytes (512KB)
• One bank contains all the
even addressed locations like
00000, 00002 and 00004
• Data lines of Even bank are
connected to the lower eight
data lines D0-D7
• Even Bank also called
lower bank

4. Memory Organization of 8086
• The other bank has all the odd
addressed locations like 00001,
00003 and 00005
• Data lines of odd bank are
connected to the upper eight
data lines, D8- D15 of the 8086
• ODD Bank also called
higher bank

5. Memory Organization of 8086
• Address line A0 is used as part of the enabling
for memory in the lower bank.
• Bus High Enable (BHE – Active Low) is used to
enable the upper memory bank
 EVEN (LOW)
BANK
 ODD (HIGH)
BANK

6. Memory Organization (Data Transfer)
• Case 1: Even address byte transfer by 8086
• Read/Write a byte form/to an even address
• A0 will be low
• BHE (Active Low) will be high
• Byte is transferred to/from low bank through
D0-D7
• One Machine Cycle required
• Example
MOV AH,DS:BYTE PTR[0000]

7. Memory Organization (Data Transfer)
• Case 1: Even address byte transfer by 8086

8. Memory Organization (Data Transfer)
• Case 2: Odd address byte transfer by 8086
• Read/Write a byte from/to an odd address
• A0 will be high
• BHE (Active Low) will be asserted low
• Low bank is disabled and high bank is enabled
• Byte is transferred through D0-D7
• One Machine Cycle required
• Example
MOV AL,DS:BYTE PTR[0001]

9. Memory Organization (Data Transfer)
• Case 2: Odd address byte transfer by 8086

10. Memory Organization (Data Transfer)
• Case 3: Even address word transfer by 8086
• A0 will be asserted low – Low byte of the word
through D0-D7
• BHE (Active Low) will be asserted low –high
byte of the word through D8-D15
• One Machine Cycle required
• Example
MOV AX,DS:WORD PTR[0000]

11. Memory Organization (Data Transfer)
• Case 3: Even address word transfer by 8086

12. Memory Organization (Data Transfer)
• Case 4: Odd address word transfer by 8086
• Read/Write a word from/to an odd address
• Two bus cycles are required
• During the first machine cycle assert BHE
(Active Low) as low and A0 as high
• First byte is transferred through D0-D7 and the
second byte is transferred through D8-D15
• Example
MOV AX,DS:WORD PTR[0001H]

13. Memory Organization (Data Transfer)
• Case 4: Odd address word transfer by 8086

14. Memory Organization (Data Transfer)
Comparison among different memory accesses
Memory
Type
Data
Type
BHE A0
BUS
Cycles
Data
Lines
Even BYTE 1 0 1 D0 – D7
Odd BYTE 0 1 1 D8 – D15
Even WORD 0 0 1 D0 – D15
Odd WORD
0 1 First D8 – D15
1 0 Second D0 – D7

15. Memory Organization (Data Transfer)
• Is the word at address 01231H in a 8086 based
system aligned or misaligned?
• How many memory cycles are required to read
the word?

16. Address Decoding Techniques
• The Different types of address decoding techniques in
8086 Microprocessor are,
1. Absolute decoding
2. Linear decoding
3. Block decoding

17. Address Decoding Techniques
1. Absolute decoding
• Memory chip is selected only for the specified logic level
on the address lines
• No other logic levels can select the chip

18. Address Decoding Techniques
1. Absolute decoding
• Figure shows the memory interface with
absolute decoding
• Two 8K EPROMs (2764) are used to provide
even and odd memory banks
• Control signals BHE and A0 are used to enable
outputs of odd and even memory banks
respectively

19. Address Decoding Techniques
1. Absolute decoding
• Each memory chip has 8K memory locations,
thirteen address lines are required to address
each locations, independently
• Remaining address lines are used to generate
an unique chip select signal
• This addressing technique is normally used in
large, memory systems.

20. Address Decoding Techniques
2. Linear decoding
• Hardware for the decoding logic can be eliminated, by
using only required number of addressing lines (not all)
• Other lines are simply ignored
• Linear Decoding or Partial Decoding

21. Address Decoding Techniques
2. Linear decoding
• Used in small systems
• Figure shows the addressing of 16K RAM (6264)
with linear decoding
• Control signals BHE and A0 are used to, enable
odd and even memory banks, respectively

22. Address Decoding Techniques
2. Linear decoding
• RAM chips when A19 is low, chip is selected
• The status of A14 to A18 does not affect the chip
selection logic
• This gives you multiple addresses (shadow
addresses)
• This technique reduces the cost of Address
Decoding Techniques in 8086 Microprocessor
circuit, but it has drawback of multiple
addresses

23. Address Decoding Techniques
3. Block decoding
• In a microcomputer system the memory array is
often consists of several blocks of memory chips
• Each block of memory requires decoding circuit
• To avoid separate decoding for each memory
block special decoder IC is used to generate
chip select signal for each block

24. Address Decoding Techniques
3. Block decoding
• Figure shows the block Address Decoding
Techniques in 8086 Microprocessor using 74138,
3:8 decoder
•

25. Memory Interfacing
Example 1: Interface 32KB of RAM to the 8086
microprocessor using absolute decoding with the suitable
address.

26. Memory Interfacing

27. Memory Interfacing

28. Memory Interfacing

29. REVIEW