Computer Architecture Degree Program in Applied Computer Science University of Urbino http://informatica.uniurb.it/

1. Carc 03.03
alessandro.bogliolo@uniurb.it
03. Logic Networks
03.03. Sequential Circuits
• Dealing with feedback
• Finite state machines
• Latches
• Flip flops
• Registers
• Synchronous sequential circuits
Computer Architecture
alessandro.bogliolo@uniurb.it

2. Carc 03.03
alessandro.bogliolo@uniurb.it
Dealing with feedback
s r y y'
0 0 ? ?
0 1 0 1
1 0 1 0
1 1 0 0
s r y y' y y'
0 0 0 0 1 1
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 0 1

3. Carc 03.03
alessandro.bogliolo@uniurb.it
Sequential circuits: FSMs
• Finite state machines (FSM): (S,I,O,f,g,s0)
• Output function o=f(s,i)
• Next-state function snext=g(s,i)
• Representation: state diagram
• Classification:
• Combinational f:I  O
• Sequential (Mealy’s) f:SxI  O g:SxI  S
• Sequential (Moore’s) f:S  O g:SxI S
• Asynchronous vs Synchronous

4. Carc 03.03
alessandro.bogliolo@uniurb.it
Moore’s FSM: example
ON
Light
OFF
Dark
off
on
offon
S = {ON,OFF}
I = {on,off}
O = {Light,Dark}
f: S  O
g: SxI  S
state
out
in
f g
State Input Output Snext
OFF off Dark OFF
OFF on Dark ON
ON off Light OFF
ON on Light ON
Case of a simple power supply system controlled
by an on/off switch and monitored by a led

5. Carc 03.03
alessandro.bogliolo@uniurb.it
Mealy’s FSM: example
ON OFF
off, D
on, D
off, D
test, D
on, D
test, L
S = {ON,OFF}
I = {on,off,test}
O = {Light,Dark}
f: SxI  O
g: SxI  S
state
in,out
f g
State Input Output Snext
OFF off Dark OFF
OFF on Dark ON
OFF test Dark OFF
ON off Dark OFF
ON on Dark ON
ON test Light ON
Case of a simple power supply system controlled
by an on/off switch and monitored by a led when a
test button is pressed

6. Carc 03.03
alessandro.bogliolo@uniurb.it
FSMs: example
state input (sr) f g
A 00 01 A
A 01 01 A
A 10 10 B
A 11 00 A
B 00 10 B
B 01 01 A
B 10 10 B
B 11 00 B

7. Carc 03.03
alessandro.bogliolo@uniurb.it
Latch SR
y y'
y' s r f g
0 0 0 1 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0
In order to use the circuit to store a bit,
we need three input configurations to:
•set y=1 regardless of the current state
•set y=0 regardless of the current state
•keep y unchanged
SETRESET
HOLD

8. Carc 03.03
alessandro.bogliolo@uniurb.it
Latch SR
y y'
y' s r f g
0 0 0 1 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0
(s,r) = (1,0) SET
(s,r) = (0,1) RESET
(s,r) = (0,0) HOLD
(s,r) = (1,1) NOT ALLOWED
Notice that y’=NOTy for all allowed input
configurations
SETRESET
HOLD

9. Carc 03.03
alessandro.bogliolo@uniurb.it
Flip Flop SR
Clk S R s r
0 0 0 0 0 HOLD
0 0 1 0 0 HOLD
0 1 0 0 0 HOLD
0 1 1 0 0 HOLD
1 0 0 0 0 HOLD
1 0 1 0 1 RESET
1 1 0 1 0 SET
1 1 1 1 1 NOT ALLOWED

10. Carc 03.03
alessandro.bogliolo@uniurb.it
Flip Flop D Level Sensitive
Clk D S R s r
0 0 0 1 0 0 HOLD
0 1 1 0 0 0 HOLD
1 0 0 1 0 1 RESET
1 1 1 0 1 0 SET

11. Carc 03.03
alessandro.bogliolo@uniurb.it
Flip Flop D Edge Triggered
n

12. Carc 03.03
alessandro.bogliolo@uniurb.it
Registers
...
n-bit register
n
0
1
n-1

13. Carc 03.03
alessandro.bogliolo@uniurb.it
Synchronous Sequential Circuits
General
Mealy’s
Moore’s
f(s,i)
g(s,i)
f(s,i)
g(s,i)
f(s)g(s,i)