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CArcMOOC 05.03 - Pipeline hazards
The document discusses various types of CPU pipeline hazards, including structural, data, and control-flow hazards, while proposing solutions for each. It explains structural hazards due to shared memory access and suggests the use of Harvard architecture to prevent them, alongside various techniques for addressing data hazards through methods such as data forwarding and utilizing multiple execution cycles. Additionally, it covers control-flow hazards and their solutions, including branch prediction techniques and delayed branches to enhance CPU performance.
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CArcMOOC 05.03 - Pipeline hazards
- 1. Carc 05.03 alessandro.bogliolo@uniurb.it 05. CPU 05.03.Pipeline hazards • Structural hazards • Data hazards • Control-flow hazards • Multi-cycle instructions • CPU-time estimate Computer Architecture alessandro.bogliolo@uniurb.it
- 2. Carc 05.03 alessandro.bogliolo@uniurb.it Structural hazards(problem) • Von-Neumann architecture: single memory Load Mem Reg ALU Mem Reg Instr1 Mem Reg ALU Mem Reg Instr2 Mem Reg ALU Mem Reg Instr3 Mem Reg ALU Mem Reg Instr4 Mem Reg ALU Mem Reg Load Mem Reg ALU Mem Reg Instr1 Mem Reg ALU Mem Reg Instr2 Mem Reg ALU Mem Reg Stall --- --- --- --- --- Instr3 Mem Reg ALU Mem Reg Instr4 Mem Reg ALU Mem Reg 2 clock cycles per memory access If 40% of instructions are memory accesses, avgCPI = 1.4
- 3. Carc 05.03 alessandro.bogliolo@uniurb.it Structural hazards(solution) • Harvard architecture: separate memories for data (DM) and instructions (IM) Memory accesses cause no structural hazards Load IM Reg ALU DM Reg Instr1 IM Reg ALU DM Reg Instr2 IM Reg ALU DM Reg Instr3 IM Reg ALU DM Reg Instr4 IM Reg ALU DM Reg
- 4. Carc 05.03 alessandro.bogliolo@uniurb.it Data hazards(problem) • Define and use / Read after write ADD r1 r2 r3 IM reg ALU DM reg SUB r4 r5 r1 IM reg ALU DM reg AND r6 r1 r7 IM reg ALU DM reg OR r8 r1 r9 IM reg ALU DM reg ZOR r10 r1 r11 IM reg ALU DM reg ADD r1 r2 r3 IM reg ALU DM reg SUB r4 r5 r1 IM --- --- --- reg ALU DM reg AND r6 r1 r7 IM reg ALU DM reg OR r8 r1 r9 IM reg ALU DM reg ZOR r10 r1 r11 IM reg ALU DM reg
- 5. Carc 05.03 alessandro.bogliolo@uniurb.it Data hazards(solution 1) • Data forwarding from MA/WB to ALU ADD r1 r2 r3 IM reg ALU DM reg SUB r4 r5 r1 IM reg ALU DM reg IR PC1 WB ME EX A B IMM RW ID/EX WB ME ALU out B RW EX/MA WB ALU out MEM Dat RW MA/WBIF/ID Instr. Mem. PC Register file Alu Data Mem. WB logic CU
- 6. Carc 05.03 alessandro.bogliolo@uniurb.it Data hazards(solution 1) • Data forwarding from EX/MA to ALU ADD r1 r2 r3 IM reg ALU DM reg SUB r4 r5 r1 IM reg ALU DM reg AND r6 r1 r7 IM reg ALU DM reg IR PC1 WB ME EX A B IMM RW ID/EX WB ME ALU out B RW EX/MA WB ALU out MEM Dat RW MA/WBIF/ID Instr. Mem. PC Register file Alu Data Mem. WB logic CU
- 7. Carc 05.03 alessandro.bogliolo@uniurb.it ADD r1r2 r3 IM reg ALU DM reg SUB r4 r5 r1 IM reg ALU DM reg AND r6 r1 r7 IM reg ALU DM reg OR r8 r1 r9 IM reg ALU DM reg Data hazards (solution 3) • Double-rate registers IR PC1 WB ME EX A B IMM RW ID/EX WB ME ALU out B RW EX/MA WB ALU out MEM Dat RW MA/WBIF/ID Instr. Mem. PC Register file Alu Data Mem. WB logic CU
- 8. Carc 05.03 alessandro.bogliolo@uniurb.it CBranch IFID EX MEM WB +1 IF (abort) Target --- --- IF ID EX MEM WB target+1 IF ID EX MEM WB Control-flow hazards (problem) • Assumptions: • Branch recognized during ID • Condition tested during EX • PC updated during MA UCBranch IF ID EX MEM WB +1 IF (abort) Target --- IF ID EX MEM WB target+1 IF ID EX MEM WB
- 9. Carc 05.03 alessandro.bogliolo@uniurb.it CBranch IFID EX MEM WB +1 IF (abort) Target --- IF ID EX MEM WB target+1 IF ID EX MEM WB Control-flow hazards (solution 1) • Assumptions: • Branch recognized during ID • Target computed during ID (PC updated soon) • Condition tested during EX (PC updated soon) UCBranch IF ID EX MEM WB +1 IF (abort) Target IF ID EX MEM WB target+1 IF ID EX MEM WB
- 10. Carc 05.03 alessandro.bogliolo@uniurb.it CBranch IFID EX MEM WB +1 IF (abort) Target IF ID EX MEM WB target+1 IF ID EX MEM WB Control-flow hazards (solution 2) • Assumptions: • Branch recognized during ID • Target computed during ID (PC updated soon) • Condition tested during ID (PC updated soon) UCBranch IF ID EX MEM WB +1 IF (abort) Target IF ID EX MEM WB target+1 IF ID EX MEM WB
- 11. Carc 05.03 alessandro.bogliolo@uniurb.it UTBranch IFID EX MEM WB +1 IF ID EX MEM WB +2 IF ID EX MEM WB Control-flow hazards (solution 3) • Predict untaken: • If the branch is not taken, the fetched instruction is not aborted TBranch IF ID EX MEM WB +1 IF (abort) Target IF ID EX MEM WB target+1 IF ID EX MEM WB
- 12. Carc 05.03 alessandro.bogliolo@uniurb.it UTBranch IFID EX MEM WB +1(delay) IF ID EX MEM WB +2 IF ID EX MEM WB Control-flow hazards (solution 4) • Delayed branch: • The instruction that follows a branch is always executed, regardless of the condition of the branch TBranch IF ID EX MEM WB +1(delay) IF ID EX MEM WB Target IF ID EX MEM WB target+1 IF ID EX MEM WB
- 13. Carc 05.03 alessandro.bogliolo@uniurb.it Multiple-execution cycles(1) • Different instructions may use different execution units • The execution phase of an instruction may require more than 1 clock cycles • Instructions with multiple-execution cycles gives rise to data and resource conflicts ADDD F4, F0, F2 IF ID EX EX MA WB ADDD F10, F6, F8 IF ID -- EX EX MA WB ADDD F14, F10, F12 IF -- ID -- EX EX MA WB
- 14. Carc 05.03 alessandro.bogliolo@uniurb.it Multiple-execution cycles(2) • Pipelined execution units • Replicated execution units ADDD F4, F0, F2 IF ID EX EX MA WB ADDD F10, F6, F8 IF ID EX EX MA WB ADDD F14, F10, F12 IF ID -- EX EX MA WB
- 15. Carc 05.03 alessandro.bogliolo@uniurb.it CPU specification •Functional specification • Instruction set • Interface • Pin-out • Electrical signals • Timing diagrams • Performance • Tclk • CPI • Latency • Repetition time
- 16. Carc 05.03 alessandro.bogliolo@uniurb.it Performance estimation stallsavgNICCPICPUC IC ICCPI CPI i ISi i avg stallsi ISi i NICCPICPUC (1) (2) (3) Latency Repetition time ICCPICPUC CPI avg avg 1