Computer Architecture Degree Program in Applied Computer Science University of Urbino http://informatica.uniurb.it/

1. Carc 05.01
alessandro.bogliolo@uniurb.it
05. CPU
05.01. Elementary pipelining and performance metrics
• Execution steps
• Multi-cycle implementation
• Pipelining
• Performance metrics
Computer Architecture
alessandro.bogliolo@uniurb.it

2. Carc 05.01
alessandro.bogliolo@uniurb.it
Execution steps
1. IF: Instruction fetch
Load a new instruction from memory
2. ID: Instruction decode
Decode the instruction and retrieve operands from
registers
3. EX: Execute
Perform computation
4. MA: Memory Access
Read or write data in memory
5. WB: Write Back
Write results back in the internal registers

3. Carc 05.01
alessandro.bogliolo@uniurb.it
Execution steps
IF ID EX MA WB
PC
MEM
CU
REG
ALU MEM REG
IR Operands
Control
Results
Address
Control
Results
Control
Resources
involved
Communication
between stages

4. Carc 05.01
alessandro.bogliolo@uniurb.it
Multi-cycle implementation
IF ID EX MA WB
PC
MEM
CU
REG
ALU MEM REG
IR Operands
Control
Results
Address
Control
Results
Control
Resources
involved
Communication
between stages

5. Carc 05.01
alessandro.bogliolo@uniurb.it
Performance
IF ID EX MAWB
IF ID EX MAWB
IF ID EX MAWB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
Single cycle
Multi cycle
Pipelining

6. Carc 05.01
alessandro.bogliolo@uniurb.it
Performance metrics
• CPUT [sec/program]
• CPUC [clocks/program]
• Tclk [sec/clock]
• CPI [clocks/instruction]
• IC [instruction/program]
• MIPS [Minstructions/sec]
• RMIPS = CPUT(ref)/CPUT*MIPS(ref)
• Latency [clocks]
• Throughput [instructions/sec]