The document discusses input/output (I/O) interfacing techniques with the 8085 microprocessor. It describes the fundamentals of I/O devices like input and output ports, and how they are used to transfer data to and from devices like keyboards and displays. The document outlines two techniques for interfacing I/O devices: memory mapped I/O which uses memory addresses and instructions to transfer data, and I/O mapped I/O which uses dedicated I/O addresses and instructions. Circuits for decoding addresses to select specific I/O devices are also presented.

1. Prof. Nitin Ahire 1
I/O Interfacing
with 8085
Prof. Nitin Ahire
XIE, Mahim

2. Prof. Nitin Ahire 2
fundamentals of I/O devices
• I/p Port
I/P PORT
BufferD0-D7
D0-D7
Enable
Data from
Keyboard

3. Prof. Nitin Ahire 3
fundamentals of I/O devices
• O/p Port
O/P PORT
latchD0-D7
D0-D7
Enable
Data to
Display

4. Prof. Nitin Ahire 4
I/O interfacing techniques
• Up support I/O interface tech.
• It partitions memory from I/O, via software
instruction like IN add, OUT add
• When these instructions decoded by the
processor it generate appropriate control
signals IO/M^
• In 8085 it is possible to connect 256 I/O
ports and 64Kb memory

5. Prof. Nitin Ahire 5
I/O interfacing techniques
• I/O devices can be interfaced in two
ways
1) I/O mapped I/O
2) Memory mapped I/O

6. Prof. Nitin Ahire 6
I/O interfacing techniques
• Memory mapped I/O
1) In this device add is 16 bit
( A0-A15)
2) MEMR^ and MEWR^
control signals are used
3) Instructions are LDA add,
STA Add, MOV A,M
4) Data trans. Bet reg and
I/O devices
5) No. of I/O devices
interface= 65536
( Theoretically)
• I/O mapped I/P
1) In this device add is 8
bit (A0-A7)
2) IOR^ and IOW^ control
signals are used
3) Instruction are IN Add,
OUT Add
4) Data trans. Bet acc and
I/O devices
5) No. of I/O devices
interface= 256 only

7. Prof. Nitin Ahire 7
I/O device selection for add (80h)
Decoder
A0
A3
A2
A1
A6
A5
A4
A7
G1^
G2^
G
Y0
OR
RD^/
WR^
IO/M^
Buffer
Or
latch
OR
NOT
OR
To I/O
device
Data
bus
Enable
IOR^/IOW^
Data bus

8. Prof. Nitin Ahire 8
• IN 80h ( here 80h is the address of i/p switches)
8 0
A15/A7 A14/A6 A9/A1A10/A2A11/A3A12/A4A13/A5 A8/A0
1 0 00000 0

9. Prof. Nitin Ahire 9
I/O device selection for add (80h)
3:8
Decoder
A0
A3
A2
A1
A6
A5
A4
A7
G1^
G2^
G
Y0
OR
RD^/
WR^
IO/M^
Buffer
Or
latch
OR
NOT
OR
Data transfer to
Accumulator
EnableIOR^/IOW^
I/P switches
S0-S7
Select
lines
Data bus

10. Prof. Nitin Ahire 10
I/O device selection for add (81h)
3:8
Decoder
A0
A3
A2
A1
A6
A5
A4
A7
G1^
G2^
G
Y1
OR
RD^/
WR^
IO/M^
Buffer
Or
latch
OR
NOT
OR
Data transfer to
Accumulator
EnableIOR^/IOW^
0/P Display
devices
Select
lines
Data bus