This document describes a column decoder design for memory that aims to minimize power and area. It summarizes the key components of a memory architecture including a 6-transistor memory cell, precharge circuit, sense amplifier, row decoder, column decoder, and control logic. The column decoder is implemented using pass transistor logic to reduce the number of transistors and area. Simulation results show the output waveforms of the column decoder, bidirectional multiplexer, sense amplifier, and control signals, verifying the read and write cycles. The design aims to reduce memory area by using a more efficient multiplexer and reducing the required number of sense amplifiers.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
In the project#1, IBM 130nm process is used to design and manual layout a 128 word SRAM, with word size 10bits. Cadence's Virtuoso is applied for layout editing, DRC and LVS running and circuit simulation.
Large number of interconnection
requirement has become a major limitation to the designs
using binary logic. One of the solutions for this is MultipleValued
Logic (MVL). MVL proves to be advantageous as it
reduces dynamic power dissipation, increases computational
ability, data density and requires less number of
interconnects. In this paper, the implementation of a Static
Random Access Memory (SRAM) cell using a quaternary D
Latch is proposed. The D Latch is built using NMAX, NMIN
and quaternary inverter circuit. Using this SRAM cell a 4X4
SRAM array is constructed and is compared with 4X4 array
of Quaternary Static CMOS memory cell. The spice coding
is done using 0.18μm CMOS technology and verification of
the design is done through HSPICE and COSMOSSCOPE
Synopsis Tools. Power and delay of the circuit is analyzed.
This is a project implemented in VHDL. It is design of a multi-level cache memory for a uni-processor system. The document also includes some of the simulation and synthesis results.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
In the project#1, IBM 130nm process is used to design and manual layout a 128 word SRAM, with word size 10bits. Cadence's Virtuoso is applied for layout editing, DRC and LVS running and circuit simulation.
Large number of interconnection
requirement has become a major limitation to the designs
using binary logic. One of the solutions for this is MultipleValued
Logic (MVL). MVL proves to be advantageous as it
reduces dynamic power dissipation, increases computational
ability, data density and requires less number of
interconnects. In this paper, the implementation of a Static
Random Access Memory (SRAM) cell using a quaternary D
Latch is proposed. The D Latch is built using NMAX, NMIN
and quaternary inverter circuit. Using this SRAM cell a 4X4
SRAM array is constructed and is compared with 4X4 array
of Quaternary Static CMOS memory cell. The spice coding
is done using 0.18μm CMOS technology and verification of
the design is done through HSPICE and COSMOSSCOPE
Synopsis Tools. Power and delay of the circuit is analyzed.
This is a project implemented in VHDL. It is design of a multi-level cache memory for a uni-processor system. The document also includes some of the simulation and synthesis results.
Static-Noise-Margin Analysis of Modified 6T SRAM Cell during Read Operationidescitation
As modern technology is spreading fast, it is very
important to design low power, high performance, fast
responding SRAM(Static Random Access Memory) since they
are critical component in high performance processors. In
this paper we discuss about the noise effect of different SRAM
circuits during read operation which hinders the stability of
the SRAM cell. This paper also represents a modified 6T
SRAM cell which increases the cell stability without
increasing transistor count.
Designed a fully customized 128x10b SRAM by constructing schematic & virtuoso layout of memory cell array (6T cell), row & column decoder, pre-charge circuit, write circuit and sense amplifier using Cadence. Manually placed and routed all components, performed DRC & LVS debugging of constructed schematic and layout and ran PEX to generate the final Netlist, Hspice Spectre simulation of final design for verification of the correct functionality and analysis of best read, best write cycles & the worst case timing for read and write. Timing and power consumed is analyzed through STA-Primetime (Static timing Analysis)
Design of a 64-bit ultra low latency memory using 6T SRAM cells and PDK 45nm technology on CADENCE to simulate the results of our chosen implementation.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH...jedt_journal
In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving
structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and
write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOL...VLSICS Design
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Static-Noise-Margin Analysis of Modified 6T SRAM Cell during Read Operationidescitation
As modern technology is spreading fast, it is very
important to design low power, high performance, fast
responding SRAM(Static Random Access Memory) since they
are critical component in high performance processors. In
this paper we discuss about the noise effect of different SRAM
circuits during read operation which hinders the stability of
the SRAM cell. This paper also represents a modified 6T
SRAM cell which increases the cell stability without
increasing transistor count.
Designed a fully customized 128x10b SRAM by constructing schematic & virtuoso layout of memory cell array (6T cell), row & column decoder, pre-charge circuit, write circuit and sense amplifier using Cadence. Manually placed and routed all components, performed DRC & LVS debugging of constructed schematic and layout and ran PEX to generate the final Netlist, Hspice Spectre simulation of final design for verification of the correct functionality and analysis of best read, best write cycles & the worst case timing for read and write. Timing and power consumed is analyzed through STA-Primetime (Static timing Analysis)
Design of a 64-bit ultra low latency memory using 6T SRAM cells and PDK 45nm technology on CADENCE to simulate the results of our chosen implementation.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH...jedt_journal
In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving
structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and
write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOL...VLSICS Design
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CUR...VLSICS Design
In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In
addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is
engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.
FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CUR...VLSICS Design
In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.
FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CUR...VLSICS Design
In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under
different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.
FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CUR...VLSICS Design
In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with
voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage
of the respective connected word line signal in a selected row cells lower than the power supply voltage
VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In
addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row
memory cells. This configuration is aimed to control the source voltages of driver transistors under
different operating modes. Specifically, during a read operation, a two-stage reading mechanism is
engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is
a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast
writing also can be achieved.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Techn...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735. Volume 5, Issue 4 (Mar. - Apr. 2013), PP 07-14
www.iosrjournals.org
Column decoder using PTL for memory
M.Manimaraboopathy1, S.Sivasaravanababu2, S.Sebastinsuresh3 A. Rajiv4
1, 2, 3&4
Assitant Professor/ECE, Veltech HighTech DrRangarajan Dr Sakunthala Engineering college -India
Abstract: Nowadays memory forms an important and necessary part of every system. In order to make the
system more compact and faster, optimization of memory in terms of area, power and speed is to be made. In
this paper column decoder has been implemented to minimize the power and area. The memory architecture is
simulated using Laker-ADP schematic tool. The number of sense amplifiers required for MxN memory is
reduced in ratio 4:1.
Keywords: Laker-ADP schematic tool, decoder, memory
I. Introduction
A conceptual memory array organization is shown in Figure 1. The data storage structure, or core,
consists of individual memory cells arranged in an array of horizontal rows and vertical columns. Each cell is
capable of storing 1-bit of binary information. In this structure, there are 2N rows, also called word lines, and 2M
columns, also called bit lines. Thus, the total number of memory cells in this array is 2N x 2M.
To access a particular memory cell, i.e., a particular data bit in this array, the corresponding word line
and corresponding bit line must be activated (selected) according to the address coming from the outside of the
memory array. The row and column selection operations are accomplished by row and column decoders,
respectively. The row decoder circuit selects one out of 2N word lines according to an N-bit row address, while
the column decoder circuit selects one out of 2M bit-lines according to an M-bit column address. The
performance of the chip interface circuit determines a measure portion of the total memory speed, especially in
high performance SRAMs.
II. Memory Architecture
Architecture consists of 6 transistor bit-cell, precharge circuit, sense amplifier, row decoder, column
decoder, control logic.
Figure 1 Memory Architecture
2.1 Transistor Memory Cell
The basic cell for static memory design is based on 2 cross-coupled inverters with 2 pass transistors.
[1] The memory cell shown in Figure 2 forms the basis for most static random-access memories (SRAM) in
CMOS technology. It uses six transistors to store and access one bit. The four transistors in the center form two
cross-coupled inverters. Due to the feedback structure, a cell will store either 0 or 1 value. In actual devices,
these transistors are made as small as possible to save chip-area, and are very weak. The two lines between the
inverters are connected to two separate bit lines via two n-channel pass-transistors (left and right of the cell).
The gates of those transistors are driven by a word line.
www.iosrjournals.org 7 | Page
2. Column decoder using PTL for memory
Figure 2 Six-transistor SRAM memory cell [4]
2.2Read Operation
Figure 2a: Six-transistor (6T) SRAM cell at the onset of read operation [4]
The 6T SRAM cell has a differential read operation. This means that both the stored value and its
inverse are used in evaluation to determine the stored value. Before the onset of a read operation, the wordline is
held low (grounded) and the two bitlines connected to the cell through transistors M5 and M6 (see Figure 2a)
are precharged high (to VCC). Since the gates of M5 and M6 are held low, these access transistors are off and
the cross-coupled latch is isolated from the bitlines.
If a ’0’ is stored on the left storage node, the gates of the latch to the right are low. That means that
transistor M3 is initially turned off. In the same way, M2 will also be off initially since its gate is held high. This
results in a simplified model, shown in figure 3.2, for reading a stored ’0’ (reading ’0’).
In the figure the capacitors Cbit represents the capacitances on the bitlines, which are several
magnitudes larger than the capacitances of the cell. The cell capacitance has here been represented only through
the value held by each inverter (Q=0 and Q=1 respectively).
The next phase of the read operation scheme is to pull the wordline high and at the same time release
the bitlines. This turns on the access transistors (M5 and M6) and connects the storage nodes to the bitlines. It is
evident that the right storage node (the inverse node) has the same potential as BL and therefore no charge
transfer will be take place on this side.
The left storage node, on the other hand, is charged to ’0’ (low) [4] while BL is precharged to VCC.
Since transistor M5 now has been turned on, a current is going from Cbit to the storage node. This current
discharges BL while charging the left storage node. As mentioned earlier, the capacitance of BL (Cbit) is far
greater than that of the storage node. This means that the charge sharing alone would lead to a rapid charging of
the storage node, potentially destroying the stored value, while the bitline would remain virtually unchanged.
However, M1 is also turned on which leads to a discharge current from the storage node down to ground. By
making M1 stronger (wider) than M5, the current flowing from the storage node will be large enough to prevent
the node from being charged high.
After some time of discharging the bitline, the bitline signal is given to a specialized detection circuit
called Sense Amplifier (see Figure 4) through MUX.
www.iosrjournals.org 8 | Page
3. Column decoder using PTL for memory
2.3Write Operation
Figure 2b: Six-transistor SRAM cell at the onset of write operation [4] (writing ’0’-’1’).
For a standard 6T SRAM cell, writing is done by lowering one of the bitlines to ground while asserting
the wordline. To write a ’0’ BL is lowered, while writing a ’1’ requires BL to be lowered.
In the write operation (Figure 2b) the bitlines no longer are released. Instead they are held at VCC and
gnd respectively. If we look at the left side of the memory cell (M1-M5) it is virtually identical to the read
operation (figure 3.2). When the wordline is raised M6 is turned on and current is drawn from the inverse
storage node to BL. At the same time, however, M4 is turned on and, as soon as the potential at the inverse
storage node starts to decrease, current will flow from VCC to the node. In this case M6 has to be stronger than
M4 for the inverse node to change its state. The transistor M4 is a PMOS transistor and inherently weaker than
the NMOS transistor M6. Therefore, making both of them minimum size, according to the process design rules,
will assure that M6 is stronger and that writing is possible. When the inverse node has been pulled low enough,
the transistor M1 will no longer be open and the normal storage node will also flip, leaving the cell in a new
stable state. [4]
2.4 Precharge Circuit
Precharge plays an important role in decreasing the delay while writing bits into the memory or
reading the bits from memory. [1] Precharge circuit makes both, bit line and bit bar line to charge to precharge
voltage before carrying out either read operation or write operation. The advantage of precharging the lines lies
in the fact that only one line, either bit or bit bar is to discharge compared to the one line charged and other
discharged.
Figure 3 SRAM cell with precharge circuit [5]
www.iosrjournals.org 9 | Page
4. Column decoder using PTL for memory
Safe read and write operations require a modification of the memory array and timing sequence, based
on a precharge circuit. The usual voltage of precharge is VDD/2. Before reading or writing to the memory, the
bit lines are tied to VDD/2 using appropriate pass gates. When reading, the BL and ~BL diverge from VDD/2
(Figure 3) and reach the "1" and "0" levels after a short time.
2.5 Sense Amplifier
The sense amplifier (Figure 4) is an important circuit to regenerate the bit-line signals in a memory
design. The sense amplifier can be also applied to the receiving of long interconnection signal with large RC
delay and large capacitive load signal. Moreover, the complexity of the differential logic circuit can be enhanced
by combining the sense amplifier with differential logic networks to reduce the delay time. [3]
Figure 4 Sense Amplifier
Due to large arrays of SRAM cells, the resulting signal, in the event of a Read operation, has a much
lower voltage swing. To compensate for that swing a sense amplifier is used to amplify voltage coming off Bit
Line and Bit bar Line.
In order to read out the value of a given bit of a word in this type of memory, the bit-cell voltage, or
the magnitude of its charge, needs to be sensed, and the results of this sense operation must be delivered to the
rest of the circuit.
2.5 Row Decoder Circuit
Figure 5 Row decoder [4]
The block diagram of the N:2N row decoder and its associated circuitry is as shown above. Basically,
the decoder selects one of 2N lines, as per the address lines. The output of the decoder is fed to the rows of
www.iosrjournals.org 10 | Page
5. Column decoder using PTL for memory
SRAM cells. The row decoder selects one of those rows, depending on the N-bit address given to it. A normal
decoder can be built using logic gates as we have studied in digital design courses. However, the normal
decoder built using logic gates has drawbacks.
2.6 Column Decoder Circuit
Figure 6 Column Decoder
The column decoder selects a particular column in the memory array for reading the contents of the
selected memory cell (Figure 6) or to modify its contents. The column selector is based on the same principles
as those of the row decoder. The major modification is that the data flows both ways, that is either from the
memory cell to the Data Out signal (Read cycle), or from the Data In signal to the cell (Write cycle).
2.7 Multiplexer (MUX)
The Multiplexing circuit is used to route the data to & from the memory depending on the column
address. The inputs to this block are- Output of the column decoder, Input data to be written, read/write (rwb)
signal. Here the bidirectional MUX is realized using PTL logic. (Figure 7) As it uses less number of transistors
(only NMOS) helps in reducing area and power consumption.
Figure 7 Multiplexer
www.iosrjournals.org 11 | Page
6. Column decoder using PTL for memory
2.8 Control Logic
Figure 8 Control Block
Control logic is the most important block (Figure 8) in the Memory. It senses any changes in external
signals and issues internal signals based on whether it is a read or write operation. These signals are generated in
an order and with accuracy. These signals are routed to memory modules which performs different operation. It
also serves as a bi-directional data bus controller. Inputs to the control logic are the chip select signal, read/write
signal. The control logic will generate the signals like precharge signal, read enable or write enable, row and
column decoder enable.
III. Results
Simulation is carried out using Laker-ADP schematic editor to verify the read and write cycle of
memory. Main concentration was in reducing area of the memory by reducing area of bimux using PTL logic
and even reducing number of sense amplifier required by the ratio 4:1 and still maintaining the performance of
the memory. Simulation results for bit cell with sense amplifiers, bidirectional MUX, read cycle are shown
below.
3.1 Output waveforms of Column decoder
www.iosrjournals.org 12 | Page
7. Column decoder using PTL for memory
3.2 Output waveforms of Bimux
3.3 Output waveforms of Sense amplifier
3.4 Output waveforms of Control waveform
www.iosrjournals.org 13 | Page
8. Column decoder using PTL for memory
IV. Conclusion
Today technology has been changing rapidly to meet requirements like speed, area and power. Attempt
is made to reduce the area by implementing bidirectional MUX using PTL reducing number of transistors
required, which in turn helps in reducing the power.
References
[1] Jan M. Rabaey, Anantha Chandraprakasan, Borivoje Nikolic, “Digital integrated circuits, a design perspective,” second edition.
[2] Allen & Holberg “CMOS Analog Circuit Design” Second edition, Oxford University press, 2003.
[3] http://www.cedcc.psu.edu/khanjan/vsrow.htm
[4] Ingvar Carlson, “Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors,” Master’s thesis
performed in Electronic Devices, Ingvar Carlson Reg nr: LiTH-ISY-EX-3481-2004, 23rd March 2004
[5] Ramon Canal CTD – Master, “Memory Structures,” CANS Slides based on: Introduction to CMOS VLSI Design, D. Harris
www.iosrjournals.org 14 | Page