The document discusses current challenges in physical design for ASICs. Delays, especially from interconnects as technologies scale down, are a major challenge. Not all physical effects are accurately modeled in design tools. Some key challenges discussed are meeting timing constraints during floorplanning when interconnects are unknown, handling hard IP blocks, and balancing skew, insertion delay, and transition time during clock tree synthesis. Continued research is needed to better model physical effects and close remaining gaps in design flows.
As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
This document discusses the layout of analog CMOS integrated circuits. It focuses on the layout of transistors and basic cells. Key topics covered include:
- Layout of a single transistor, use of multiple fingers, and interdigitated transistors for matching.
- Common centroid layouts and dummy devices to reduce mismatch.
- Ensuring matched interconnect resistance, capacitance, and parasitics.
- Stacked layout of analog cells with stick diagrams to represent multiple transistors.
- Two examples of laying out basic cells - a two-stage op-amp and folded cascode. Design considerations like transistor sizing and grouping are discussed.
The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.
The document discusses VLSI design methodologies and limitations using CAD tools. It provides an overview of different VLSI design methodologies such as full custom design, semi-custom design, gate array design, standard cell design, FPGA-based design and CPLD-based design. It also discusses the evolution of VLSI design flows from past to present technologies. Furthermore, it describes the complexities in VLSI design and how CAD tools help manage these complexities and automate the design process. Finally, it summarizes different types of VLSI CAD tools and compares various open source and licensed CAD tool vendors.
This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.
Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern is believed to blur at around 45 nm half-pitch. For the semiconductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below. This presentation gives us an insight of why multiple patterning is an important to give us a better resolution below 32nm.
As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
This document discusses the layout of analog CMOS integrated circuits. It focuses on the layout of transistors and basic cells. Key topics covered include:
- Layout of a single transistor, use of multiple fingers, and interdigitated transistors for matching.
- Common centroid layouts and dummy devices to reduce mismatch.
- Ensuring matched interconnect resistance, capacitance, and parasitics.
- Stacked layout of analog cells with stick diagrams to represent multiple transistors.
- Two examples of laying out basic cells - a two-stage op-amp and folded cascode. Design considerations like transistor sizing and grouping are discussed.
The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.
The document discusses VLSI design methodologies and limitations using CAD tools. It provides an overview of different VLSI design methodologies such as full custom design, semi-custom design, gate array design, standard cell design, FPGA-based design and CPLD-based design. It also discusses the evolution of VLSI design flows from past to present technologies. Furthermore, it describes the complexities in VLSI design and how CAD tools help manage these complexities and automate the design process. Finally, it summarizes different types of VLSI CAD tools and compares various open source and licensed CAD tool vendors.
This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.
Multiple patterning is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern is believed to blur at around 45 nm half-pitch. For the semiconductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below. This presentation gives us an insight of why multiple patterning is an important to give us a better resolution below 32nm.
1. The document discusses the process for designing and fabricating analog integrated circuits using CMOS technology. It covers topics like MOS transistor operation, CMOS fabrication process steps, and SPICE device modeling parameters.
2. The CMOS fabrication process involves growing gate oxides, depositing polysilicon gates, implanting sources and drains, and depositing multiple metal interconnect layers.
3. SPICE device models are needed to simulate the behavior of transistors and circuits during the design process prior to fabrication. Device parameters are provided for a 0.8 micron CMOS process.
This document is a tutorial on circuit design using FinFETs presented at the 2013 IEEE International Solid-State Circuits Conference by Bing Sheu from TSMC. The tutorial covers technology considerations of FinFETs including their electrostatics benefits, SPICE modeling using the BSIM-CMG model, digital and memory circuit design methodology, and applications to analog/mixed-signal circuits. The document provides details on FinFET device structures, parasitic capacitances, scaling techniques, and performance comparisons to planar MOSFETs.
This document provides an introduction to VLSI technology and MOS transistors. It discusses the history and generations of integrated circuits from SSI to VLSI. The dominant fabrication process for high performance VLSI circuits is now silicon CMOS technology. The document then describes the basic MOS transistor structure and different types of MOS transistors including nMOS, pMOS, and CMOS. It explains the working of enhancement mode and depletion mode transistors. Finally, it discusses CMOS fabrication processes like p-well and n-well and the basic structure of a p-well CMOS process.
This document provides an overview of VLSI technology trends over time. It discusses how Moore's Law has been sustained through transistor scaling down to the nanometer level enabled by various techniques like strained silicon, high-k dielectrics, metal gates, SOI, multi-gate transistors like FinFETs. It outlines the evolution from bipolar junction transistors to MOSFETs to integrated circuits. Short channel effects posed challenges to scaling which were addressed through new device architectures in the second generation of scaling.
This document provides an overview of the ASIC design process, which includes the following main steps:
1. Front-end design including market research, specification, architecture, and RTL design.
2. Verification of the RTL code by verification engineers.
3. Synthesis of the RTL code into a gate-level netlist, followed by equivalence checking.
4. Physical design including placement and routing of standard cells, followed by extraction of parasitic components and timing analysis.
5. Physical verification including design rule checking and layout vs schematic checking.
This document discusses chip packaging technology. It explains that chip packaging brings signal and power connections out of the silicon die while also protecting the die from environmental conditions and dissipating heat. The document covers key aspects of chip packaging like Rent's rule, material selection, interconnect levels, multichip modules, thermal considerations, and trends in packaging technologies. It provides an overview of chip packaging objectives and requirements.
This document summarizes techniques for minimizing crosstalk in VLSI designs. It discusses the VLSI design cycle and physical design cycle. Routing is a key stage that involves global and detailed routing. Crosstalk occurs due to mutual inductance and capacitance between wires and can affect signal integrity, delay, and timing. Basic approaches to reduce crosstalk include segregating wires, increasing spacing between wires, using ground shields, optimizing the net ordering and layer assignments. Specific techniques mentioned are widening spacing, minimizing wire heights and lengths of parallel runs, using differential routing, and routing orthogonal layers.
The document discusses various layout optimizations that can be made to standard cells to reduce both internal power and area. These include removing "hammer head" structures to decrease transistor length, moving gate contacts over active areas to reduce transistor height, and reducing source/drain capacitances to decrease dynamic current without impacting speed. Post-layout simulations showed a new D flip-flop design with these optimizations reduced internal power by 20% while maintaining clock-to-Q delay, and improved saturation current by 15-50% while reducing area by 20%.
The document discusses four topics related to transistors:
1. Threshold voltage is the minimum gate voltage needed to create a conducting path between source and drain, and depends on oxide thickness, temperature, and random dopant fluctuations.
2. Latchup refers to a short circuit formed between power and ground rails in an integrated circuit, caused by interaction between parasitic bipolar transistors.
3. Electromigration is the forced movement of metal ions due to an electric field, with atoms traveling toward the positive conductor end and vacancies toward the negative end.
4. Mobility degradation occurs due to lateral and vertical electric fields scattering carriers, reducing surface mobility as channel lengths shrink.
The document discusses the inputs and outputs of place and route tools used in the chip design process. It describes the .cel, .blk, .par, and .net files that are used as inputs to specify connectivity, layout structure, global parameters, and nets. The outputs include the .p11, .p12, .pin, .twf, and .out files that describe placement and routing results. The document also briefly mentions design capture tools like HDL, schematics, and floor planning, as well as design verification tools such as simulation and timing verification.
The document provides an overview of analog layout design. It discusses that analog circuits require careful attention to geometry during layout due to process variations. The analog design flow includes electrical design, physical design involving layout, and fabrication/testing. Key considerations for analog layout include minimizing parasitic resistances and capacitances, reducing noise, and ensuring matching between identical components using techniques like common-centroid layout. Resistors and capacitors must be carefully laid out to minimize non-ideal effects and provide accurate values.
This document provides an overview of an "Analog VLSI Design" course. The goals of the course are to introduce principles of analog integrated circuit design and CMOS technology. Students will learn about CMOS layout design using CAD tools and complete a design project. The course covers topics including CMOS technology, resistors, capacitors, MOSFETs, current mirrors, amplifiers, and data converters. Assessment includes homework, a project, and a final exam.
IR Drop Analysis and Its Reduction Techniques in Deep Submicron TechnologyIJERA Editor
This paper presents a detailed conceptual analysis of IR Drop effect in deep submicron technologies and its reduction techniques. The IR Drop effect in power/ground network increases rapidly with technology scaling. This affects the timing of the design and hence the desired speed. It is shown that in present day designs, using well known reduction techniques such as wire sizing and decoupling capacitor insertion, may not be sufficient to limit the voltage fluctuations and hence, two more important methods such as selective glitch reduction technique and IR Drop reduction through combinational circuit partitioning are discussed and the issues related to all the techniques are revised.
The document provides an overview of the history and scaling of transistors and integrated circuits. It discusses how vacuum tubes were replaced by transistors, with the first transistor invented in 1947 and the first integrated circuit in 1958. It describes how continuous scaling and improvements in silicon manufacturing have led to billions of transistors being integrated onto a single chip today. The document then discusses different transistor technologies, including MOSFETs, and how scaling to smaller sizes introduced challenges like short channel effects that new transistor designs like FinFETs help address.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
This document discusses formal verification in VLSI systems. It begins by explaining that formal verification uses mathematical proofs to show a system works as intended, as an alternative to testing which is limited and costly for large VLSI designs. It then covers various techniques in formal verification including Kripke structures to model systems, temporal logic to specify properties, and model checking to automatically verify properties by exhaustive search. The document provides examples and discusses the challenges of state explosion in formal verification.
This document discusses the key inputs required for the physical design phase of a VLSI chip, using Synopsys tools as an example. The main inputs are: (1) a gate-level netlist describing the logical connections, (2) libraries providing timing, power and physical information for standard cells and macros, (3) a technology file describing manufacturing details, (4) parasitic extraction files (TLU+) for timing analysis, and (5) constraints describing design objectives. Additional inputs include floorplanning guidelines, scenarios for optimization, and reference design methodologies. The goal of physical design is to implement the logic from the netlist while meeting area, timing and power targets.
This document discusses physical design verification checks that are performed on an integrated circuit layout. It describes design rule checking (DRC) which checks that a layout adheres to foundry design rules for manufacturability. Layout versus schematic (LVS) checks that the layout connectivity matches the schematic netlist. Electrical rule checking (ERC) identifies electrical issues like floating devices or short circuits. The document provides examples of DRC, LVS, and ERC checks and typical issues found during these verification steps.
Calibre is an industry standard tool for layout verification. This document provides steps to run Design Rule Checking (DRC) and Layout Versus Schematic (LVS) checks using Calibre Interactive. The steps include setting the rule file, inputs, running DRC or LVS, and reviewing the results. Running DRC checks for layout rule violations. Running LVS compares the layout to the schematic netlist to check for electrical mismatches or connectivity errors.
The document discusses low power design techniques in VLSI. It begins by explaining why low power has become important, especially with the rise of mobile devices. It then discusses the different sources of power consumption, including dynamic and static power. Several low power design techniques are covered, such as clock gating, multi-Vt libraries, multi-voltage design, and power gating. The document emphasizes analyzing power at the system level and using EDA tools to implement low power techniques throughout the design flow. Overall, it provides an overview of analyzing power consumption and the goals and methods of low power VLSI design.
This document discusses digital VLSI design flows. It begins by acknowledging previous work that informed the presentation. It then discusses considerations in developing an electronic system, including components of the system. It describes integrated circuits based on application, fabrication technology, device, and device count. It discusses using standard or application-specific integrated circuits. It outlines a top-down design approach and terminology used in the design flow.
1. The document discusses the process for designing and fabricating analog integrated circuits using CMOS technology. It covers topics like MOS transistor operation, CMOS fabrication process steps, and SPICE device modeling parameters.
2. The CMOS fabrication process involves growing gate oxides, depositing polysilicon gates, implanting sources and drains, and depositing multiple metal interconnect layers.
3. SPICE device models are needed to simulate the behavior of transistors and circuits during the design process prior to fabrication. Device parameters are provided for a 0.8 micron CMOS process.
This document is a tutorial on circuit design using FinFETs presented at the 2013 IEEE International Solid-State Circuits Conference by Bing Sheu from TSMC. The tutorial covers technology considerations of FinFETs including their electrostatics benefits, SPICE modeling using the BSIM-CMG model, digital and memory circuit design methodology, and applications to analog/mixed-signal circuits. The document provides details on FinFET device structures, parasitic capacitances, scaling techniques, and performance comparisons to planar MOSFETs.
This document provides an introduction to VLSI technology and MOS transistors. It discusses the history and generations of integrated circuits from SSI to VLSI. The dominant fabrication process for high performance VLSI circuits is now silicon CMOS technology. The document then describes the basic MOS transistor structure and different types of MOS transistors including nMOS, pMOS, and CMOS. It explains the working of enhancement mode and depletion mode transistors. Finally, it discusses CMOS fabrication processes like p-well and n-well and the basic structure of a p-well CMOS process.
This document provides an overview of VLSI technology trends over time. It discusses how Moore's Law has been sustained through transistor scaling down to the nanometer level enabled by various techniques like strained silicon, high-k dielectrics, metal gates, SOI, multi-gate transistors like FinFETs. It outlines the evolution from bipolar junction transistors to MOSFETs to integrated circuits. Short channel effects posed challenges to scaling which were addressed through new device architectures in the second generation of scaling.
This document provides an overview of the ASIC design process, which includes the following main steps:
1. Front-end design including market research, specification, architecture, and RTL design.
2. Verification of the RTL code by verification engineers.
3. Synthesis of the RTL code into a gate-level netlist, followed by equivalence checking.
4. Physical design including placement and routing of standard cells, followed by extraction of parasitic components and timing analysis.
5. Physical verification including design rule checking and layout vs schematic checking.
This document discusses chip packaging technology. It explains that chip packaging brings signal and power connections out of the silicon die while also protecting the die from environmental conditions and dissipating heat. The document covers key aspects of chip packaging like Rent's rule, material selection, interconnect levels, multichip modules, thermal considerations, and trends in packaging technologies. It provides an overview of chip packaging objectives and requirements.
This document summarizes techniques for minimizing crosstalk in VLSI designs. It discusses the VLSI design cycle and physical design cycle. Routing is a key stage that involves global and detailed routing. Crosstalk occurs due to mutual inductance and capacitance between wires and can affect signal integrity, delay, and timing. Basic approaches to reduce crosstalk include segregating wires, increasing spacing between wires, using ground shields, optimizing the net ordering and layer assignments. Specific techniques mentioned are widening spacing, minimizing wire heights and lengths of parallel runs, using differential routing, and routing orthogonal layers.
The document discusses various layout optimizations that can be made to standard cells to reduce both internal power and area. These include removing "hammer head" structures to decrease transistor length, moving gate contacts over active areas to reduce transistor height, and reducing source/drain capacitances to decrease dynamic current without impacting speed. Post-layout simulations showed a new D flip-flop design with these optimizations reduced internal power by 20% while maintaining clock-to-Q delay, and improved saturation current by 15-50% while reducing area by 20%.
The document discusses four topics related to transistors:
1. Threshold voltage is the minimum gate voltage needed to create a conducting path between source and drain, and depends on oxide thickness, temperature, and random dopant fluctuations.
2. Latchup refers to a short circuit formed between power and ground rails in an integrated circuit, caused by interaction between parasitic bipolar transistors.
3. Electromigration is the forced movement of metal ions due to an electric field, with atoms traveling toward the positive conductor end and vacancies toward the negative end.
4. Mobility degradation occurs due to lateral and vertical electric fields scattering carriers, reducing surface mobility as channel lengths shrink.
The document discusses the inputs and outputs of place and route tools used in the chip design process. It describes the .cel, .blk, .par, and .net files that are used as inputs to specify connectivity, layout structure, global parameters, and nets. The outputs include the .p11, .p12, .pin, .twf, and .out files that describe placement and routing results. The document also briefly mentions design capture tools like HDL, schematics, and floor planning, as well as design verification tools such as simulation and timing verification.
The document provides an overview of analog layout design. It discusses that analog circuits require careful attention to geometry during layout due to process variations. The analog design flow includes electrical design, physical design involving layout, and fabrication/testing. Key considerations for analog layout include minimizing parasitic resistances and capacitances, reducing noise, and ensuring matching between identical components using techniques like common-centroid layout. Resistors and capacitors must be carefully laid out to minimize non-ideal effects and provide accurate values.
This document provides an overview of an "Analog VLSI Design" course. The goals of the course are to introduce principles of analog integrated circuit design and CMOS technology. Students will learn about CMOS layout design using CAD tools and complete a design project. The course covers topics including CMOS technology, resistors, capacitors, MOSFETs, current mirrors, amplifiers, and data converters. Assessment includes homework, a project, and a final exam.
IR Drop Analysis and Its Reduction Techniques in Deep Submicron TechnologyIJERA Editor
This paper presents a detailed conceptual analysis of IR Drop effect in deep submicron technologies and its reduction techniques. The IR Drop effect in power/ground network increases rapidly with technology scaling. This affects the timing of the design and hence the desired speed. It is shown that in present day designs, using well known reduction techniques such as wire sizing and decoupling capacitor insertion, may not be sufficient to limit the voltage fluctuations and hence, two more important methods such as selective glitch reduction technique and IR Drop reduction through combinational circuit partitioning are discussed and the issues related to all the techniques are revised.
The document provides an overview of the history and scaling of transistors and integrated circuits. It discusses how vacuum tubes were replaced by transistors, with the first transistor invented in 1947 and the first integrated circuit in 1958. It describes how continuous scaling and improvements in silicon manufacturing have led to billions of transistors being integrated onto a single chip today. The document then discusses different transistor technologies, including MOSFETs, and how scaling to smaller sizes introduced challenges like short channel effects that new transistor designs like FinFETs help address.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
This document discusses formal verification in VLSI systems. It begins by explaining that formal verification uses mathematical proofs to show a system works as intended, as an alternative to testing which is limited and costly for large VLSI designs. It then covers various techniques in formal verification including Kripke structures to model systems, temporal logic to specify properties, and model checking to automatically verify properties by exhaustive search. The document provides examples and discusses the challenges of state explosion in formal verification.
This document discusses the key inputs required for the physical design phase of a VLSI chip, using Synopsys tools as an example. The main inputs are: (1) a gate-level netlist describing the logical connections, (2) libraries providing timing, power and physical information for standard cells and macros, (3) a technology file describing manufacturing details, (4) parasitic extraction files (TLU+) for timing analysis, and (5) constraints describing design objectives. Additional inputs include floorplanning guidelines, scenarios for optimization, and reference design methodologies. The goal of physical design is to implement the logic from the netlist while meeting area, timing and power targets.
This document discusses physical design verification checks that are performed on an integrated circuit layout. It describes design rule checking (DRC) which checks that a layout adheres to foundry design rules for manufacturability. Layout versus schematic (LVS) checks that the layout connectivity matches the schematic netlist. Electrical rule checking (ERC) identifies electrical issues like floating devices or short circuits. The document provides examples of DRC, LVS, and ERC checks and typical issues found during these verification steps.
Calibre is an industry standard tool for layout verification. This document provides steps to run Design Rule Checking (DRC) and Layout Versus Schematic (LVS) checks using Calibre Interactive. The steps include setting the rule file, inputs, running DRC or LVS, and reviewing the results. Running DRC checks for layout rule violations. Running LVS compares the layout to the schematic netlist to check for electrical mismatches or connectivity errors.
The document discusses low power design techniques in VLSI. It begins by explaining why low power has become important, especially with the rise of mobile devices. It then discusses the different sources of power consumption, including dynamic and static power. Several low power design techniques are covered, such as clock gating, multi-Vt libraries, multi-voltage design, and power gating. The document emphasizes analyzing power at the system level and using EDA tools to implement low power techniques throughout the design flow. Overall, it provides an overview of analyzing power consumption and the goals and methods of low power VLSI design.
This document discusses digital VLSI design flows. It begins by acknowledging previous work that informed the presentation. It then discusses considerations in developing an electronic system, including components of the system. It describes integrated circuits based on application, fabrication technology, device, and device count. It discusses using standard or application-specific integrated circuits. It outlines a top-down design approach and terminology used in the design flow.
This document discusses routing of clock and power nets in VLSI physical design automation. It describes how clock and power routing have special considerations compared to other signal nets due to factors like clock skew, IR drop, and being major power consumers. It provides details on clock tree routing techniques like H-trees, MMM algorithm, and GMA algorithm to minimize clock skew. It also discusses power grid routing using mesh structures in multiple metal layers to reduce voltage drop and electromigration issues. Non-tree clock routing and combining clock routing with other optimizations are noted as future trends.
This document provides an overview of the EE895KR Advanced VLSI Design course taught by Professor Kaushik Roy at Purdue University. The course is targeted towards graduate students with prior VLSI design experience. It will cover real-world challenges in designing high-performance and low-power circuits. Students will complete a term-long individual project involving circuit design and simulation using CAD tools. The course topics include scaling issues, high-performance logic design, low power techniques, and process variation.
This document discusses static timing analysis (STA), which is used to verify that a digital circuit design meets timing requirements without simulating the circuit. It begins by explaining the objectives of timing analysis and the differences between static and dynamic timing analysis. Static timing analysis is described as examining all possible signal paths to calculate worst-case arrival times and check for timing violations, while dynamic analysis uses test vectors but is slower. The document then covers gate and net delay models used in STA, limitations of simple fixed delay models, and lumped and distributed RC net delay models.
This document provides an overview of VLSI design methodologies. It discusses how complexity of ICs grows exponentially each year, requiring methodology updates. It also covers topics like lower power consumption, cost reduction, reliability improvements, and more compact designs enabled by VLSI. The document outlines the typical VLSI design flow from system specification to fabrication. It also describes common design styles like FPGA, gate array, standard cell-based, and full custom designs as well as considerations for testability, yield, and technology updates.
This document provides an overview of the ASIC back-end design flow, including timing driven placement. It discusses the inputs to the Astro placement and routing tool, including the gate-level netlist, standard cell library, and timing constraints. It describes key aspects of the placement process, including floorplanning, placement rows, and timing driven placement to optimize critical paths. The goal is to meet all timing constraints by balancing timing, area, power, and signal integrity.
This document provides an overview of an ASIC/FPGA technology and design flow course. It discusses the course organization, material, schedule, and recommended literature. The course will cover FPGA and ASIC design flows, including Verilog, synthesis, simulation, and implementation. It will also discuss chip structures, technologies, applications and the semiconductor industry. Students will complete projects to design an FPGA peripheral and an ASIC, with design reviews to mimic industry practice. The goal is to prepare students for careers in chip design and verification.
This document introduces VLSI physical design. It discusses how the number of transistors on chips has rapidly increased over time, from 100,000 to over 3 million. Complex chip design is now only possible using computer-aided design tools. The document outlines the different levels of abstraction in chip design from behavioral modeling down to the cell/mask level. It provides examples of logical and architectural design, and discusses the different layout styles including full-custom, gate-array, and standard-cell approaches.
This document discusses deterministic Ethernet and related IEEE 802 standards. It begins with a history of deterministic Ethernet, describing its origins in industrial automation and professional audio/video. It discusses key markets and use cases such as industrial control, vehicular networks, and mission critical applications. It then covers topics including time synchronization using IEEE 802.1AS, quality of service mechanisms like audio/video bridging and scheduled traffic, and emerging work to further improve deterministic capabilities.
Traditional network design was based on general rules and focused on capacity planning rather than optimization. A top-down approach begins by analyzing customer requirements and applications before selecting devices. The network design life cycle includes phases for analysis, design, implementation, operation, optimization, and retirement. Key aspects of network analysis and design involve understanding customer needs, prioritizing performance requirements, and recognizing necessary trade-offs during optimization.
High speed-pcb-board-design-and-analysiscadence-130218085524-phpapp01khalid noman husainy
This document discusses Cadence's solutions for high speed PCB design challenges. It introduces SPECCTRAQuest, a suite of products for signal integrity, power integrity, and packaging analysis throughout the PCB design flow. Key aspects covered include constraint management, frequency-domain analysis for power delivery, and a new Model Integrity module for creating and validating models. A demonstration overview discusses using these capabilities for model development, topology planning, and system-level verification.
This document discusses challenges and requirements for low-power design and verification. It begins with an overview of how leakage is significantly increasing due to process scaling and how active power is now a major portion of power budgets. New strategies are needed to address process variations and enhance scaling approaches. The verification flows must support multi-voltage domain analysis and rule-based checking across voltage states while capturing island ordering and microarchitecture sequence errors. Low-power implementation introduces challenges for design representation, implementation across tools, and verification. Methodologies and design flows must be adapted to account for power and ground nets becoming functional signals.
The document discusses trends in integration technologies such as VLSI. It describes how VLSI has allowed for more compact, lower power, and higher speed integrated circuits. It classifies integrated circuits based on application, fabrication technique, technology, and device count. It then discusses the history of integrated circuits from the transistor in 1947 to modern chips containing tens of millions of transistors. It outlines drivers for VLSI technology including smaller sizes, lower power, and reduced costs.
The document discusses several topics related to integrated circuit design flow:
- It outlines the basic steps in analog and digital IC design flows, including schematic design, simulation, layout, DRC/LVS checks, and post-layout simulation.
- It reviews concepts like feature size, which refers to the minimum dimensions that can be reliably manufactured, and how feature size has decreased over time according to Moore's Law.
- It covers reliability challenges like defects that can cause circuit failures and how yield is modeled based on die area and defect density.
This document discusses disruptive technologies, specifically how Moore's Law has impacted the technology industry and networking. It provides three key points:
1. Moore's Law, which predicted the doubling of transistors on integrated circuits every two years, has been the guiding principle for new product development. However, for networking, transistor count has doubled but speed has increased slowly.
2. Networking performance has not kept up with Moore's Law like CPU performance has. Network ASICs have increased 10x over 12 years while CPUs increased 64x.
3. Merchant silicon using full custom chip designs has allowed networking to scale at Moore's Law growth rates, providing higher port density, lower price per port, and lower power consumption
This document discusses various system design techniques and networks. It begins with an overview of design methodologies like waterfall model, spiral model, and concurrent engineering. It then covers topics like requirements analysis, specifications, CRC cards for system analysis, and quality assurance techniques. It discusses several distributed embedded systems including CAN bus, I2C, Ethernet, and the Internet. It concludes with sections on multiprocessor system-on-chips and shared memory multiprocessors.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
2. Agenda - Current Challenges in ASIC
Physical Design
• Roots of challenges
• Delays - the main challenge
– Wire load models
• Generic PD flow
• Challenges in PD flow at different steps
• SI Challenge - Noise & Crosstalk, IR Drop
• Process effects
– Process Antenna Effect
– Electromigration
• Moving Forward
3. Root of challenges
• The main motivation behind ASIC Design is to develop chips
that:
– Work faster
– Are reliable
– Highly integrated
• Speed of a circuit is directly governed by delays involved in
the overall design – these are well-understood today
• Reliability is dependent on physical effects that can
manifest in some form or the other in a chip
– Can be controlled only by continuously evolving the fabrication
methodology
– A lot of effects are still a subject of active research
• Integration is being facilitated by scaling – very aggressive
4. Speed Requirement
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Frequency
(Mhz)
Doubles every
2 years
5. No. of Transistors - following Moore’s
law so far
Courtesy:Paper by Greg Watson of University of Delaware: “Moore’s Law: Is it rolling over?”
6. Root…
• While reliability and integration are foundry/ technology issues,
speed falls in ASIC design domain
• To achieve higher speeds, a lot of methodologies are being evolved
– Plain synthesis – not efficient for DSM (Deep Sub-Micron) technologies
– Physical Synthesis – closed the gap that was present in Plain Synthesis
flow
– Virtual Prototyping – closes the gap further – but yet not complete
– Interconnect-centric flow – likely to close the gap further – still being
studied
• Some device level effects have been modeled mathematically and
have been brought into EDA tool domain
• A lot of these are still at a very basic level – subject of active
research
7. Challenges
• Physical Design Engineer has to contend with real, physical effects
• Physical Design is an exercise of mapping a design from logical
domain to physical domain
• Entire process is dependant upon
– Libraries - where the physical effects are mathematically modeled
– Tools - have the necessary corrections/ remedies to the physical
effects
• As of now, not all the physical effects have been modeled - hence
there is a huge overhead on the Physical Design Flow to take care of
the adverse effects
• Delay is the only effect that has been modeled with a good accuracy
- flow based on handling delay has been used for long - known devil
8. Challenges
• Other challenges in Physical Design are:
– Flow Based:
• Partitioning - the most challenging aspect of this is getting a rectilinear
physical partition, optimal partition that meets timing, power etc.
• Floor planning - with IPs and memories flooding the designs, floor
planning is becoming the key to a successful design closure
• Placement - placer has to take care of a lot of issues like meeting
timing, congestion, design considerations like scan, boundary scan etc.
• Clock Tree Synthesis - the most challenging aspect of this is meeting
skew AND transition time AND insertion delay constraints
• Routing - router has to take care of design requirements like meeting
timing, incremental routing, routing on specific layers etc.
• Extraction - 3D and accurate extraction, extracting in standard format,
limited file size
9. Challenges
– Device related:
• Antenna effect - device scaling has made the transistor gate more
vulnerable to this effect - short term reliability issue
– Ref: https://en.wikipedia.org/wiki/Antenna_effect
• Noise - device scaling has also reduced the threshold of the
devices thereby increasing noise vulnerability
• Crosstalk - Due to increase in the vertical profile of nets, coupling
capacitance component has increased, causing increased crosstalk
• IR Drop - device scaling is also bringing down the value of
allowable IR drop
– Ref: http://www.vlsitechnology.org/html/irdrop_1.html
• Electromigration - Increased integration means increased power
dissipation - root for electromigration
– https://en.wikipedia.org/wiki/Electromigration
• Hot Electron effect - long term reliability issue
– https://en.wikipedia.org/wiki/Hot-carrier_injection
• Leakage current - IDDQ
• Sub-threshold effects due to reducing channel length
10. Delay
• Delay is the difference in “required time” and “arrival time”
– in synthesis terminology
• What can cause delay in a design?
– Device
– Interconnects
• Pre-DSM designs:
– Device delays were predominant
• DSM – UDSM designs:
– Device delays have been scaled down, but interconnect delays
have shot up
• ASIC design flow remained largely unchanged even if the
technology improved from 0.5 microns to 0.13 microns in
just 3 years
12. Gate Delay Modeling
• Cell Delay consists of two components:
– Intrinsic component
• Intrinsic delay - DI
– Extrinsic component
• Slope delay – DS – caused due to input transition - transition due
to previous stage
• Transition delay – DT – caused due to output pin loading and its
driving capability
• Interconnect delay – DC – caused due to the wire connecting the
output of one stage to the input of the next stage
DI
DS
DT
DC
13. Gate Delay…
• DI Is the intrinsic delay of the cell without any load
connected to it
• DC Is the delay due to the wire connecting one
stage to another – this is not known until the routing stage
• DT Is the delay due to the output load – more
popularly known as fanout
• DS Is the delay due to the transition delay of the previous
stage
• Cell delay are modeled in library in the form of 2-
dimensional tables
– Delay is a function of input transition and output load
– Too difficult to make it a function of DC since immense
possibilities of net topologies
Differentiate better between input delay and output delay
14. Interconnect Modeling - Wire Load
Models
• As DC is not available at the time of Synthesis,
some estimate is taken for calculation - this is
called Wire Load Model
• Equations for different delay components are
as follows:
DS = Ss x DT(previous stage)
DT = Rdriver(Cwire + Cpins)
DC = Rwire(Cwire + Cpins)
15. Wire Load Models
• Rwire
– determined from wire load model
• Length of net
– computed from the global estimation function which is
based on the number of fanouts for that net
• Cwire
– determined from the function that relates wire length with
the capacitance
• This forms the basis of Wire Load Models
• WLMs are estimations which relate the above three
parameters
• Examples:
16. WLM - Examples
• In the examples shown below
– Resistance - typical resistance of the nets per length
– Capacitance - typical capacitance of the nets per length
– Area - area of the net
– Slope - multiplication factor for wire lengths > 1 in the fanout_length construct
wire_load("tsmc13_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
}
wire_load("tsmc13_wl20") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 133.334;
fanout_length (1,133.334);
}
Example - 1 Example - 2
17. Gate Intrinsic Delay
• The basic building block of today’s cell-based designs is
a CMOS inverter
• CMOS Parasitics
– Resistance
• Source - Drain channel resistance
• Well tap resistance
• Substrate tap resistance
– Capacitance
• Source - Drain capacitance
• Gate - Channel capacitance
• Gate - Source overlap capacitance
• Gate - Drain overlap capacitance etc.
– SCR - causes latch up (Similar to Thyristor latchup)
21. Physical Design Flow Basics
• Physical Design Flow methodology can be classified as
follows:
– Flat
• Entire design is read into the PD tool and then P&R carried out
• Does not mean that the netlist is flat - netlist CAN have logical
hierarchy - it is flattened once it is read into PD tool
– Hierarchical
• Entire design is read into the PD tool, partitioned and then P&R
carried out on each partition as well as top-level
• Netlist MUST have logical hierarchy
• It can be further classified into:
– Timing Driven - based on timing constraints
– Non-timing Driven - does not depend upon the timing
constraints
22. Existing ASIC Design Flow:
Floorplan
TPNA
S, P&R
Physical
Verification
TPNA
TPNA
Block
Charact.
Top level FLP
P&R
Physical
Verification
TPNA
TPNA
TPNA
Block Level Implementation
Top Level Integration
TPNA
T - Timing
P - Power
N - Noise
23. Basic ASIC Design Flow
Chip Specification
RTL
Partition into Blocks
Floorplan
Select circuit fam. & topology
Draw schematics
Functional Verification
Timing Verification
Fast enough?
Synthesize
Timing Verification
Fast enough?
Layout & Tapeout
Resize
or
change
topology
Add/
modify
constraints
No No
Custom Circuit
Flow
Automatic Circuit
Flow
24. Partitioning
• The process of decomposition of a larger system is
done such that:
– the original functionality of the design is not lost
– the interface interconnections between the blocks is kept
to minimum
– the resulting block sizes are manageable from the tool
point of view (memory/ processor time/ manpower etc.)
– the process of decomposition should be just a fraction of
the total design time (this is from the tool algorithm point
of view)
– the resulting block could be reusable in different designs
• Both SOCE and MAGMA can handle designs with
around 5 million gate count in “flat” fashion
25. Partitioning
• For all the existing tools, physical partitioning is possible only if the
design has logical hierarchy - limitation
• Partitioning exercise is actually a grouping exercise where one
groups the modules together based on certain design criteria
– functionality
– proximity
– least number of interconnection between physical partitions
• It has been difficult to obtain partitions that are rectilinear in shape
- SOCE is capable of generating rectilinear soft blocks, MAGMA is
not
• Each tool generates a different type of soft block abstract
– LEF in Cadence flow
– Glass Box in MAGMA flow
• Top level interconnect lengths are long - challenge
27. Floor Planning
• The floorplanning problem is to plan the positions and
shapes of the modules at the beginning of the design
cycle to optimize the circuit performance:
– Chip Area
• Should be minimized keeping the Aspect Ratio in mind
– Total Wirelength
• Cannot be estimated at such an earlier stage - a major challenge
– Delay of critical path
• Plan the block placement and module placement in a way that
minimizes this delay
– Routability
• Floor planning should be carried out keeping in mind the
routability of the design
28. Floor Planning - some factors for
consideration
• Factors to be considered during floorplanning are:
– Shape of the block
• Modules should be shaped such that they form a perfect fit
– Routing considerations
• Follows from the routability concern from the previous slide
– Floorplanning and placement for high-performance circuits
• Certain techniques like blockaging etc. to be used to effectively
plan the area available for placement
– Packaging considerations
• While placing IOs one has to follow the packaging rules - IO
spacing rules
– Pre-placed blocks
• pre-placed blocks should not be moved
29. Floor Planning...
• One of the major challenges during the floor planning steps is to
ensure that timings are met
– how can one ensure timing closure when the interconnects are not in
place?
– Virtual Prototyping is the answer to this - tool must support that
• a step where a quick P&R is done to get an idea about the over all timing
profile of the design
• There is no tool which automatically generates a few floor plans
and gives out the timing and design statistics for each floor plan
– this will allow the designer to choose from the possible floor plans
• There is not tool which writes out parasitics file at this stage of the
flow
– If it does, the designer can carry out STA and find out the timing
statistics for a given floor plan
30. Floor Planning
• Hard IPs
– Advantage is that these are reusable as they are
– Problem is that these have fixed size
• Cannot resize during floor plan
• Causes problems for timing closure at the chip level (top
level)
– Can be solved by obtaining Soft IPs
• Can be resized and timing optimized from global perspective
• Another major challenge is packaging:
– Wire bond packaging - to follow packaging rules to
plan IOs
– Flip Chip methodology
31. Placement
• Placement strategies are built around the basic classification of
whether it is done timing driven or non-timing driven
• These strategies are:
– Scan based - whether scan is present or not
– Spare Cells based - whether spare cells are present in the design or
not
– Timing optimization requirement - whether timing optimization is
required or not and modes of optimization required
– Optimization Cells requirements - to use or not to use certain cells for
optimization
– Pre-wire keepout requirements - whether placement should be
allowed under the power stripes or not
– Region based placement - whether some cells are to be placed close
to IOs or in some region
32. Placement
• Challenges:
– Handling Multi-VT cells
• one would be required to create a different area for placing
these components since their physical features are different
• Most of the library vendors have started supporting this type
of cells as they are used for Low Power applications
– Ref: http://asic-soc.blogspot.in/2008/04/multi-threshold-mvt-
technique.html
– Handling Double-height cells
• one would be required to create a different area for placing
these components since their physical features are different
33. TERMINOLOGY
• Insertion delay - is a measure of time it takes the clock to
propagate from the root of the tree to the leaf cells
– Caused due to insertion of buffers along the clock path
– Two types - Minimum insertion delay and Maximum insertion
delay
• Skew - Spatial variation in arrival time of clock transition
• Jitter - Temporal variation of clock period at a given point
on a chip
• Transition time - slew rate of the clock
• Clock Tree Problem statement - balance the arrival time of
clock edge at the leaf pins with minimum skew making use
of the insertion delays while not compromising on the clock
transition time
34. TERMINOLOGY
• Skew - Spatial variation in arrival time of clock transition
– is the measure of the difference of delay between the minimum
and maximum time it takes the clock to reach the leaf cells
– A pair of registers are sequentially adjacent if only combinatorial
logic (no sequential elements) exist between the two cells.
– Effective skew - is the measure of the difference of delay between
the minimum and maximum time it takes the clock to reach the
leaf cells which are sequentially adjacent
– Does not change from cycle to cycle
Ri Rj
Combinational Logic
Tcomb
d q d q
clk
din dout
Ref for what is a leaf cell and other terms in the hierarchy:
http://www.rulabinsky.com/cavd/text/chap01-2.html
35. Terminology
• Jitter - temporal variation of clock period at a
given point on the chip
– Clock period changes from cycle to cycle
– Often specified at a given point
– Becoming a concern as clock frequencies are rising
– Cannot prevent it - PLL issue
36. Terminology
clk
clk with skew
clk with jitter
T
tjitter
launch edge capture edge
tskew
tsetup
thold
clk with skew & jitter
tskew
tjitter
37. Clock Equations
• Without skew and jitter
T > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold
• With Skew
T + tskew > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + tskew
• With Jitter (worst case)
T - 2tjitter > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + 2tjitter
• Combined skew and jitter effects (worst case)
T + tskew - 2tjitter > Tcomb + tpc-q + tsetup
tpc-q + Tcomb > thold + 2tjitter + tskew
39. Routing
• Design Requirement
– Timing Driven Routing
– Non Timing Driven Routing
– Routing in a particular order
• Example: Clock Nets, Critical Nets etc.
– Routing the nets on a particular layer
– Routing with Process Antenna Effect corrections
– Routing only on the grid or allow off grid routing
– Post Route optimization
– Shielded Routing
– ECO routing
– Route only specific area
40. Extraction
• The Standard Parasitic File (SPF) lists extracted electrical
data for a design created by Place and Route tools such as
Silicon Ensemble
– This extracted data consists of placed and interconnected cell
instances
• The SPF file can have one of two formats
– Detailed SPF (DSPF) format or
– Reduced SPF (RSPF) format
• Embedded in each format are two circuit level models,
each with different degrees of complexity and accuracy,
that represent the physical design
• SPEF - Standard Parasitics Extraction Format - IEEE 1481
standard
41. Capacitance - overall view
Source: Cadence - HyperExtract User's Manual
C a= Area capacitance
from the target wire
to the bottom plate
C f = Fringe (or sidewall-
to-plate) capacitance
from the target wire to
the bottom plate
C c= Sidewall coupling
(or sidewall-to-sidewall)
capacitance from the
target wire to an
adjacent parallel wire
C v= Vertical coupling (or
vertical-wall-to-vertical-
wall) capacitance from
the target wire to a wire
that aligns exactly on at
least one side on an
adjacent layer
42. Interconnect Modeling
• Prevailing models are based only on Resistance and Capacitance
• Classification
– Lumped model
• The RCs are modeled as “near cap”, “far cap” and total resistance - pi model
• Less accurate
• File handling is easier and faster since less information
– Distributed model
• PI RC network for sections of net - number of section can be controlled
• More accurate
• File handling is slower
– Extraction tools use Model Order Reduction to reduce information
without compromising on accuracy
• Elmore algorithm
• Arnoldi algorithm
43. Extraction Challenges
• Modeling inductance
– depends upon a current loop
– difficult to model only from the layout since current return
paths need not necessarily be through substrate
• Modeling process effects
– Dishing effects due to CMP (chemical mechanical polishing)
process on metals
– Trapezoidal net profiles
– ILD (inter-level dielectric) thickness variation due to CMP
process
– Interconnect profile change caused due to Optical Proximity
Correction applied during mask preparation step
– Contacts and vias have started contributing to the RC effects -
this was ignored in earlier technologies
44. Extraction - Process effects
Post-CMP ILD thickness
Features
Dummy features
Post-CMP ILD thickness
Copper Dishing Effect
Optical Proximity Correction
46. Noise and Crosstalk
• Noise and Crosstalk effects have increased due to the above net
profiles
– Together, the noise and crosstalk effects are called “SI” effects
• Capacitance components
– Parallel Plate - between the net and substrate
– Coupling - between the side-walls of the nets
CC
CC
CPP CPP CPP CPP
0.25 microns
0.13 microns
47. SI Effects
• SI effect revolves around two types of nets
– Aggressor net - the source net from where the transitions get coupled
– Victim net - the destination net which gets affected by the coupled
transition
• Crosstalk is the effects where the transition on one net (aggressor)
gets induced on to another net (victim)
• Causes two types of effects:
– Static - where victim net is quiet and only the aggressor net is
switching
• Not a concern if the induced glitch is at the input of a Flop
• Definitely a concern if the induced glitch is at the input of a combinational
logic
– Dynamic - where both, the victim and the aggressor are swicthing
• Causes timing violations
48. Static SI Effects
• Victim net is static
• If the glitch remains at the time when clock arrives, it would be
passed on to the next stage and would be a failure
• If the glitch vanishes before the clock arrives, it is not a concern
49. Dynamic SI Effects - Timing Violations
• Both, the victim net and the aggressor net are switching
• Here, the timing window is important
– If the nets are switching in the same timing window, it is a
matter of concern
– If the nets are not switching in the same window - case reduces
to static effects
• Switching within the same timing window
– If the aggressor and the victim are switching in the same
direction, it results into speeding up the signal on the victim net
- hold issue
– If the aggressor and the victim are switching in the opposite
direction, it results into slowing down of the signal on the victim
net - setup issue
51. Corrections
• The corrections can be planned upfront during
functional simulation and can be applied during
routing
• Corrections include:
– Wire Spacing
– Net Ordering and Wire Topology Control
– Layer selection to reduce coupling
– Layer selection to reduce resistance
– Minimizing parallel long wires
– Shielding
– Buffer insertion on victim
52. Corrections
Reduced coupling due to
Wider spacing
Reduced coupling due to
layer selection
Net order/ topology control Avoiding long parallel nets
54. IR Drop
• One of the most basic causes of failure in nanometer
designs is failure due to Ohm’s Law - IR Drop
• As voltage is scaling, IR drop is becoming a challenge
• Has a direct bearing on Power Distribution arrangement
• Maximum allowable IR drop is a technology measure -
around 2-3% of VDD
• Can cause IR drop induced delays
• An IR drop of 100mV caused an increase in path delays by:
– 15% in 0.25 micron technologies - VDD = 3.3V
– 55% in 0.13 micron technologies - VDD = 1V
• Correction measure is to carry out a Power aware physical
design
55. Process Antenna Effect
• This is a process effect - caused at the time of fabrication
• It is an “immediate” reliability issue
• Causes dielectric breakdown of the gate of a transistor
thereby destroying it - corresponding gate will be shorted
to channel
• Caused by accumulation of charge on an interconnect at
the time of fabrication
• This charge is generated during the processes like Ion
Etching or Chemical Mechanical Polishing etc.
• If the amount of charge collected on a net exceeds the gate
capability the gate oxide breaks down leading to short
circuit between gate and the channel
56. Process Antenna Effect
• Has been successfully modeled in library as well as
tools
• Library
– has parameters like:
• Antenna Gate Area Ratio: which is the ratio of Gate area to area of
the Net connected to the gate
• Antenna Diffusion Area Ratio: which is the ratio of Diffusion area
to area of the Net connected to the gate
• and so on
• Tool - routers
– Routers are built with PAE correction mechanism
• through Diode insertion
• Through layer hopping - re-ordering of metal layers of a net
57. Electromigration
• Electromigration is a long term reliability issue
• This is the effect where the wire heats up and breaks (fuses)
• Can cause voids (open circuit) at one end and hillocks (shorts) at the
other end
58. Electromigration
• Current flow in a normal housing wire is limited to 104 A/cm2 as it is
limited due to Joule heating effect
• In a semiconductor this limit is 1010 A/cm2 - due to good heat-
sinking
• If the current exceeds the above limit, the wire heats up and fuses
• This is the effect of electromigration
• Electromigration is caused by transport of diffusion atoms by flow
of current in a wire
• Definition: (Arzt and Nix, 1991)
– Electromigration is considered to be the result of momentum transfer
from the electrons, which move in the applied electric field, to the
ions which make up the lattice of the interconnect material
59. Electromigration
• Cause:
– Ions make up a crystal lattice which in turn make up a metal
– These ions vibrate due to several reasons - thermal energy is one of
the reasons
– Some ions can shift from their positions in the lattice - due to internal
vibration of the ions
– If the shift coincides with the flow of electrons these ions are carried
away - resulting into mass transfer
• Electromigration causes voids at the source point and hillocks at the
destination point of the current flow
• The electromigration effect is accelerated due to imperfection in
the interconnect microstructure - that is the reason Cu is preferred
over Al as an interconnect nowadays
60. Electromigration
• It is a regenerative effect as seen from the
figure
Growth of voids
Increase of local
current density
Increase of
heating
Increase of
temperature
61. Project Execution
•Design:
•Micro-architecture definition
•RTL coding in verilog
•Integration
•Verification
•Test environment design and coding
•System test plan generation & verification
•Synthesis and STA
•Synthesis (RC)
•Formal verification (Conformal), STA (ETS)
•PD
•Cadence flow for Digital and Analog physical design
•FE, QRC, VSPE, ETS and Virtuoso XL
•DFT – Encounter Test
•Scan, ATPG for the digital block
•Test IO pins for testing system
•Methodology – hierarchical
Chip Features
•Target Technology :90nm - Fujitsu
•Die Size : 2.5mm X 2.5mm
•Gate Count : 250K (no embedded memories)
•Frequency : 2 domains 696MHz, 232MHz
(Sigma Delta: 1.6GHz)
•Team size : 2 verification, 1 Physical Design and
1 DFT engineers, 4 Analog design
engineers, 4 analog layout engineers
•Project Duration : 6 months
DigitalCore DigitalTop
Case Study – 90nm TV Tuner
62. Case Study – 28nm Networking Chip
• Design Parameters
– 28nm TSMC HPM
– 1Ghz Core Clock
– 800 MHz Serdes Logic Clock
– 25G Hz Serdes Internal Freq
– 25mm x 25mm Die Size
– Flip Chip
– 180 SERDES Instances
– 50 unique Blocks
– 140W - Die Power
• Program Size
– PnR : 25 Engineers ( Including Leads )
– 9 Months Execution ( 2 Phases )
– Final Netlist Phase : 2.5 months ( 1.5 months
Blocks, 1 Month Top )
• Methodology
– Full Hierarchical implementation
– Mesh Clock Implementation
– All Feedthrough paths are implements are
repeater islands to isolate the Top & Block
Level dependencies
– Max block Size 3M instance count
– Max IO block size : 1.2M instance count
– Synthesis - DC Topo/DC-SPG
– PnR Implementation – ICC ( IO Blocks ),
Talus (Core Blocks)
– Formal Verification Sign-off : LEC
– Timing / Noise Sign-off : PTSI
– Power Analysis Sign-off : Redhawk
– Physical verification Signoff : calibre
– Vt based Timing / Power recovery
• Sign-off Parameters
– Modes : Core Block : 2 Modes, IO Blocks – 12
Modes
– Timing Corners : 3 – Process, 2 –Temp, 4 –
voltage, 4 – RC, 2- RC Temp
– Setup Fix scenario : 8
– Hold Fix scenario : 9
– Nosie : ff, rcbest, 125C
– OCV : Setup – 10% capture Clock Cells. 10%
capture Clock Nets
• Hold : 15% Launch Clock Cells , 15% Capture Clock
Cells , 20% Launch Clock Nets , 20% capture Clock Netss
– Sign-off Margin : 40ps Hold , 160ps setup
– IR Drop : 60mV ( Dynamic Vector-less worst
case Activity Based Analysis )
– 5% LVT Count
64. Moving Forward
• Steps being studied and undertaken
– Unified Data Model between the tool vendors - remote chances!!
• Difficult since the algorithms used in the tools are different and cannot be
merged
– Common libraries between the tools
• This step has matured over the last few years and today we have to deal with
LEF and LIB format only
• However, these formats are tool vendor specific - LEF: Cadence and LIB:
Synopsys and are not standards
– Subject to unilateral modifications
• Industry working towards ALF (Advanced Library Format) which is an IEEE
standard - IEEE1603 - 2003
– Models timing, power, SI, synthesis and physical library views
– Manufacturing aware Physical Design
• Design For Manufacturing is the new Mantra!!