This document summarizes a research paper on implementing a low power design methodology for recursive encoders and decoders. It discusses how recursive coding can achieve better error correction performance at low signal-to-noise ratios compared to other codes. It then describes the design of a recursive decoder that uses the log-MAP algorithm to minimize power consumption. The decoder uses five main computational steps - branch metric calculation, forward metric computation, backward metric computation, log-likelihood ratio calculation, and extrinsic information calculation. It also compares the implementation of four-state and eight-state recursive encoders. The goal of the design is to optimize the power and area of recursive encoders and decoders.
A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEMVLSICS Design
Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEMVLSICS Design
Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Hardware Implementations of RS Decoding Algorithm for Multi-Gb/s Communicatio...RSIS International
In this paper, we have designed the VLSI hardware for a novel RS decoding algorithm suitable for Multi-Gb/s Communication Systems. Through this paper we show that the performance benefit of the algorithm is truly witnessed when implemented in hardware thus avoiding the extra processing time of Fetch-Decode-Execute cycle of traditional microprocessor based computing systems. The new algorithm with less time complexity combined with its application specific hardware implementation makes it suitable for high speed real-time systems with hard timing constraints. The design is implemented as a digital hardware using VHDL
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Stochastic Computing Correlation Utilization in Convolutional Neural Network ...TELKOMNIKA JOURNAL
In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work.
A novel technique for speech encryption based on k-means clustering and quant...journalBEEI
In information transmission such as speech information, higher security and confidentiality are specially required. Therefore, data encryption is a pre-requisite for a secure communication system to protect such information from unauthorized access. A new algorithm for speech encryption is introduced in this paper. It depends on the quantum chaotic map and k-means clustering, which are employed in keys generation. Also, two stages of scrambling were used: the first relied on bits using the proposed algorithm (binary representation scrambling BiRS) and the second relied on k-means using the proposed algorithm (block representation scrambling BlRS). The objective test used statistical analysis measures (signal-to-noise-ratio, segmental signal-to-noise-ratio, frequency-weighted signal-to-noise ratio, correlation coefficient, log-likelihood ratio) applied to evaluate the proposed system. Via MATLAB simulations, it is shown that the proposed technique is secure, reliable and efficient to be implemented in secure speech communication, as well as also being characterized by high clarity of the recovered speech signal.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration
for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the
IoT network scenario considered in the work, for the same coding rate and the number of decoding
iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective
fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to
polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large
number of decoding iterations and high coding rates.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct_journal
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the IoT network scenario considered in the work, for the same coding rate and the number of decoding iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large number of decoding iterations and high coding rates.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Hardware Architecture of Complex K-best MIMO DecoderCSCJournals
This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for MIMO and 64 QAM modulation scheme. Use of Schnorr-Euchner (SE) enumeration and a new parameter, Rlimit in the design reduce the complexity of calculating K-best nodes to a certain level with increased performance. The total word length of only 16 bits has been adopted for the hardware design limiting the bit error rate (BER) degradation to 0.3 dB with list size, K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 782 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Low complexity design of non binary ldpc decoder using extended min-sum algor...eSAT Journals
Abstract
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon’s limit. Nonbinary
LDPC is the class of binary LDPC, which works on the higher order Galois field. The decoding performance of non-binary
(NB) LDPC is better than binary LDPC for moderate code lengths. The increased computation with the increased order of field is
the major challenge in hardware realization of NB-LDPC. The extension of conventional sum-product algorithm, known as
extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper. However, a tradeoff exists
between computational complexity and decoding performance.
This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The
bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm
can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Keywords—Non-binary; LDPC; EMS algorithm; PCM
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
Abstract
Low complexity and power consumption are the key concerns while designing reconfigurable pulse shaping FIR filter for multistandard wireless communication system. In FIR filter, the single input to be multiplied by a set of coefficients known as multiple constant multiplications. This multiple constant multiplication becomes an obstruction in many applications. To overcome that, Digit Based Recoding, Canonic Sign Digit, Common Subexpression Elimination and Binary Common Subexpression Elimination algorithms are used to optimize the number of addition and subtraction operations. While designing these MCM algorithms in the architecture of RRC FIR filter, Binary Common Subexpression Elimination (BCSE) algorithm provides the better performance in terms of area and power.
Keywords: Multiple Constant Multiplication (MCM), Root Raised Cosine Filter (RRC), Canonic Sign Digit (CSD), Multiple Sign Digit (MSD), Common Subexpression Elimination (CSE)
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementationinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Chaos Encryption and Coding for Image Transmission over Noisy Channelsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Stochastic Computing Correlation Utilization in Convolutional Neural Network ...TELKOMNIKA JOURNAL
In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work.
A novel technique for speech encryption based on k-means clustering and quant...journalBEEI
In information transmission such as speech information, higher security and confidentiality are specially required. Therefore, data encryption is a pre-requisite for a secure communication system to protect such information from unauthorized access. A new algorithm for speech encryption is introduced in this paper. It depends on the quantum chaotic map and k-means clustering, which are employed in keys generation. Also, two stages of scrambling were used: the first relied on bits using the proposed algorithm (binary representation scrambling BiRS) and the second relied on k-means using the proposed algorithm (block representation scrambling BlRS). The objective test used statistical analysis measures (signal-to-noise-ratio, segmental signal-to-noise-ratio, frequency-weighted signal-to-noise ratio, correlation coefficient, log-likelihood ratio) applied to evaluate the proposed system. Via MATLAB simulations, it is shown that the proposed technique is secure, reliable and efficient to be implemented in secure speech communication, as well as also being characterized by high clarity of the recovered speech signal.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration
for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the
IoT network scenario considered in the work, for the same coding rate and the number of decoding
iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective
fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to
polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large
number of decoding iterations and high coding rates.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct_journal
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the IoT network scenario considered in the work, for the same coding rate and the number of decoding iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large number of decoding iterations and high coding rates.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Hardware Architecture of Complex K-best MIMO DecoderCSCJournals
This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for MIMO and 64 QAM modulation scheme. Use of Schnorr-Euchner (SE) enumeration and a new parameter, Rlimit in the design reduce the complexity of calculating K-best nodes to a certain level with increased performance. The total word length of only 16 bits has been adopted for the hardware design limiting the bit error rate (BER) degradation to 0.3 dB with list size, K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 782 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Low complexity design of non binary ldpc decoder using extended min-sum algor...eSAT Journals
Abstract
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon’s limit. Nonbinary
LDPC is the class of binary LDPC, which works on the higher order Galois field. The decoding performance of non-binary
(NB) LDPC is better than binary LDPC for moderate code lengths. The increased computation with the increased order of field is
the major challenge in hardware realization of NB-LDPC. The extension of conventional sum-product algorithm, known as
extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper. However, a tradeoff exists
between computational complexity and decoding performance.
This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The
bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm
can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Keywords—Non-binary; LDPC; EMS algorithm; PCM
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
Abstract
Low complexity and power consumption are the key concerns while designing reconfigurable pulse shaping FIR filter for multistandard wireless communication system. In FIR filter, the single input to be multiplied by a set of coefficients known as multiple constant multiplications. This multiple constant multiplication becomes an obstruction in many applications. To overcome that, Digit Based Recoding, Canonic Sign Digit, Common Subexpression Elimination and Binary Common Subexpression Elimination algorithms are used to optimize the number of addition and subtraction operations. While designing these MCM algorithms in the architecture of RRC FIR filter, Binary Common Subexpression Elimination (BCSE) algorithm provides the better performance in terms of area and power.
Keywords: Multiple Constant Multiplication (MCM), Root Raised Cosine Filter (RRC), Canonic Sign Digit (CSD), Multiple Sign Digit (MSD), Common Subexpression Elimination (CSE)
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
Belief Propagation Decoder for LDPC Codes Based on VLSI Implementationinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Chaos Encryption and Coding for Image Transmission over Noisy Channelsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
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DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
Here are the elements you need to get back again when your rankings went down. All these onsite and offsite factors are important in making your website rank.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
This paper presents the bit error rate performance of the low density parity check (LDPC) with the concatenation of convolutional channel coding based orthogonal frequency-division-multiplexing (OFDM) using space time block coded (STBC). The OFDM wireless communication system incorporates 3/4rated convolutional encoder under various digital modulations (BPSK, QPSK and QAM) over an additative white gaussian noise (AWGN) and fading (Raleigh and Rician) channels. At the receiving section of the simulated system, Maximum Ratio combining (MRC) channel equalization technique has been implemented to extract transmitted symbols without enhancing noise power.
Improving The Performance of Viterbi Decoder using Window System IJECEIAES
An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmIJERA Editor
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
Iterative network channel decoding with cooperative space-time transmissionijasuc
One of the most efficient methods of exploiting space diversity for portable wireless devices is cooperative
communication utilizing space-time block codes. In cooperative communication, users besides
communicating their own information, also relay the information of other users. In this paper we
investigate a scheme where cooperation is achieved using two methods, namely, distributed space-time
coding and network coding. Two cooperating users utilize Alamouti space time code for inter-user
cooperation and in addition utilize a third relay which performs network coding. The third relay does not
have any of its information to be sent. In this paper we propose a scheme utilizing convolutional code based
network coding, instead of conventional XOR based network code and utilize iterative joint networkchannel
decoder for efficient decoding. Extrinsic information transfer (EXIT) chart analysis is performed to
investigate the convergence property of the proposed decoder.
FPGA Implementation of Soft Output Viterbi Algorithm Using Memoryless Hybrid ...VLSICS Design
The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.
Convolutional encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. Fangled Viterbi decoders are variants of Viterbi decoder (VD) which decodes quicker and takes less memory with no error detection capability. Modified fangled takes it a step further by gaining one bit error correction and detection capability at the cost of doubling the computational complexity and processing time. A new efficient fangled Viterbi algorithm is proposed in this paper with less complexity and processing time along with 2 bit error correction capabilities. For 1 bit error correction for 14 bit input data, when compared with Modified fangled Viterbi decoder, computational complexity has come down by 36-43% and processing delay was halved. For a 2 bit error correction, when compared with Modified fangled decoder computational complexity decreased by 22-36%.
FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID ...VLSICS Design
The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
n this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms.
Similar to ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODEL (20)
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
At WSTS 2024, Alon Stern explored the topic of parametric holdover and explained how recent research findings can be implemented in real-world PNT networks to achieve 100 nanoseconds of accuracy for up to 100 days.
Enhancing Performance with Globus and the Science DMZGlobus
ESnet has led the way in helping national facilities—and many other institutions in the research community—configure Science DMZs and troubleshoot network issues to maximize data transfer performance. In this talk we will present a summary of approaches and tips for getting the most out of your network infrastructure using Globus Connect Server.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Welcome to the first live UiPath Community Day Dubai! Join us for this unique occasion to meet our local and global UiPath Community and leaders. You will get a full view of the MEA region's automation landscape and the AI Powered automation technology capabilities of UiPath. Also, hosted by our local partners Marc Ellis, you will enjoy a half-day packed with industry insights and automation peers networking.
📕 Curious on our agenda? Wait no more!
10:00 Welcome note - UiPath Community in Dubai
Lovely Sinha, UiPath Community Chapter Leader, UiPath MVPx3, Hyper-automation Consultant, First Abu Dhabi Bank
10:20 A UiPath cross-region MEA overview
Ashraf El Zarka, VP and Managing Director MEA, UiPath
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11:15 The UiPath approach to GenAI with our three principles: improve accuracy, supercharge productivity, and automate more
Boris Krumrey, Global VP, Automation Innovation, UiPath
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Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Accelerate your Kubernetes clusters with Varnish Caching
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODEL
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
DOI : 10.5121/vlsic.2013.4402 9
ANALOG MODELING OF RECURSIVE
ESTIMATOR DESIGN WITH FILTER DESIGN
MODEL
R. Rajendra prasad1
Dr.M.V.Subramanyam 2
Dr.K.Satya Prasad3
1
Asso.professor of ECE Department, N.B.K.R.Institute of science and technology,
Vidyanagar, S.P.S.R.Nellore, Andhra Pradesh, India.
Rajendra_831@yahoo.co.in,rechalabhi812@gmail.com
2
Principal and Professor of ECE Department,
Santhi Ram Engineering College, Nandyal, India.
mvsraj@yahoo.com
3
Professor of ECE Department and Rector, JNTU Kakinada, Kakinada, India.
prasad_kodati@yahoo.co.in
ABSTRACT
The low power solution for developing the application specific design methodologies using recursive
coding had become central topic of modern research .In 3G mobile communication systems, in order to
achieve low power consumption and high speed at low cost design. This paper focuses on implementing a
design methodology using recursive encoder /decoder for optimizing the power and area and analyzing the
performance interms of bit error rate (BER).
KEYWORDS
Power Optimization, Recursive Encoder/Decoder, low power design,
1. INTRODUCTION
In today’s modern and competitive world as there is lot of advancements in research. Many
application specific designs at various abstraction levels have been proposed in order to provide
cost effective and efficient solutions. Special portable applications such as cellular phones,
laptops and modems. The main criteria in these applications are maximizing the battery life by
minimizing the power consumption [1, 2].
In digital integrated circuits, there is an enormous technological need of low power design [1]. The
importance of power limiting and estimating the power consumption at different levels is described
in [3-16]. The power estimation will help in improving the efficiency at various levels of design.
There will be great impact on saving power at the lower level abstractions like circuit level and
transistor level. Without illustrating brief about register transfer logic architecture, some
researchers proposed a DSP design methodology in behavioral level starting from entry level to
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
10
algorithmic level. They propose a design methodology using communication applications for
performance analysis.
In 1993 recursive codes were presented. In the research society, recursive codes gathered
enormous interest among researchers because of its high performance in low signal to noise ratio
(SNR) in comparison to other codes. There will be lot of pressure in implementing these
technologies in advance third generation (3G) systems and beyond. to limiting power the objective
was to implement complex algorithms for limiting power consumption. Recursive coding is a
forward error correction (FEC) scheme. Iterative decoding is the key feature of recursive codes
[17, 18]. Recursive codes consist of concatenation of two convolution codes. To achieve high
performance the [19, 20] proposed recursive codes and analyzed that the performance of
recursive codes is better at low signal to noise ratio (SNR). Interestingly, the name Recursive was
given to these codes because of the cyclic feedback mechanism (as in Recursive machines) to the
decoders in an iterative manner. Recursive codes with short delay are being heavily researched.
When the interleavers exceeds 200 bit length [21] proposed recursive coding whose performance
is much better than the conventional convolution al and block codes. Similarly the [22] author
proposed a device equipped with 32x32-bit interleaver to achieve high performance than the
conventional concatenated codes with outer code using reed –Solomon and inner code using
convolution code. Power minimization is an important aspect in remote areas so [23] proposed
recursive coding for power minimization. Recursive algorithm are similar to that of the above two
methods i.e. [21] and [22]. One aspect which differs between them is interleaving algorithm
whose allowable input range and rate of constituent RSC encoders [24].
There are three types of algorithms used in recursive decoder namely MAP, Max-Log-MAP and
Log-MAP. In order to minimize the probability of bit error MAP algorithm is used which results in
high complexity and instability. This result in higher power consumption in coding and also
requires larger area coverage to process. The solution to overcome the above mention problem is
to operate in log-domain. The reason behind using is that the multiplication becomes addition and
also a correction term in log domain and can be useful for maximization. So Max-Log-MAP
algorithm in recursive decoder is used in this work. The approach of designing the recursive code
or low power objective in logarithmic domain is focused and a evaluation on the consumption of
power for such an operation is suggested.
2. SYSTEM DESIGN
For the implementation of a log-Max MAP approach a coding and decoding approach is been
suggested. The computational complexity of the design unit is reduced by the optimal realization
of the decoding approach in 5 distinct operations. The operation performed for the operation is as
outlined in the following section. The objective of the iterative decoding algorithm is used to
calculate the posteriori probability (APP) of the information symbols which shows the reliability
of the each symbol.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
11
Figure 1: Decoder Schematic Diagram
There are five main computations to be performed during each iteration in the decoding stage as
shown in the figure above.
1) Branch metric calculation
By using eqn. (1) one can calculate the branch metric and the branch metric is represented by
states. Each state has two branches. As there are four states total eight branch metrics and each
branch need to be calculated which is given by below eqn. (1)
…… Eqn. (1)
Where [k] is the branch metric at time k, [k] are the systematic bits of information with frame-
length N, [k] is the information that is fed back from one decoder to the other decoder, Lc is the
channel estimate which corresponds to the maximum signal to distortion ratio, is the encoded
parity bits of the encoder, xs[k] is the noisy observed values of the encoded parity bits and xp[k] is
the observed values of the encoded systematic bits.
2) Forward metric computation
The second computation step of decoding algorithm is the forward metric. The forward metric
can be calculated from eqn.(2) which signify the probability of a state at time k, with the
probabilities of states at previous time instance.
------Eqn. (2)
At a time instance K at each node the forward direction traversing for states 00,01,10,11 need to
be calculated from the eqn. (2).Where the summation represents the total state transitions.
3) Backward metric unit
The third computational step of decoding algorithm is the backward metric the back metric can be
calculated by using eqn.(3) in the backward direction. .The backward metric represents the
probability of the state at each time k and the future received symbols, is recursively evaluated and
stored
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
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------Eqn. (3)
In a 4 state decoder, βs’ represents the state transition is calculated from states 00, 01, 10, 11. In
an 8 state decoder - for states 000, 001,010, 011, 100, 101, 110 and 111 the 3GPP version is
calculated.
4) Log likelihood ratio (lr)
The fourth computational step of the algorithm is Log likelihood ratio llr. The recursive decoder
output is llr. At time k, llr ouput for each symbol is calculated by below eqn. (4)
----Eqn. (4)
Where input message bit is represented by U[k] 1. The numerator part in the eqn.(4) represents the
summation of over all the states from S’ to S in γ[k]. The γ values, α unit output and the β
values obtained from the above steps are used to compute the llr values. The log likelihood ratio
llr[k] for each γ[k] is computed. The reliability can be estimated using magnitude and the sign
correspond to the hard decision
5) Extrinsic unit
In the extrinsic unit, extrinsic information need to be estimated which is given to the next decoder
based on the order of iteration. The extrinsic information represented by ext[k-1] is computed by
using log likelihood ratio given by llr[k-1] and subtracted the weighted channel systematic bits.
The obtained information is fed to the other decoder.
The four state and 8 eight state encoders are implemented so as to analyze the performance by
comparing the characteristics of both encoders. The difference between the four state and eight state
encoder is the usage of memory elements that each encoder utilizes. The four state encoder utilizes
two memory elements where as the eight state encoder utilizes three memory elements. This is the
encoder that is specified in the 3GPP standards.
Figure 2: The 8 state encoder – 3GPP version
3. DESIGN MODULES
As soon as the decoding commences, the encoded data information is demultiplexed and separated
into the systematic received data (ys), parity data elements from the encoder1 (yp1) and the parity
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
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data values from the encoder2 (yp2).the information is then processed by a unit called
interleaving unit. The output data of the interleaving process is provided as an input to the
decoder units. The data is segregated with the help of data supply unit and provides the required
input for the decoder1 and decoder 2 units.
Now the decoder 1 and decoder 2 are set for processing.
1) Decoder1
The decoder1 unit consist of the following blocks such γ, α, β, llr, extrinsic unit, intermediate
storage units with associated feedback units, such as extrinsic interleaver and its storage units. By
using FIFO/LIFO the storage units are modeled and pattern analysis is used for accessing the data
which was illustrated in the previous chapter.
2) Decoder2
As decoder2 has similar block that were used in decoder1, except inputs are different in the
computational blocks the ther difference between the decoder 1 and decoder2 is tat the decoder2
is equipped with an additional decision unit which is not present in the decoder1. The
functionality of the decision units is it gives the final estimation values of the retrieved
message..In order to process the next iteration the output of decoder2 is stored and fed back to the
decoder1.
B) Selector module
In order to carry the processing of second iteration to the sixth iteration a specific selector module
in the recursive decoder is required. Decoder receives the encoded data as an input. During first
iteration, The encoded data is multiplexed and generates respective parity bits and then data is
proceed to interleaving process. After the completion of the interleaving process is data is stored.
This process continues for the second till sixth iteration for decoder1 and decoder2. During first
iteration the selector module (multiplexer) collect the input signal from the data and provides a
start signal to the decoder1 (unit). During the successive iterations, the input signal is collected by
the selector module from the last computational unit and gives a start signal to the enable the
decoder2 (extrinsic interleaver unit) unit.
C) FSM Controller Unit
The process of the proposed recursive decoder is controlled and managed by a unit called Finite
state machine (FSM) controller unit. The proposed recursive decoder unit consist of two decoder
with six iteration to perform it operation. In order to control and manages the set of states, Finite
state machine (FSM) is required. In recursive decoder, for each iteration, A transition signal is
moved from present state to next state. In the recursive decoder the data computation and the
iteration control are differentiated by the FSM, which has a typical algorithmic behavior.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
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Figure 3: State diagram representation of FSM used in the recursive decoder design
Figure 3 depicts the state diagram of the FSM used in the recursive decoder design to control the
number of iterations. In FSM of the recursive decoder design the there are six states S0 to S5. The
first iteration starts from state S0 which represents the initial state of the FSM of the recursive
decoder design. As there are six states, it requires six iteration where the data need to be received
by each stage and get processed. Based on the value of the frame start signal, the decoding process
either enables or disable. If the value of the frame start signal is zero (low) then the decoding
process of the decoder is disabled. If the value of the frame start signal is one (high) then the
decoding process of the decoder enable. Based on the number of iteration the signal of the decoder
unit is send to next state and is controlled by the FSM unit. In order to The recursive decoder
module requires many memory modules in its design, so as to facilitate the opportunity from
which memory location, the data need to read or write with appropriate conditions is specified in
the module. In Xilinx, during systhesis process the internal RAM memory of VirtexII device is
used for realizing the modules.
4. RESULT ANALYSIS
The proposed design is modeled in active HDL and synthesized in Xilinx synthesizer. For power
analysis the Xpower analyzer in xilinx helps in evaluating the power by reading the pre-routed
and post routed design data of the device. By using the 0.18m technology the estimated voltage
of the design is 2.5V. There is a provision to give a specific switching activity for the design power
estimation. The estimates for 20 and 50 activity factor are found. Xpower analyzer of the Xilinx
tool one can calculate the power of each element in the design or total power consumed by the
whole design.The estimated power consumed is product of capacitance, square of the voltage,
activity factor and frequency of operation and its units are mW.
Figure 4: simulation observation illustrating timing result for the developed encoding unit
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
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Figure 5: simulation timing observation for the decoding logic developed for the implemented system.
For the realization of the developed logic and its evaluation in physical environment in this work
the developed system is synthesized on Xilinx ISE synthesizer targeting on to virtex2p device
part number 2vp100ff1696-6. The obtained parameter for this device is given below,
Design Statistics: # IOs : 19
Cell Usage : # BELS : 6549
Maximum Frequency: 141.012MHz
Figure 6: obtained RTL realization for the encoding unit
Figure 7. The routed logical operation for the developed system onto the targeted FPGA device.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
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Figure 8. Logical placement of the logical blocks on a targeted FPGA logic.
The summarized observation for different targeted FPGA devices were outlined below,
5. CONCLUSION
Based on memory issues, this paper proposed a an application specifc design methodology by
using low power design techniques. In communication system for achieving low power
consumption using low cost design an recursive coding is used in forward error correction
channel coding. Recursive coding uses three steps 1. For simplified decoding, parallel
concatenation of codes is allowed. For better weight distribution an interleaving concept is
introduced and to maximize the gain of the decoder a soft decoding is used for improving decoder
decisions. The proposed methodology developed in Active HDl and evaluated the performance
using Xilinx synthesizer. By using different target devices of PLD’s, the proposed method is
evaluated. The target devices varies from 37.2-43.32mw of power and 131.223 – 167.320MHz of
frequency variation.
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