Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
A 0.6-V 2-nA CMOS Current Reference CircuitIJERA Editor
This paper proposes a 0.6-V current reference circuit for use in ultra-low-power applications. In a conventional resistorlessbeta-multiplier current reference circuit, a MOSFET that operates in the strong inversion and triode regions is used as a resistor. Our proposed circuit provides a forward body-biasing for the MOSFET to lower its threshold voltage and make it operate in its strong inversion region even at a very low supply voltage of 0.6 V.We ran simulations using BSIM3v3 SPICE parameters for a 0.18-m standard CMOS process. At a supply voltage of 0.6V, the reference current was 2nA. The chip area of the proposed current reference circuit was 0.022 mm2
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
A 0.6-V 2-nA CMOS Current Reference CircuitIJERA Editor
This paper proposes a 0.6-V current reference circuit for use in ultra-low-power applications. In a conventional resistorlessbeta-multiplier current reference circuit, a MOSFET that operates in the strong inversion and triode regions is used as a resistor. Our proposed circuit provides a forward body-biasing for the MOSFET to lower its threshold voltage and make it operate in its strong inversion region even at a very low supply voltage of 0.6 V.We ran simulations using BSIM3v3 SPICE parameters for a 0.18-m standard CMOS process. At a supply voltage of 0.6V, the reference current was 2nA. The chip area of the proposed current reference circuit was 0.022 mm2
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
energy conversion systems and electric drives. Both these systems are based
on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs)
and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
makes the PWM inverter more efficient.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Digital Implementation of DSVPWM Control for EV fed through Impedance Source ...IAES-IJPEDS
In this paper, a new space vector modulation technique is proposed for speed
control of Induction Motor using Z-source inverter powered by a low voltage
DC source. The zero states of conventional space vector modulation are used
for boosting the DC-link voltage to the required level. The proposed SVM
technique estimates the required shoot through period of the Z-source
inverter to maintain the DC-link voltage constant at the desired level through
capacitor voltage control. A 32 bit DSP (TMS320F28335) is used to
implement the proposed space vector modulation method. The power
structure and the modulation technique is well suited for electric vehicle
application.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
A Single-Stage High-Frequency Isolated Secondary- Side Controlled AC-DC Conve...IDES Editor
This paper presents a new single-stage highfrequency
isolated ac-dc converter that uses a simple control
circuit. It is well suitable for wide input variation power
sources. The circuit configuration combines a diode rectifier,
boost converter and half-bridge dc-dc resonant converter. A
high power factor is achieved by discontinuous current mode
(DCM) operation of the front-end integrated power factor
correction circuit. The output voltage is regulated by fixedfrequency,
secondary-side phase-shift active rectifier. Softswitching
operation is achieved for all the switches. This
converter operates in three modes, which is classified
according to conduction of different switches and diodes. The
intervals of operation and steady-state analysis are presented
in detail. Design example of a 100 W proposed converter is
given together with its simulation and experiment results for
wide variation in input voltage.
Analsis of very fast transient over voltages in gas insulated substationseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillatorIJECEIAES
The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal– oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.
42 30 nA Comparative Study of Power Semiconductor Devices for Industrial PWM ...IAES-IJPEDS
The growing demand of energy translates into efficiency requirements of
energy conversion systems and electric drives. Both these systems are based
on Pulse Width Modulation (PWM) Inverter. In this paper we firstly present
the state of art of the main types of semiconductors devices for Industrial
PWM Inverter. In particular we examine the last generations of Silicon
Carbide (SiC) MOSFETs and Insulated Gate Bipolar Transistors (IGBTs)
and we present a comparison between these devices, obtained by SPICE
simulations, both for static characteristics at different temperatures and for
dynamic ones at different gate resistance, in order to identify the one which
makes the PWM inverter more efficient.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Digital Implementation of DSVPWM Control for EV fed through Impedance Source ...IAES-IJPEDS
In this paper, a new space vector modulation technique is proposed for speed
control of Induction Motor using Z-source inverter powered by a low voltage
DC source. The zero states of conventional space vector modulation are used
for boosting the DC-link voltage to the required level. The proposed SVM
technique estimates the required shoot through period of the Z-source
inverter to maintain the DC-link voltage constant at the desired level through
capacitor voltage control. A 32 bit DSP (TMS320F28335) is used to
implement the proposed space vector modulation method. The power
structure and the modulation technique is well suited for electric vehicle
application.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
A Single-Stage High-Frequency Isolated Secondary- Side Controlled AC-DC Conve...IDES Editor
This paper presents a new single-stage highfrequency
isolated ac-dc converter that uses a simple control
circuit. It is well suitable for wide input variation power
sources. The circuit configuration combines a diode rectifier,
boost converter and half-bridge dc-dc resonant converter. A
high power factor is achieved by discontinuous current mode
(DCM) operation of the front-end integrated power factor
correction circuit. The output voltage is regulated by fixedfrequency,
secondary-side phase-shift active rectifier. Softswitching
operation is achieved for all the switches. This
converter operates in three modes, which is classified
according to conduction of different switches and diodes. The
intervals of operation and steady-state analysis are presented
in detail. Design example of a 100 W proposed converter is
given together with its simulation and experiment results for
wide variation in input voltage.
Analsis of very fast transient over voltages in gas insulated substationseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillatorIJECEIAES
The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal– oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
Dual-Level Adaptive Supply Voltage System with Bandgap Reference MPR for Vari...IJERA Editor
Nowadays VLSI circuits have become much advanced by overcoming many challenges such as extra power
consumption, but circuit aging along with process variations are still challenging the advancements in power
efficient VLSI circuits. The aim of this dissertation is to propose the new adaptive technique to efficiently
compensate the fine grained variations by addressing the limitations in existing adaption approach. Adaptive
supply voltage (ASV) is proved to be one among the top most adaptation approaches in tuning of power
performance. Controlling power leakage is the main advantage in using ASV, while delivery overheads along
with voltage generation from conventional ASV systems make their application to mitigate fine-grained
variations demanding. The main aim of this dissertation is to present a dual level ASV system with band gap
reference Miniature programmable regulator (BGRMPR). Reference voltage independent of process and
temperature variations can be achieved because of using band gap reference voltage. Another advantage of
adapting this approach is because less power is consumed by system when compared to dual-level ASV system
with MPR.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
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An Approach to Detecting Writing Styles Based on Clustering Techniques
Authors:
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-Shweta Ambekar
-Harshit Singh
-Nakul Sharma (Assistant Professor)
Institution:
VIIT Pune, India
Abstract:
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A High-Swing OTA with wide Linearity for design of self-tunable linear resistor
1. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
DOI :10.5121/vlsic.2010.1301 1
A High-Swing OTA with wide Linearity for design
of self-tunable linear resistor
Nikhil Raj, R.K.Sharma
Department of Electronics and Communication Engineering
National Institute of Technology, Kurukshetra
Haryana, 136119, India
nikhilquick@gmail.com, mail2drrks@gmail.com
ABSTRACT
Low power consumption, long battery life and portability are essential requirements of modern health
monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is
an basic building block for low power health monitoring products design. An modified design of OTA
which incorporates better linearity and increased output impedance has been discussed in this paper. The
proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency
applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at
power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low
voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The
circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM
3v3 level-53 model parameter and verified results through use of ELDO Simulator.
KEYWORDS
Bulk-input, Wilson mirror, Linear range, MOS resistor
1. Introduction
Device sizing is the latest trend in VLSI. Scaling down the channel length in CMOS technology
facilitates the submicrometer devices on single IC. Battery operated devices in medical electronics
like Ambulatory Brain Computer Interface (ABCI) systems, insulin pumps, hearing aids
essentially require low power designs using submicron devices.
Such rapid increase use of battery-operated portable equipment is realized with VLSI (very
large scale integrated) technologies. As the technology of biomedical instrumentation amplifier is
moving towards portability, lower power consumption is highly desirable for devices which
monitors patient whole day.
Small amplitude and low frequency range are special features of biological signals like ECG. In
order to process these signals low pass filters are used with sufficient large time constant, typically
for a capacitor value of less than 5pF which in turn require very high resistance. For example, in
ECG signal detection, low-pass filter required must have cut-off frequency less than 300 Hz for
which use of low-power continuous-time OTA-based filters are preferred [1]. However, major
limitation of conventional OTAs is its limited linear range. As device sizes are scaling down,
traditional saturation-based OTAs are facing design challenges to overcome poor linearity and
limited output impedance. Various techniques for extending linear range have been proposed
2. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
2
among which one is based on source-degeneration and multitanh principle [2]. An alternative
method forces to employ diodes as source degeneration elements to extend the linear range [3], but
using stacked diodes in series as degeneration elements increases the need of supply voltage. In
[4], the OTA uses 21-transistor operating in subthreshold mode gives a linear range of about 700
mV. Since the OTA is a current source device, the output impedance of the device must be high.
This work uses the OTA circuit proposed in [5] as reference. The current mirror part of this OTA
has been replaced with High-swing improved-Wilson current mirror circuit. The simulation of
modified OTA proved considerable improvements in linearity (upto 1.9 volt) as well as sufficient
increase in output impedance.
The proposed work has been organized into four sections. Section 2 covers detailed description
on working of proposed OTA; based on principle of bulk-driven MOS transistors. Section 3 is
detailed on implementation of modified OTA in design electronically tunable linear resistor using
MOS. The simulation results and conclusion has been discussed in section 4 and 5 respectively.
2. Proposed OTA
2.1 The referred OTA
The OTA is a transconductance type device, which means that the input voltage controls an
output current by means of the device transconductance, labeled mg . This makes the OTA a
voltage controlled current source (VCCS). In the past few years, engineers have improved the
linearity of MOS transconductor circuits. Such improvement has been primarily in the area of
above-threshold, high-power, high-frequency, continuous time filters. The architecture of OTA is
shown in Fig. 1 which provides a linearity of 1.7 volt by combination of four techniques. Firstly,
the well terminals of the differential-pair transistors 1W and 2W is used as amplifier inputs.
Secondly, feedback techniques like source degeneration via 1S and 2S transistors whereas gate
degeneration via 1GM and 2GM provide further improvement. Finally, 1B and 2B used as bump
transistors. The bump-linearization technique is used to overcome parasitic effects which occur at
low input voltage, generally less than 1 volt.
Figure1. Basic OTA [5]
3. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
3
The P transistor act as bias current source and the remaining transistor 1pM , 2pM , 3nM and 4nM are
configured as simple current mirrors. Besides, there is an offset voltage adjustment which sets
OSV around 5 mV less than DDV . To improve OTA performance, simple current mirror used is
replaced by complex mirroring, that is, High-swing improved-Wilson current mirror. This
technique not only removes the offset voltage adjustment but increases output resistance compared
to case of simple current mirror.
The current equation for subthreshold MOS is given as
( )1
0
gs T ws TkV V k V V
I I e e
− − −
= (1)
for well-input MOS
( )V g Vs w
TV
I eα
− −
(2)
( ) ( )
( ) ( )
2 2 1 1
2 2 1 1
V gV V gVs w s w
T T
V gV V gVs w s w
T T
V V
OUT d
V V
B T
I I I I e e
I I I I e e
− − − −
− − − −
+ −
+ −
− −
= = =
+ +
(3)
Solving
1
tanh
21
d T
d T
gV V
OUT d
gV V
B T
I gVe
I Ve
−
= =
+
(4)
where 2 1d w wV V V V V+ −
= − = −
i.e. tanhOUT
d
B
L
V
I I
V
= (5)
where outI is the output current, BI is the bias current of P transistor , LV is the linear range of OTA
expressed as 2L TV V g= , where g is the overall reduced transconductance of OTA.
Analyzing the left half-circuit of Fig. 1, the overall transconductance g is reduced by a feedback
factor( )1 1 1p nk k+ + ,
i.e.
1
1 1 1p n
k
g
k k
−
=
+ +
(6)
where 1 pk and 1 nk are the loop gain of source degeneration and gate degeneration transistor
respectively. From tanh series expansion
3
tanh
2 2 24
x x x
= − + − − − ; it can be observed that if LV
is made sufficiently high then cubic order term in the tanh series expansion can be easily neglected
thereby reducing distortions of non-linearity.
2.2 High-swing improved-Wilson current Mirror
A current mirror is characterized by the current level it produces, the small-signal ac output
resistance and voltage drop across it. The simple current mirror uses the principle that if gate-to-
source potentials of two identical MOS transistors are equal then their channel currents are equal.
4. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
4
In late 1967, George Wilson proposed a modified current mirror just by adding one extra transistor
which increases output impedance to appreciable amount and named the circuit as Wilson current
mirror. The Wilson current mirror implemented using three nMOS transistors is shown in Fig. 2
(a). The architecture consists of simple current mirror and a current to voltage converter connected
in the feedback loop. If there is any increase in output current due to output voltage variation, the
simple current mirror transistors senses this variation and feed back the current to input node
thereby reducing gate voltage of output transistor followed by reduction in original current
increase. But these current mirror suffered systematic gain error along with unequal voltages
across input and output transistors. To compensate systematic gain error, Barrie Gilbert; added a
fourth transistor in diode connected form in the input branch and later this circuit became famous
by name improved Wilson current mirror [6] as shown in Fig. 2 (b).
Figure2. (a) Wilson current mirror, (b) Modified Wilson current mirror
These circuits require an input voltage of two diode drops and output compliance voltage
incorporates a diode drop plus saturation voltage. Such diode drop made Wilson mirror
unattractive for low-power design units. To overcome this, a new Wilson topology was introduced
[7], which sense the output current at low input voltage of a diode drop plus a saturation voltage
whereas output senses only two saturation voltage. As seen from architecture, the diode connected
transistor on input side biased by current source bI , causes the input voltage to decrease much
lower than gate voltage needed as in case of simple mirrors to sink input current. This makes it a
low voltage high-swing improved-Wilson current mirror as shown in Fig. 3. The mirror achieves
high output resistance by using negative feedback and is directly proportional to the magnitude of
the loop-gain of the feedback action from the output current to the gate of output transistor 3nM .
The transistor 1nM and 2nM samples the OUTI and compares it with inI . In combination with
current source load inI , transistor 1nM act as a common source amplifier used to maintain gate
voltage of 3nM to avoid mismatching of OUTI to inI . Neglecting 2nd
order effects, the output
resistance outr is approximated as
1 1 3out m o or g r r≈ (7)
where, 1mg and 1or are transconductance and output resistance of 1nM whereas 3or is output
resistance of 3nM .
5. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
5
Figure 3. High-swing improved Wilson current mirror
2.3 Modified OTA
The proposed architecture of OTA using high-swing improved-Wilson current mirror is shown
in Fig. 4. The architecture works on low supply thereby introducing appreciable reduction in
power consumption. A bias current generator circuit is attached to OTA which generates current in
the range of nanoamperes.
Figure 4. Proposed OTA using High-swing improved Wilson current mirror
Transistors 13 16n nM M− and 11 12p pM M− along with sR comprises current generator circuit. As the
source-to-gate voltage of 11PM and 12PM are equal their corresponding currents are equal, i.e.
6. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
6
11 12D DI I= (neglecting channel length modulation). Furthermore, it can be noted
that 13 11D DI I= and 14 13D DI I= .
The equation for drain current of MOS transistor is given by
( )21
2
D n ox GS Tn
W
I C V V
L
µ= − (8)
Solving for GSV
( )
2 D
GS Tn
n ox
I
V V
C W Lµ
= + (9)
In Fig. 3
, 13 , 14 , 14GS n GS n D n SV V I R= + (10)
From (10)
( ) ( )
, 13 , 14
, 14
13 14
2 2D n D n
D n S
n ox n oxMn Mn
I I
I R
C W L C W Lµ µ
= + (11)
Rearranging above expression and solving for , 12D pI by equating equivalent currents, the , 12D pI
is given as
( )
( )
( )
2
13
, 12 2
13 14
2 1
1 Mn
D p
n ox SMn Mn
W L
I
C W L W LRµ
= −
(12)
The output current biasI , that is, , 13D pI is now the function of , 12D pI . By adjusting the aspect ratio
of 13pM relative to 12pM , desired biasI can be obtained. The W L ratio of 13pM is kept four times
lower than 12pM , which results in output current , 13 , 12 4D p bias D pI I I= = .
3. Self-tunable linear resistor using MOS
Electronically tunable linear resistors are highly versatile circuit elements. MOS transistors are
generally used for resistor modeling as when it is operated under triode mode behaves as a resistor
controlled by its gate terminal voltage. MOS being a four terminal device offers two control
parameters that is gate and bulk terminal to control resistor value. Through electronic tuning of
gate terminal voltage of MOS transistor, correspondingly electronic control on resistance can be
achieved. In the past, MOS resistors with approximately linear I-V characteristics were obtained
by operating the transistor in the ohmic (triode) region of strong inversion to exploit the resistive
nature of the channel. Generally, these approaches were limited by the small ohmic region and its
intrinsic non-linearities. Various techniques have been proposed to minimize nonlinear effects
associated with operating the MOS transistor in the ohmic strong inversion regime with good
results [8]-[9]. In regard to this, a MOS resistor is used that does not require triode operation [10].
7. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
7
MOS transistor RM shown in Fig. 5, act as a self-tunable resistor when get tuned by capacitance
C connected at its gate terminal.
Figure 5. Electronically self-tuned linear resistor using MOS
To maintain resistor characteristics, a feedback network is configured at its gate terminal. The
two OTAs, OTA1 and OTA2 have same inputs XV and YV connected to their input terminals in
alternative fashion and are biased by the same current source GMI . The potential difference
X YV V− across the MOS device RM is sensed and converted into a current ,OUT GMI using a wide
linear range low power OTA for which the output current equation is of the form
( ),OUT GM M X YI G V V= − (13)
Where, ( )M GM LG I V= is the transconductance of OTA while GMI and LV are the biasing current
and linear range of the OTA respectively. These OTAs are configured in conjunction with diode
connected transistors M1 and M3 to produce two half-wave rectified currents that are proportional
to XYV , voltage across the source-drain terminals of RM . The rectified output currents are
8. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
8
mirrored via M2 and M4 to create a full wave rectified current. The saturation currents XsatI and
YsatI of RM are proportionally replicated by sensing GV , WV , XV and YV on the gate, well, source
and drain terminals of RM buffered via source followers and applying potentials GXV and GYV
across the gate-source terminals of transistors XM and YM . Transistors M7-M13 serve to compute
Xsat YsatI I− or Ysat XsatI I− and transistors M14-M17 compare Xsat YsatI I− with a mirrored version of
output current using M6. Any difference between these two currents causes the capacitor C to
charge or discharge tuning the gate bias voltage GV which equilibrates at a point where the two are
nearly equal via negative feedback action.
To overcome loading effect on terminals of MOS transistor RM , source follower is employed
shown within dotted lines marked as SF in Fig. 5. The source follower has the capability to source
and sink large output currents. Its primary use is to buffer signals and provide low output
impedance to drive resistive loads while, at the same time handle large output voltage swing and
obtain low harmonic distortion. Traditional source have load drive capability limited to the
quiescent current in the buffer. In addition traditional source followers require too much power for
many applications. To reduce power dissipation (and area) required to reach a given output
resistance, composite source follower is used. The composite source follower comprises a current
source, PMOS (Msf3) configured to provide a (relatively) constant current to the rest of the circuit,
a source follower NMOS (Msf0, Msf2) configured to receive an input signal, a folded cascade
device PMOS (Msf4) connected to sense the drain current of the source follower, and a current
mirror device NMOS (Msf1) connected to multiply the sensed drain current for application to an
output load connected at the source follower output. It provides a four-fold increase in
transconductance which offer perfect tracking of input by output having no level shift problem as
compared to common voltage buffers. Being less complex circuitry, it is most effetely used in field
of low power architectures.
4. Simulation Results
The simulations were performed under normal condition (room temperature) on TSMC 0.18
micron technology using ELDO Spice Simulator. The bias current generator circuit generates
biasI of 65nA at 10SR K= Ω . The supply voltage is kept at 0.9 volt. Fig. 6 shows the transfer
characteristics of proposed OTA with enhance linearity to about ± 1.9 volt with no offset voltage
adjustment. Fig. 7 shows the ac response of OTA under no load condition. The achieved phase
margin is 55.332 degree and UGB of 342.30 KHz. Its low UGB supports it for use in biomedical
applications.
9. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
9
Figure 6. Transfer characteristic of proposed OTA
Figure 7. AC response of proposed OTA
When configured as follower integrator using 1 pf of load shown in Fig. 8, it tracks the input
perfectly with slight variation at low input voltage, that is, below 0.4 volt. The transfer
characteristic of MOS acting as linear resistor is shown in Fig. 9. The value of resistor is varied in
accordance to tuning the OTA bias current gmI of OTA used in design.
10. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
10
Figure 8. Follower integrator DC characteristics at 1pF load
Figure 9. Transfer characteristic of self-tunable linear resistor using MOS
5. Conclusion
This paper explored the approach of low-voltage OTA design using the bulk-driven technique
and enhancement of output impedance using high-swing improved-Wilson current mirror. The
design of such low voltage, high performance OTA circuit on TSMC 0.18 micron technology
satisfies the required parameters for its implementation not only in power-saving devices but also
in biomedical portable devices. Further its application in design of tunable MOS resistor find
application in variable gain amplifiers, oscillators, balanced resistive bridges and analog filters.
11. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
11
Acknowledgment
The author would like to thank K.H.Wee and R. Sarpeshkar for the measurement assistance and
meaningful discussions on OTA and MOS resistor. The author also extend their thanks to B. A.
Minch for the measurement assistance of different CM circuits.
References
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order 2.4 Hz lowpass filter for medical applications,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
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[3]L. Watts, D. A. Kerns, R. F. Lyon, and C. A. Mead, “Improved implementation of the silicon cochlea,” IEEE J.
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[8]J. Ramirez-Angulo, M.S. Sawant, R.G. Carvajal and A. Lopez-Martin “Linearisation of MOS resistors using
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Authors
Nikhil Raj received his M.Tech degree in Electronics and Communication Engineering with
specialization in VLSI Design from National Institute of Technology Kurukshetra, Haryana, India in 2009.
Currently, he is a lecturer with the Department of Electronics and Communication Engineering, NIT Kurukshetra,
India. After doing many research works in VLSI area, he is currently doing research in low power analog circuits.
R.K.Sharma received his M.Tech in Electronics and Communication engineering and
PhD degree in VLSI Design from National Institute of Technology Kurukshetra, India in 1993 and 2007,
respectively. Currently he is Associate Professor with the Department of Electronics and Communication
Engineering, NIT Kurukshetra, India. His main research interests are in the field of low power VLSI design,
electronic measurements, microprocessor and FPGA based measurement systems.