An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
An analytical model for the current voltage characteristics of GaN-capped AlG...IJECEIAES
We present an analytical model for the I-V characteristics of AlGaN/GaN and AlInN/GaN high electron mobility transistors (HEMT). Our study focuses on the influence of a GaN capping layer, and of thermal and self-heating effects. Spontaneous and piezoelectric polarizations at Al(Ga,In)N/GaN and GaN/Al(Ga,In)N interfaces have been incorporated in the analysis. Our model permits to fit several published data. Our results indicate that the GaN cap layer reduces the sheet density of the twodimensional electron gas (2DEG), leading to a decrease of the drain current, and that n + -doped GaN cap layer provides a higher sheet density than undoped one. In n + GaN/AlInN/GaN HEMTs, the sheet carrier concentration is higher than in n + GaN/AlGaN/GaN HEMTs, due to the higher spontaneous polarization charge and conduction band discontinuity at the substrate/barrier layer interface.
DC bus stabilization using passive damping network in distributed power syste...TELKOMNIKA JOURNAL
In distributed power system (DPS), the stability performance is always associated with the behaviour of constant power load (CPL). Since DPS large complex system build up from many power electronic converters, the DC bus of the system becomes unstable due to the strenuous action from power converters. When these converters tightly regulated, it behaves as constant power load and exhibit negative incremental input impedance which becomes the main reason in stability degradation of DPS. In this paper, four passive damping network topologies was proposed to reduce the DC bus instability. The best damping performance of the topologies was chosen and analysed using MATLAB/Simulink. The DC bus performances was studied in four cases which are damping behavior due to CPL power level, CPL disconnection, effects of filter and damping capacitor, and effects of filter cut-off frequency. Simulation results obtained shows that the DC bus was successfully stabilized and the resonance damped when passive damper installed. An experimental hardware tests was conducted to verify the proposed damping method and the results were compared with the simulated output waveforms. The analysis results in overshoot, settling time and steady state error of bus voltage shows system improvement with the proposed damper network.
The document describes the design and implementation of a PFC CUK converter for a PMBLDCM drive. It aims to improve the drive's efficiency through power factor correction. A CUK DC-DC converter is used as the PFC converter to reduce power quality problems and improve the power factor at the AC mains input. A three-phase voltage source inverter is used as an electronic commutator to operate the PMBLDCM drive. The speed of the PMBLDCM is controlled by controlling the DC link voltage proportional to the desired speed. The proposed PFC converter topology is modeled and simulated in Matlab/Simulink, showing improved power quality and power factor over a wide speed range of the drive
This document analyzes diode emulation in synchronous buck converters operating under light load conditions. It discusses how diode emulation reduces output voltage ripple and inductor current ripple compared to continuous conduction mode. It also examines transient response and power losses. While diode emulation improves efficiency by reducing losses, extra transitions can cause overshoot during load changes. The document proposes a scheme to separate diode emulation transitions from regular load transients to reduce overshoot. Experimental results are presented to validate the analysis and effectiveness of the proposed scheme.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
An analytical model for the current voltage characteristics of GaN-capped AlG...IJECEIAES
We present an analytical model for the I-V characteristics of AlGaN/GaN and AlInN/GaN high electron mobility transistors (HEMT). Our study focuses on the influence of a GaN capping layer, and of thermal and self-heating effects. Spontaneous and piezoelectric polarizations at Al(Ga,In)N/GaN and GaN/Al(Ga,In)N interfaces have been incorporated in the analysis. Our model permits to fit several published data. Our results indicate that the GaN cap layer reduces the sheet density of the twodimensional electron gas (2DEG), leading to a decrease of the drain current, and that n + -doped GaN cap layer provides a higher sheet density than undoped one. In n + GaN/AlInN/GaN HEMTs, the sheet carrier concentration is higher than in n + GaN/AlGaN/GaN HEMTs, due to the higher spontaneous polarization charge and conduction band discontinuity at the substrate/barrier layer interface.
DC bus stabilization using passive damping network in distributed power syste...TELKOMNIKA JOURNAL
In distributed power system (DPS), the stability performance is always associated with the behaviour of constant power load (CPL). Since DPS large complex system build up from many power electronic converters, the DC bus of the system becomes unstable due to the strenuous action from power converters. When these converters tightly regulated, it behaves as constant power load and exhibit negative incremental input impedance which becomes the main reason in stability degradation of DPS. In this paper, four passive damping network topologies was proposed to reduce the DC bus instability. The best damping performance of the topologies was chosen and analysed using MATLAB/Simulink. The DC bus performances was studied in four cases which are damping behavior due to CPL power level, CPL disconnection, effects of filter and damping capacitor, and effects of filter cut-off frequency. Simulation results obtained shows that the DC bus was successfully stabilized and the resonance damped when passive damper installed. An experimental hardware tests was conducted to verify the proposed damping method and the results were compared with the simulated output waveforms. The analysis results in overshoot, settling time and steady state error of bus voltage shows system improvement with the proposed damper network.
The document describes the design and implementation of a PFC CUK converter for a PMBLDCM drive. It aims to improve the drive's efficiency through power factor correction. A CUK DC-DC converter is used as the PFC converter to reduce power quality problems and improve the power factor at the AC mains input. A three-phase voltage source inverter is used as an electronic commutator to operate the PMBLDCM drive. The speed of the PMBLDCM is controlled by controlling the DC link voltage proportional to the desired speed. The proposed PFC converter topology is modeled and simulated in Matlab/Simulink, showing improved power quality and power factor over a wide speed range of the drive
This document analyzes diode emulation in synchronous buck converters operating under light load conditions. It discusses how diode emulation reduces output voltage ripple and inductor current ripple compared to continuous conduction mode. It also examines transient response and power losses. While diode emulation improves efficiency by reducing losses, extra transitions can cause overshoot during load changes. The document proposes a scheme to separate diode emulation transitions from regular load transients to reduce overshoot. Experimental results are presented to validate the analysis and effectiveness of the proposed scheme.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
IRJET- Impact of Buffer Mole Fraction on Algan/ Gan HEMT with Different G...IRJET Journal
This document summarizes research on the impact of buffer mole fraction on AlGaN/GaN HEMTs. Increasing the Al mole fraction in the AlGaN buffer results in higher polarization charges at the interface, which leads to increased 2DEG density and higher drain current. Simulation results show that at different gate voltages, an Al mole fraction of 0.30 produces the highest drain and source currents. The increased electron confinement and reduced short channel effects with higher mole fractions improve device output resistance and performance.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Full IEDM paper version - as last submittedDavid Goren
This paper proposes an air-core slab inductor structure to achieve ultra-high Q for on-chip power conversion circuits with over 90% efficiency. The structure uses a wide, thick metal slab with specially designed current return paths on either side to minimize DC resistance. Experiments demonstrate Q values as high as 25-35 at 200-300MHz, achieving 96.6% estimated inductor efficiency. Simulations of buck converters using the proposed inductor design show over 90% conversion efficiency for 2:1 voltage ratios. The structure can be implemented in a standard CMOS backend process without thin-film magnetics.
Measurement of the hot carrier damage profile in LDMOS devices stressed at hi...Saverio Aurite
This document describes a study of hot carrier damage in laterally diffused nMOSFET (LDMOS) devices. The researchers developed a new methodology using charge pumping measurements to estimate the spatial distribution of hot carrier damage in the devices. They applied constant drain voltage stresses to the devices and measured changes in device parameters and charge pumping curves. They then used a model assuming exponential damage profiles matching simulations of impact ionization rates. By fitting the model to experimental charge pumping data, they were able to extract the interface trap densities and trapped charge distributions as a function of stress conditions and injected charge amount. The methodology provided good agreement with measurements and improved understanding of degradation mechanisms in these high voltage devices.
novel design of current dierencing transconductance amplier with high
2 transconductance gain and enhanced bandwidth
Shireesh Kumar RAI1 , Rishikesh PANDEY1 , Bharat GARG1 , Sujit Kumar PATEL1
1Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
In this paper a novel control technique for switching-frequency-modulated switch-mode power converters (SMPC) operating in discontinuous conduction mode is proposed. The use of the technique leads to significant reduction in peak-to-peak output voltage and peak currents increased due to straightforward application of switching frequency modulation (SFM). The technique is based on hybrid modulation scheme in which both switching frequency and duty ratio are modulated simultaneously by the same modulation signal. Theoretical analysis and experimental verification of the proposed technique are presented in details. Both computer simulations and experiments show that switching-frequency-modulated SMPC with the proposed control technique in comparison to SMPC without SFM has appreaciably lower conducted electromagnetic emissions, at the cost of slightly increased peak-to-peak output voltage and peak currents.
Electromagnetic analysis of submarine umbilical cables with complex configura...thinknice
This document summarizes electromagnetic analyses of different configurations of integrated production umbilical cables. Umbilical cables can have multiple independent power circuits and steel tubes. Three configurations (A, B, C) are analyzed using a combined 2D finite element and transposition methodology to evaluate performance considering load terminal voltages and induced voltages. Configuration B, where each power circuit rotates around its own center, has the best performance with balanced terminal voltages and minimized induction effects along the cable length.
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
The document proposes a bus encoder design to reduce crosstalk and power dissipation in RLC modeled VLSI interconnects. It introduces a modified bus invert encoding method using counters to count different types of crosstalk couplings. The encoder divides the data bus into clusters of 4 data bits and 1 control bit. It uses counters to count type-0, type-1 couplings with original and inverted data. The counts are compared and the control bit determines if original or inverted data is transmitted, reducing switching activity and crosstalk. Simulation results show the proposed encoder reduces power dissipation and crosstalk induced delay by 55.43% and 45.87% respectively compared to previous designs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation Yayah Zakaria
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for
the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 and a subthreshold slope
of 0.44V/dec. Sentaurus TCAD simulations is the tool which
offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Wavelet based analysis for transmission line fault locationAlexander Decker
This document summarizes a technique for locating faults on electric power transmission lines using wavelet analysis. It begins with an introduction to transmission line faults and issues with existing fault location methods. It then describes the basics of traveling wave theory and modal analysis for decomposing fault currents. A proposed algorithm is outlined that uses the discrete wavelet transform to analyze modal components of fault current received at a relay point. Time delays between modal components are used to determine the fault location based on the faulted transmission line length and wave propagation speed. Simulation results using MATLAB are presented to illustrate the approach. The method aims to provide accurate fault location independently of factors like fault inception angle and impedance.
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A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
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DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
This document presents a high efficient loaded resonant converter with feedback for DC-DC energy conversion. The proposed converter consists of a half-bridge inductor-capacitor-inductor resonant inverter connected to a bridge rectifier and load. Soft switching reduces losses and improves efficiency. Simulation results show the converter achieves up to 85.8% efficiency. Feedback control provides accurate output regulation. Analysis and MATLAB simulation demonstrate the converter's improved performance for DC-DC energy conversion applications.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
IRJET- Impact of Buffer Mole Fraction on Algan/ Gan HEMT with Different G...IRJET Journal
This document summarizes research on the impact of buffer mole fraction on AlGaN/GaN HEMTs. Increasing the Al mole fraction in the AlGaN buffer results in higher polarization charges at the interface, which leads to increased 2DEG density and higher drain current. Simulation results show that at different gate voltages, an Al mole fraction of 0.30 produces the highest drain and source currents. The increased electron confinement and reduced short channel effects with higher mole fractions improve device output resistance and performance.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Full IEDM paper version - as last submittedDavid Goren
This paper proposes an air-core slab inductor structure to achieve ultra-high Q for on-chip power conversion circuits with over 90% efficiency. The structure uses a wide, thick metal slab with specially designed current return paths on either side to minimize DC resistance. Experiments demonstrate Q values as high as 25-35 at 200-300MHz, achieving 96.6% estimated inductor efficiency. Simulations of buck converters using the proposed inductor design show over 90% conversion efficiency for 2:1 voltage ratios. The structure can be implemented in a standard CMOS backend process without thin-film magnetics.
Measurement of the hot carrier damage profile in LDMOS devices stressed at hi...Saverio Aurite
This document describes a study of hot carrier damage in laterally diffused nMOSFET (LDMOS) devices. The researchers developed a new methodology using charge pumping measurements to estimate the spatial distribution of hot carrier damage in the devices. They applied constant drain voltage stresses to the devices and measured changes in device parameters and charge pumping curves. They then used a model assuming exponential damage profiles matching simulations of impact ionization rates. By fitting the model to experimental charge pumping data, they were able to extract the interface trap densities and trapped charge distributions as a function of stress conditions and injected charge amount. The methodology provided good agreement with measurements and improved understanding of degradation mechanisms in these high voltage devices.
novel design of current dierencing transconductance amplier with high
2 transconductance gain and enhanced bandwidth
Shireesh Kumar RAI1 , Rishikesh PANDEY1 , Bharat GARG1 , Sujit Kumar PATEL1
1Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
This document compares three switching methods for an asymmetric cascaded H-bridge multilevel inverter: selective harmonic elimination (SHE), nearest level control (NLC), and multi-carrier pulse width modulation (PWM). SHE and NLC aim to minimize total harmonic distortion but are offline methods not suitable for closed-loop systems. Multi-carrier PWM provides appropriate harmonic performance while being an online method. Equations are presented for generating PWM signals to control the switches in each cell based on multiple carrier waves to synthesize a high number of voltage levels from asymmetric DC input voltages. Simulation results show multi-carrier PWM has advantages over SHE and NLC for use in an asymmetric multilevel inverter system.
In this paper a novel control technique for switching-frequency-modulated switch-mode power converters (SMPC) operating in discontinuous conduction mode is proposed. The use of the technique leads to significant reduction in peak-to-peak output voltage and peak currents increased due to straightforward application of switching frequency modulation (SFM). The technique is based on hybrid modulation scheme in which both switching frequency and duty ratio are modulated simultaneously by the same modulation signal. Theoretical analysis and experimental verification of the proposed technique are presented in details. Both computer simulations and experiments show that switching-frequency-modulated SMPC with the proposed control technique in comparison to SMPC without SFM has appreaciably lower conducted electromagnetic emissions, at the cost of slightly increased peak-to-peak output voltage and peak currents.
Electromagnetic analysis of submarine umbilical cables with complex configura...thinknice
This document summarizes electromagnetic analyses of different configurations of integrated production umbilical cables. Umbilical cables can have multiple independent power circuits and steel tubes. Three configurations (A, B, C) are analyzed using a combined 2D finite element and transposition methodology to evaluate performance considering load terminal voltages and induced voltages. Configuration B, where each power circuit rotates around its own center, has the best performance with balanced terminal voltages and minimized induction effects along the cable length.
BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED VLSICS Design
The document proposes a bus encoder design to reduce crosstalk and power dissipation in RLC modeled VLSI interconnects. It introduces a modified bus invert encoding method using counters to count different types of crosstalk couplings. The encoder divides the data bus into clusters of 4 data bits and 1 control bit. It uses counters to count type-0, type-1 couplings with original and inverted data. The counts are compared and the control bit determines if original or inverted data is transmitted, reducing switching activity and crosstalk. Simulation results show the proposed encoder reduces power dissipation and crosstalk induced delay by 55.43% and 45.87% respectively compared to previous designs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation Yayah Zakaria
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for
the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 and a subthreshold slope
of 0.44V/dec. Sentaurus TCAD simulations is the tool which
offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Wavelet based analysis for transmission line fault locationAlexander Decker
This document summarizes a technique for locating faults on electric power transmission lines using wavelet analysis. It begins with an introduction to transmission line faults and issues with existing fault location methods. It then describes the basics of traveling wave theory and modal analysis for decomposing fault currents. A proposed algorithm is outlined that uses the discrete wavelet transform to analyze modal components of fault current received at a relay point. Time delays between modal components are used to determine the fault location based on the faulted transmission line length and wave propagation speed. Simulation results using MATLAB are presented to illustrate the approach. The method aims to provide accurate fault location independently of factors like fault inception angle and impedance.
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A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
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DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODELVLSICS Design
This document summarizes a research paper on implementing a low power design methodology for recursive encoders and decoders. It discusses how recursive coding can achieve better error correction performance at low signal-to-noise ratios compared to other codes. It then describes the design of a recursive decoder that uses the log-MAP algorithm to minimize power consumption. The decoder uses five main computational steps - branch metric calculation, forward metric computation, backward metric computation, log-likelihood ratio calculation, and extrinsic information calculation. It also compares the implementation of four-state and eight-state recursive encoders. The goal of the design is to optimize the power and area of recursive encoders and decoders.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
This document summarizes a research paper that proposes a new low-power full adder cell design using carbon nanotube field-effect transistors (CNTFETs) in 32 nanometer technology. Simulation results show that the design, which uses 24 CNTFETs, reduces power consumption compared to previous CNTFET full adder designs. The power and power-delay product increase with supply voltage but are largely unaffected by temperature. Compared to previous designs, the proposed cell has lower power, delay, and power-delay product, especially at 0.65V supply voltage, demonstrating its improved energy efficiency.
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUITVLSICS Design
This document summarizes a research paper that proposes a new low voltage current mirror circuit using a bulk-driven technique. The proposed circuit consists of 4 PMOS and 5 NMOS transistors and can operate at a supply voltage of +0.85V. It uses bulk connections to reduce the threshold voltage of the PMOS transistors. The document describes the circuit operation and provides its AC equivalent model. It was simulated in Cadence using a 180nm process and was found to function as a current mirror.
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DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
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Research Inventy : International Journal of Engineering and Science is publis...researchinventy
This document summarizes research on characterizing the electrical properties of AlGaN/GaN modulation-doped field-effect transistors (MODFETs). Key findings include:
- A threshold voltage of -3.87V, maximum saturation current of 122.748 mA, and transconductance values were achieved.
- Dependence of two-dimensional electron gas density at the interface on Al mole fraction and AlGaN barrier layer thickness was presented.
- A novel method for studying AlGaN/GaN interface properties by solving the Schrodinger and Poisson equations self-consistently using finite difference methods was developed. This allows calculating electron distributions, energy band structures, and other characteristics of
I v characteristics and transconductance modeling for dual channel algangan m...eSAT Journals
Abstract This paper presents the design and practical implementation of a Boost-type power converter for Photovoltaic (PV) system for energy storage application based on Perturb and Observe Maximum Power Point Tracking (MPPT) algorithm. A Boost converter is used to regulate battery charging. The major drawbacks faced by the tracking algorithm in the conventional method of tracking is overcome by the strategic utilization of a properly controlled and programmed design of Peripheral Interface Controller which helps in achieving optimized output results of MPPT algorithm.. The system is controlled by a Peripheral Interface Controller (PIC) 16F877 controller by sensing the solar panel voltage and generating the Pulse Width Modulation (PWM) signal to control duty cycle of the boost converter. This type of microcontroller was chosen is best suited as it has the necessary features for the proposed design such as built-in Analog-to-Digital Converter (ADC), PWM outputs, low power consumption and low cost. Hardware results demonstrate the effectiveness and validity of the proposed system in order to attain satisfactory results from the method. This paper mainly focuses on the effective utilization of PIC controller in the implementation of the MPPT algorithm and its constructional features which help gain the appropriate and accurate results. Keywords: Photovoltaic system, Analog-to-Digital Converter, Peripheral Interface Controller, Maximum Power Point Tracking, Pulse Width Modulation, Boost-type power converter, Duty Cycle.
Threshold voltage model for hetero-gate-dielectric tunneling field effect tra...IJECEIAES
In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 10 16 /cm 3 . The higher concentration in the source (N s ) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.
Numerical investigation of the performance of AlGaN/GaN/BGaN double-gate dou...IJECEIAES
In this work, we examine the direct-current (DC) behavior and the radio frequency (RF) performance of both single-gate simple-channel (SGSC), single-gate double-channel (SGDC) and double-gate double-channel (DGDC) AlGaN/GaN/BGaN high electron mobility transistor (HEMT) with BGaN back-barriers consist of 250 nm gate length. Using technology computer aided design (TCAD) Silvaco, our isothermal simulation results reveal that the proposed structure of double-gate double-channel HEMT with BGaN back-barriers (DGDCBB HEMT) increases electron concentration and consequently the saturation drain current, breakdown voltage, the transconductance. On the other hand, decreases the gate leakage current compared to a conventional HEMT and to a double-channel HEMT back-barriers. Furthermore, the proposed double-gate double-channel backbarrier HEMT device shows good cutoff frequency (94 GHz) and a maximum oscillation frequency (170 GHz). These results suggest that double-gate double channel HEMT back-barriers could be useful for high frequency and high-power microwave applications.
Transistor mismatch effect on common-mode gain of cross-coupled amplifierTELKOMNIKA JOURNAL
In this paper, the analytical approach of MOS transistor mismatch effect on common-mode gain
of cross-coupled amplifier is presented. Transconductance (MOS transistor parameter) mismatch effect on
common-mode gain of cross-coupled amplifier was analyzed. This study was started with mathematical
derivation for representing the mismatch effect of transconductance between 2 differential pairs of crosscoupled
amplifier due to common-mode voltage. The derivation result was simulated based on Monte
Carlo simulation with random transconductance mismatch rate from 0.05% until 1%. The common-mode
gain increases 36.9 dB and average common-mode gain is -81.1 dB. The transconductance mismatch rate
increases followed by increase in common-mode gain. The results can be used by circuit designers to
design analog circuits, especially operational amplifier used for biosignals processing to minimize the
common-mode gain of their circuits. This research presents aid to circuit designers to improve their circuits
performance.
Enabling relay selection in non-orthogonal multiple access networks: direct a...TELKOMNIKA JOURNAL
In this paper, we consider downlink non-orthogonal multiple access (NOMA) in which the relay selection (RS) scheme is enabled for cooperative networks. In particular, we investigate impact of the number of relays on system performance in term of outage probability. The main factors affecting on cooperative NOMA performance are fixed power allocations coefficients and the number of relay. This paper also indicate performance gap of the outage probabilities among two users the context of NOMA. To exhibit the exactness of derived formula, we match related results between simulation and analytical methods. Numerical results confirms that cooperative NOMA networks benefit from increasing the number of relay.
Average Channel Capacity of Amplify-and-forward MIMO/FSO Systems Over Atmosph...IJECEIAES
In amplify-and-forward (AF) relay channel, when the direct link between source and destination terminals is deeply faded, the signal from the source terminal to the destination terminal propagates through the relay terminals, each of which relays a signal received from the previous terminal to the next terminal in series. This paper, we theoretically analyze the performance of multiple-input multiple-output (MIMO) AF free-space optical (FSO) systems. The AF-MIMO/FSO average channel capacity (ACC), which is expressed in terms of average spectral efficiency (ASE) is derived taking into account the atmospheric turbulence effects on the MIMO/FSO channel. They are modeled by log-normal and the gamma-gamma distributions for the cases of weak-to-strong turbulence conditions. We extract closed form mathematical expression for the evaluation of the ACC and we quantitatively discuss the influence of turbulence strength, link distance, different number of relay stations and different MIMO configurations on it.
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsTELKOMNIKA JOURNAL
Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore
power amplifiers are the most important parts of electronic circuits. This is why the designing of power
amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design
of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using
a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The
configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The
proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also
utilized for getting the good matching condition. The advanced design system (ADS) software is used for
design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent
power gain; is changed between 28.5 and 20 dB with an output power of 12.45dBm at 1dB compression
point. For the input reflection coefficient (S11) is varied between -20 and -42 dB. While the output reflection
coefficient (S22) is varied between -10 dB and -49 dB over the wide frequency band of 3.2-3.8 GHz.
UWB THz plasmonic microstrip antenna based on grapheneTELKOMNIKA JOURNAL
This paper proposes design and investigates of graphene based plasmonic microstrip antenna for terahertz high speed communication and application systems 0.1-20 THz. The proposed antenna structure composed of graphene-based rectangular patch and transmission line mounted on a grounded silicone dioxide substrate. SPP (Surface Plasmon Polariton) waves that appear in graphene at THz band is analyzed. The proposed antenna simulation was done by using numerical method CST program. The simulation results show the scattering parameter S11 less than -10 dB at frequency band (0.1-20) THz. Also, the presented antenna system has a good gain along the frequency band.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
This document describes the design and simulation of an AlGaN/GaN high electron mobility transistor (HEMT) on a silicon carbide substrate for low noise applications. Key findings from the simulation of the 0.25 um gate length device include:
1) The device exhibited a minimum noise figure of 0.41 dB and maximum associated gain of 19.95 dB at 10 GHz.
2) It also demonstrated a minimum noise figure of 0.71 dB and maximum associated gain of 17.4 dB at 18 GHz.
3) The device showed a peak extrinsic transconductance of 215 mS/mm and a high current drive capability of 1400 mA/mm, indicating its potential for
Analytic Estimation of Two-Dimensional Electron Gas Density and Current-Volta...IJECEIAES
This paper is mainly dedicated to understand the phenomena governing the formation of two-dimensional electron gas (2DEG) confined in the quantum well which hold the role of the channel in the high electron density transistors (HEMT) based on AlGaN / GaN heterojunction. The theory takes into account: the crystal structure, the spontaneous and piezoelectric polarization concept, the formation mechanism of two-dimensional electron gas at the AlGaN / GaN interface, the approximate resolution of the Poisson and Schrödinger equations to determine the density of Two-dimensional electron gas after the analytical formula of the current-voltage characteristic is established. Our study is also concerned with the dependence of the twodimensional electron gas density on the following technological parameters: Aluminum molare fraction, AlGaN layer thickness and AlGaN layer doping, In order to control the influence of these parameters on the device performance. Finally, the current-voltage characteristic which reflects the variation of the drain-source current as a function of the modulation of the gate voltage has been discussed.
TWO DIMENSIONAL MODELING OF NONUNIFORMLY DOPED MESFET UNDER ILLUMINATIONVLSICS Design
A two dimensional numerical model of an optically gated GaAs MESFET with non uniform channel doping has been developed. This is done to characterize the device as a photo detector. First photo induced voltage (Vop) at the Schottky gate is calculated for estimating the channel profile. Then Poisson’s equation for the device is solved numerically under dark and illumination condition. The paper aims at developing the MESFET 2-D model under illumination using Monte Carlo Finite Difference method. The results discuss about the optical potential developed in the device, variation of channel potential under different biasing and illumination and also about electric fields along X and Y directions. The Cgs under different illumination is also calculated. It has been observed from the results that the characteristics of the device are strongly influenced by the incident optical illumination.
The document discusses the history and principles of wireless power transfer using magnetic resonance, called Witricity. It explains how near-field inductive coupling between resonant objects allows for energy transfer with minimal losses. Simulation results show that the ratio of coupling to loss rates remains high even in the presence of external objects, demonstrating the feasibility of wireless power transfer using magnetic resonance.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation IJECEIAES
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 , and a subthreshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Performance Analysis of PAPR Reduction in MIMO-OFDMIJARBEST JOURNAL
Authors: Jayaraman.G1, VeeraKumar K2, Selvakani.S3
Abstract— In communication system, it is aimed to provide highest possible
transmission rate at the lowest possible power and with the least possible noise. MIMOOFDM
has been chosen for high data rate communications and widely deployed in many
wireless communication standards. The major drawback in OFDM signal transmission is
high PAPR. In previous, use clipping technique to tackle this problem. In this paper, use
EM-GAMP algorithm to reduce PAPR in considerable amount.
GPR Probing of Smoothly Layered Subsurface Medium: 3D Analytical ModelLeonid Krinitsky
An analytical approach to GPR probing of a
horizontally layered subsurface medium is developed, based on the coupled-wave WKB approximation. An empirical model of current in dipole transmitter antenna is used.
Recent research shows the tremendous potential for the development of optical devices viz. photo-detector, optical sources, connectors and applications etc. This is mainly because of the success of optical communication in the recent for gigabit transmission and is intended for terabits transmission in future. In this paper, mathematical model for the optical dependence of I-V, C-V characteristics of MISFET structure (to be used as photo-detector) is reported. Model is based on solution of Poisson‟s and current continuity equation. Proposed structure of MISFET includes, In0.53Ga0.47As used as substrate material and InP as insulator. Light is made to incident perpendicular to the surface. Drain current can be controlled optically by means of varying light intensity of incident radiation. There is significant effect of intensity modulation on IV and CV characteristics of MISFET. As a result of intensity modulation, drain current increases significantly in presence of illumination mainly due to change in carrier concentration of channel results from photo-generated carriers. Simulation of mathematical model is carried out in MATLAB.
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leewayhertz.com-AI in predictive maintenance Use cases technologies benefits ...alexjohnson7307
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ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS FOR MICROWAVE APPLICATIONS
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
DOI : 10.5121/vlsic.2013.4205 51
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF
2-D MODFET WITH POLARIZATION EFFECTS
FOR MICROWAVE APPLICATIONS
Ramnish Kumar1
, Sandeep K Arya1
and Anil Ahlawat2
1
Department of ECE, GJUST, Hisar
2
Department of CSE, KIET, Ghajiabad
contactram1@rediffmail.com
ABSTRACT
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
KEYWORDS
AlGaN/GaN MODFETs, cut-off frequency, drain - conductance, polarization, trans - conductance.
1. INTRODUCTION
In recent years, MODFETs (Modulation Doped Field Effect Transistors) or HEMTs (High
Electron Mobility Transistors) have been developed because of their very high switching speed,
low power consumption and relatively simple fabrication technology. The HEMT fabricated in
AlGaN/GaN materials is most suitable for high power, low noise, high speed, good stability and
high temperature microwave devices. The use of HEMTs is increasing in many microwave
circuits and systems because of their high frequency and high speed response. The
pseudomorphic high electron mobility transistors have shown excellent microwave and noise
performance and are very attractive for millimetre wave and optoelectronic applications [1-3].
Recently, pHEMTs have shown superior performance at microwave and millimetre frequency
range. pHEMTs have also demonstrated excellent performance, both as microwave and digital
devices [4-6]. AlGaN/GaN HEMTs have emerged as a strong option for high power application
owing to their large band gap energy and high saturation velocity [7-9]. The presence of strong
polarization (spontaneous & piezoelectric) fields leads to the enhanced performance of these
devices. The polarization charges, the conduction–band discontinuity and mole fraction are the
important parameters that affect the sheet carrier density at the interface. An increase in
aluminium composition in the mole fraction of AlGaN/GaN pHEMTs increases the density of the
two dimensional electron gas and electron lie more closely to the interface. The additional
characteristic features of the AlGaN/GaN material that lead to excellent performance of GaN-
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
52
based HEMTs are large breakdown field and high thermal stability [10]. Along with advances in
HEMT fabrication, large number of analytical and numerical models has been developed [11-22].
These models are helpful as they provide good insight into the physical operation of the device.
But, they normally require some simplifying assumptions to obtain the sheet charge density of 2-
DEG. The present model is developed by solving the two dimensional poisson’s equation and the
parasitic resistance. This model is then used to derive the small-signal parameters namely
transconductance, drain conductance, transit time and cut-off frequency of AlGaN/GaN pHEMTs,
including the effects of spontaneous and polarization fields. The 2-D analysis of the device has
been carried out in the saturation region and modified expression of device transconductance and
output conductance has been given. The results of the proposed model have been verified with the
published experimental/ simulated data.
2. THEORETICAL CONSIDERATION
The basic structure of AlGaN/GaN pHEMT considered in the present analysis is [11] as shown in
figure-1.
Figure 1.Schematic diagram of AlGaN/GaN pHEMT
The 2-DEG sheet charge density formed at the Alm Ga1-m N/GaN heterointerface is obtained
By solving Poisson’s equation [12-13] as
݊௦ሺ݉, ݔሻ =
Ɛሺሻ
.ሺௗ ାௗ ା∆ ሻ
൫ܸ௦−ܸሺݔሻ−ܸ௧ሺ݉ሻ൯ (1)
Where
dd = doped AlGaN/GaN Layer thickness
di = spacer (undoped AlGaN/GaN) layer thickness
∆d=effective thickness of 2-DEG
D= dd +di +∆d=separation between the gate and the channel
q = electronic charge
m = Al mole fraction
Ɛ(m) = AlGaN/GaN dielectric constant
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
53
Vgs = applied gate source voltage
Vc(x) = channel potential at x due to the drain voltage.
Vth = threshold voltage.
Threshold voltage is defined as the applied gate voltage for which the channel is completely
depleted of free carriers and is considered as the minimum potential in the channel. The threshold
voltage Vth(m) of AlGaN/GaN pHEMT is strongly dependent on polarization charge density. It is
given [16] as:
ܸ௧ሺሻୀߔ݉ሺ݉ሻ − ∆ܧ ሺ݉ሻ −
ேௗ
మ
ଶ Ɛሺሻ
−
.ఙሺሻ
Ɛሺሻ
+
ாሺሻ
(2)
Where
Φm(m)=schottky barrier carrier
∆Ec(m)=conduction-band discontinuity of AlGaN/GaN interface
Nd=doping concentration of the AlGaN barrier
σ(m)=net polarization induced sheet charge density at the AlGaN/GaN interface
Ef (m)=Fermi potential
The total polarization induced charge sheet density is given [10] as:
ߪሺ݉ሻ = ܲௌሺ ݈ܣܽܩଵିܰሻ − ܲௌሺܰܽܩሻ + ܲሺ݈ܣܽܩଵିܰ) - ܲሺܰܽܩሻ (3)
Where
PSP=Spontaneous polarization of AlGaN and GaN layers resp.
PPZ=Piezoelectric polarization of AlGaN and GaN resp.
In the above expression, it has been assumed that the GaN layer is fully relaxed. This is
reasonable assumption since the thickness of GaN layer is much larger than that of strained
AlGaN layer. Thus Ppz=0.
The total amount of polarization induced sheet charge density for AlGaN/GaN heterostructure
field effect transistor is obtained as:
ǀߪሺ݉ሻǀ = ǀܲௌሺ ݈ܣܽܩଵିܰሻ − ܲௌሺܰܽܩሻ + ܲሺ݈ܣܽܩଵିܰ) ǀ (4)
Where
ܲሺ ݈ܣܽܩଵିܰሻ = 2 ቀ
ሺሻିሺሻ
ሺሻ
ቁ൬݁ଷଵሺ݉ሻ − ݁ଷଷሺ݉ሻ
భయሺሻ
యయሺሻ
൰
Pspሺ ݈ܣܽܩଵିܰሻ=-0.052m-0.029
Psp(GaN)=-0.029 (5)
a (m) is lattice constant, e31 (m) and e33 (m) are piezoelectric constants, c13 (m) and c33 (m) are
elastic constants respectively.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
54
2.1 CURRENT -VOLTAGE CHARACTERISTICS
The drain source current in the channel is obtained from the current density equation and is given
[15] as:
ܫௗ௦ሺ݉, ݔሻ = ߤݍݖሺ,ݔ ݉ሻ ቀ݊௦ሺ݉, ݔሻ
ௗ௩ሺ௫ሻ
ௗ௫
+
ಳ்
ௗೞሺ,௫ሻ
ௗ௫
ቁ (6)
Where z is the gate width, T is temperature, KB is Boltzman constant.
µ(x) =field dependent electron mobility and is given [11] as:
ߤሺ,ݔ ݉ሻ =
ఓబሺሻ
ଵା൬
ഋబሺሻಶషೇೞೌ
ಶೇೞೌ
൰
ೡೣ
ೣ
(7)
Using equations (1) and (7) in (6) and on integrating using boundary conditions
ݒሺݔሻǀ௫ୀ = ܫௗ௦ሺ݉, ݔሻܴݏ (8)
ݒሺݔሻǀ௫ୀ = ݒௗ௦ − ܫௗ௦ሺ݉, ݔሻሺܴݏ + ܴ݀ሻ (9)
Where Rs and Rd are the parasitic source and drain resistances respectively.
The Ids-Vds equation for the linear region is obtained as
ܫௗ௦ =
ିఈ±ඥఈమିସఉఊ
ଶఉ
(10)
Where
α = − ቂL + EଵVୢୱ + Eଶ ቀVୱିV୲୦ −
୩ా
୯
ቁ ሺ2Rs + Rd ሻ − EଶVୢୱሺRs + Rdሻ ቃ (11)
ߚ = ܧଵሺ2ܴݏ + ܴ݀ሻ −
ாమோௗ
ଶ
ሺܴ݀ + 2ܴݏሻ (12)
ߛ = ܧଶ ቀܸ௦ିܸ௧ −
ಳ்
ቁ ܸௗ௦ −
ாమ
ଶ
ܸௗ௦
ଶ
(13)
ఓ ாିೞೌ
ாೞೌ
= ܧଵ (14)
ఓ Ɛሺሻ
= ܧଶ (15)
ௗ௩ ሺ௫ሻ
ௗ௫
= ܸ
ᇱ
ሺݔሻ (16)
At the onset of saturation, the carriers get velocity saturated, and the electric field attains the
critical value (ܧ). The current in the saturation region is obtained as
ܫௗ௦௧ =
ఓ ாƐሺሻ
ௗ
ቂܸ௦ିܸ௧ିܸௗ௦௧ሺ݉ሻ −
்
ቃ (17)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
55
The saturation current can also be obtained from equation (10) by replacing Vds by Vdsat. The
drain saturation voltage Vdsat is obtained by equating the two expressions for Idsat due to the
current continuity between the linear and saturation region as by equations (10) and (17):
Vୢୱୟ୲ =
ିభ±ටభ
మିସమయ
ଶమ
(18)
Where
ߔଵ =
ఓ Ɛሺሻா
ௗ
ቂ
ିଶொఉఓ Ɛሺሻா
ௗ
− ܧଵܳ + ܧଶܳሺܴݏ + ܴ݀ሻ + ܮ + ܧଶܳሺ2ܴݏ + ܴ݀ሻቃ +
ܧଶܳ (19)
ߔଶ =
ఓ Ɛሺሻா
ௗ
ቂ
ఉ ఓ Ɛሺሻா
ௗ
+ ܧଵ−ܧଶ ሺܴݏ + ܴ݀ሻቃ −
ாమ
ଶ
(20)
ߔଷ =
ொఓ Ɛሺሻா
ௗ
ቂ
ఉఓ Ɛሺሻாమொ
ௗ
− ܮ −
ாమொሺଶோ௦ାோௗሻ
ௗ
ቃ (21)
ܳ = ܸ௦ିܸ௧ −
ಳ்
(22)
2.2 SMALL SIGNAL PARAMETERS
The small signal parameters (drain conductance, transconductance, cut-off frequency and transit
time) govern the current driving capability and are extremely important for estimating the
microwave performance of the device[11,12]. The small signal parameters have been modelled in
terms of basic device parameters and terminal voltages to give an insight into device performance
and serve as a basis for device design and optimization.
(a) Drain/Output conductance
It is an important microwave parameter that determines the maximum voltage gain attainable
from a device. The drain conductance of the AlGaN/GaN pHEMT is evaluated as
݃ௗሺ݉ሻ =
డூೞሺሻ
డೞ
ܽݐ ܸܿݐ݊ܽݐݏ݊௦ (23)
݃ௗሺ݉ሻ =
ଵ
ଶఉ
−ܧଵ + ܧଶሺܴௗ + ܴ௦ሻ +
ଵ
ଶඥఈమିସఉఊ
ሼ2ߙሺ−ܧଵ+ܧଶ ሺܴௗ + ܴ௦ሻሻ − 4ߚܧଶሺܳ −
ܸௗ௦ሻሽቃ (24)
(b) Transconductance
It is the most important parameter for optimization of FET high frequency behaviour. The major
part of the gain mechanism is embodied in the active channel transconductance, which is
evaluated as
݃ሺ݉ሻ =
డூೞሺሻ
డೞ
ܽݐ ܸܿݐ݊ܽݐݏ݊ௗ௦ (25)
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
56
݃ሺ݉ሻ =
ଵ
ଶఉ
−ܧଶሺ2ܴݏ + ܴ݀ሻ +
ଵ
ଶඥఈమିସఉఊ
൛2ߙ൫−ܧଶ ሺ2ܴݏ + ܴ݀ሻ൯ − 4ߚܧଶܸௗ௦ൟ൨
(26)
(c) Cut-off frequency
The primary figure of merit for high frequency performance of a device is the current gain cut-
off frequency. The cut-off frequency of the AlGaN/GaN MODFET is calculated as
݂௧ሺ݉ሻ =
ሺሻ
ଶగƐሺሻ
(27)
By substituting the value of trans-conductance from equation (26), the cut-off frequency can be
evaluated.
(d) Transit time
The transit time effect is the result of a finite time being required for carriers to traverse from
source to drain. Smaller transit times are desirable to attain a high frequency response from a
device. The transit time for the AlGaN/GaN pHEMT is evaluated as
ܶ௧ሺ݉ሻ =
ଵ
ଶగሺሻ
(28)
By putting equation (27) in equation (28), transit time can be obtained.
3. RESULTS AND DISCUSSION
Figure 2. Current-voltage characteristics of AlGaN/GaN HEMT for 50nm gate Length
Figure 2 shows the current-voltage characteristics of AlGaN/GaN HEMT for various values of
gate source voltages. It can be seen that current increases with the increase in drain source
0
100
200
300
400
500
600
0 1 2 3 4 5 6
Drain voltage , vds (V)
Draincurrent,lds(mA/mm)
●●● Experimental [18]
Present model
L = 50nm
Z = 50nm
m = 0.15
di
= 300 Å
Vgs = 1V
Vgs = 0 V
Vgs
= -1V
Vgs = -2 V
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
57
voltage. The device have a maximum drain current density of 501.5mA/mm at a gate bias of
1V and a drain bias of 6V.High currents are attributed to very high sheet charge density, resulting
from large conduction band discontinuity and strong polarization effects. The calculations for
drain currents have been done for Al mole fraction (m) equal to 0.15. This shows that
AlGaN/GaN devices can be effectively used for high power applications.it is seen that it
resembles with the drain characteristics of MOSFET and the drain current gets saturated at an
applied voltage of 4V. The results are in good agreement with the previously published
experimental data.
Figure 3. Variation of transconductance with gate source voltage
Figure 4. Variation of transconductance with drain current
Figure 3 shows the peak value of transconductance which occurs near the gate bias at which the
2-DEG charge density reaches the equilibrium value is 159mS/mm at a gate bias of -1V. The high
transconductance may be attribute to the improved charge control and better transport properties
in the GaN based HEMT. The decrease in transconductance at higher values of Vgs occurs,
because with the 2-DEG density approaches the equilibrium value, the current density no longer
increases proportionally with the gate voltage. The results of the model are in close agreement
0
20
40
60
80
100
120
140
160
180
-4 -3 -2 -1 0 1
Gate voltage, vgs
(V)
Transconductance,gm(mS/mm)
▲▲▲ Experimental[18]
— Present model
L= 50nm
Vds = 4V
d = 400Å
Nd = 2 x1018 cm-3
0
50
100
150
200
0 50 100 150 200 250 300 350
Drain saturation current ,Idsat (mA/mm)
Transconductance,gm(mS/mm)
Vds = 5 V
Nd = 2x 1018
cm-3
Z = 50nm
■■■ Experimental [18]
— Present model
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
58
with the experimental data. The proposed model is valid over a large range of gate lengths and
widths and is thus highly suitable for device structure and performance optimization.
Figure 4 shows the variation of transconductance with the drain saturation current. The
transconductance increases for smaller values of current and then saturate to peak value of
165mS/mm and a drain current of 220mA/mm. The results are in close proximity with the
experimental data which confirms the validity of the proposed model
Figure 5. Variation of cut-off frequency with gate length
Figure 6. Current gain cut-off frequency with drain voltage
Figure 5 shows the variation of cut-off frequency with gate length. Ft falls sharply with an
increase in the gate length. As the channel length is increased, the electron transit time through
the channel also increases, thus causing a reduction of the frequency. A high cut-off frequency of
about 122GHz is obtained at a gate length of 50nm. As compared with experimental data, cut-off
frequency increases with the decrease in gate length.
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5
Gate length,L (µm)→
cut-offfrequency,ft(GHz)→
vds =5v
nd=2 x 10
18
cm
-3
z=75um
µ0=900vm
2
/vs
vs at=1.5 x 10
7
cm/s
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5
Gate length, L (nm)
Cut-offfrequency,ft(GHz)
Vds=5 V
Nd=2 x 1018
cm-3
z=50 nm
vsat=1.5 x 107
cm/s
0
5
10
15
20
25
0 20 40 60 80 100
S ource Drain Bias,Vds (V)
Cut-offFrequency,ft(GHz)
0
5
10
15
20
25
0 20 40 60 80 100
Drain Bias,Vds (V)
Cut-offFrequency,ft(GHz)
L = 50nm
m = 0.15
Nd = 1x1018cm-3
▪▪▪Experimental[18]
̶ Present
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
59
Figure 6 shows the variation of cutoff frequency with drain bias. The cutoff frequency of about
5.2 GHz at a drain bias of 40V is obtained for the present proposed model, which indicates its
higher microwave power ability. As the bias voltage increases, the cutoff frequency exhibits a
slight increase. The results confirm the validity of the proposed model.
Figure 7. variation of drain conductance with drain voltage
Figure 7 shows the variation of output conductance with drain voltage. The drain conductance
decreases with an increase in the drain bias until it becomes zero in saturation region. This
happens because with an increase in the drain bias voltage, the carrier velocity rises gradually and
then saturates. The results are in good agreement with the previously published results.
Figure 8.Variation of cut-off frequency with drain current
Figure 8 shows the variation of cut-off frequency with drain current density. A cut-off frequency
of 9.5GHz is obtained at a drain current of 185mA/mm. when drain current is low,
transconductance is low and hence cut-off frequency is also low. And when transconductance is
high means drain current is high means cut-off frequency is also high. The results are in good
agreement with the experimental results.
0
0.2
0.4
0.6
0.8
1
1.2
0 2 4 6 8 10 12 14
D rain voltage,V ds (V )
Drainconductance,gd(S/mm)
m=0.15
0
0.2
0.4
0.6
0.8
1
1.2
0 2 4 6 8 10 12 14
Drain voltage,Vds (V)
Drainconductance,g
d
(mS/mm)
m = 0.15
Vgs = 5 V
Z = 50 nm
L = 50 nm
Nd = 5x1024
cm-3
0
5
10
15
20
25
0 50 100 150 200 250 300 350
Drain Current,Id (mA/mm)
Cut-offFrequency,ft(GHz)
0
5
10
15
20
25
0 50 100 150 200 250 300 350
Drain Current,Id (mA/mm)
Cut-offFrequency,ft(GHz)
Vds = 3 V
Z = 50 nm
L = 50 nm
T = 300 K
■■■Experimental[18]
─ Present
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
60
4. CONCLUSION
The proposed model is developed for the 2 DEG sheet charge density which is the most important
parameter in characterizing and evaluating the performance of AlGaN/GaN pHEMTs. The model
is developed for the I-V characteristics and small signal parameters of an AlGaN/GaN MODFET
taking into effect of strong polarization effects. The model also shows the potential of
AlGaN/GaN pHEMT as a future candidate for high power, high speed applications. The model
can further be extended to obtain the device capacitances and noise characteristics.
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