With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
Active Power Exchange in Distributed Power-Flow Controller (DPFC) At Third Ha...IJERD Editor
This paper presents a component within the flexible ac-transmission system (FACTS) family, called
distributed power-flow controller (DPFC). The DPFC is derived from the unified power-flow controller (UPFC)
with an eliminated common dc link. The DPFC has the same control capabilities as the UPFC, which comprise
the adjustment of the line impedance, the transmission angle, and the bus voltage. The active power exchange
between the shunt and series converters, which is through the common dc link in the UPFC, is now through the
transmission lines at the third-harmonic frequency. DPFC multiple small-size single-phase converters which
reduces the cost of equipment, no voltage isolation between phases, increases redundancy and there by
reliability increases. The principle and analysis of the DPFC are presented in this paper and the corresponding
simulation results that are carried out on a scaled prototype are also shown.
Sag mitigation in distribution system by using Dynamic voltage Restorer (DVR)IJERA Editor
Power quality is most important concern in the current age. It’s now a day’s necessary with the refined devices, where performance is very perceptive to the quality of power supply. Power quality crisis is an incidence manifest as a typical voltage, current or frequency that results in a failure of end use equipments. One of the major crises dealt here is the power sag. Perceptive industrial loads and distribution networks suffer from different types of service interruptions and outages which results in a major financial loss. To improve the power quality, custom power-devices are used. The device considered in this work is Dynamic Voltage Restorer. This paper shows modelling, analysis and simulation of a DVR test systems using MATLAB.
I have considered single line to ground fault for linear load. The role of DVR is to “compensate load voltage” is examined during the different fault conditions like voltage sag, single phase to ground faults.
Low frequency ac transmission for power systems by Aamir SaleemAamir Saleem
Voltage instability is one of the major issue in
HVAC power network operating at 50 Hz frequency due to
limited power transfer capability and distance limit. The stable
operation of power system must be kept within limits to
increase the efficiency of power transmission system. In this
research Low Frequency AC (LFAC) transmission system has
been proposed as a new power transmission technology to
reduce the losses of transmission network and controlling the
reactive power using Flexible AC transmission device. A
LFAC Transmission lines operates at 16.7Hz frequency for
transmission of power from source to load and use two
Frequency converters at source and load side. The normal
operation of power system depends on the reactive power
flowing through the power transmission lines, which can be
adjusted by a flexible AC transmission device; Static
synchronous compensator. LFAC transmission lines with
STATCOM controller improve the Power system voltage
stability under various disturbances and enhance the power
transmission capability as compare to HVAC transmission.
The simulations are done in Matlab Simulink 2017a .The
Output of Matlab Simulink model shows that voltage will
become Stable and reactive power is compensated for best
performance for power system.
Analysis of multi terminal hvdc transmission system feeding very weak ac netw...eSAT Journals
Abstract This paper presents a line commutated converter (LCC) based multi-terminal HVDC transmission (MTDC) system feeding very weak AC networks with hybrid reactive power compensators (RPC’s) at the inverter AC side. The hybrid compensator is accomplished by the equal mixing of any two of the following compensators: synchronous compensator (SC); static var compensator (SVC); static synchronous compensator (STATCOM). The four-terminal HVDC transmission system model is implemented in the Matlab with the firefly algorithm based optimal proportional integral (PI) controller for rectifiers and inverters control. The transient performances of hybrid RPC’s (SC+SVC, SVC+STATCOM and SC+STATCOM) are studied under various fault conditions and the results are compared with the performance of the SC, SVC and STATCOM to focus the high quality of the hybrid compensators. The simulation results authorize that the equivalent mixture of SC and STATCOM has a steady and fastest response. The results also reveal the supremacy of the firefly algorithm based optimal PI controller over the conventional PI controller. The harmonic present in the inverter side AC quantities is also calculated under steady state operation to assure the quality of power supply. Keywords: MTDC, Very weak AC system, Hybrid RPC, PI controller, Firefly Algorithm.
Active Power Exchange in Distributed Power-Flow Controller (DPFC) At Third Ha...IJERD Editor
This paper presents a component within the flexible ac-transmission system (FACTS) family, called
distributed power-flow controller (DPFC). The DPFC is derived from the unified power-flow controller (UPFC)
with an eliminated common dc link. The DPFC has the same control capabilities as the UPFC, which comprise
the adjustment of the line impedance, the transmission angle, and the bus voltage. The active power exchange
between the shunt and series converters, which is through the common dc link in the UPFC, is now through the
transmission lines at the third-harmonic frequency. DPFC multiple small-size single-phase converters which
reduces the cost of equipment, no voltage isolation between phases, increases redundancy and there by
reliability increases. The principle and analysis of the DPFC are presented in this paper and the corresponding
simulation results that are carried out on a scaled prototype are also shown.
Sag mitigation in distribution system by using Dynamic voltage Restorer (DVR)IJERA Editor
Power quality is most important concern in the current age. It’s now a day’s necessary with the refined devices, where performance is very perceptive to the quality of power supply. Power quality crisis is an incidence manifest as a typical voltage, current or frequency that results in a failure of end use equipments. One of the major crises dealt here is the power sag. Perceptive industrial loads and distribution networks suffer from different types of service interruptions and outages which results in a major financial loss. To improve the power quality, custom power-devices are used. The device considered in this work is Dynamic Voltage Restorer. This paper shows modelling, analysis and simulation of a DVR test systems using MATLAB.
I have considered single line to ground fault for linear load. The role of DVR is to “compensate load voltage” is examined during the different fault conditions like voltage sag, single phase to ground faults.
Low frequency ac transmission for power systems by Aamir SaleemAamir Saleem
Voltage instability is one of the major issue in
HVAC power network operating at 50 Hz frequency due to
limited power transfer capability and distance limit. The stable
operation of power system must be kept within limits to
increase the efficiency of power transmission system. In this
research Low Frequency AC (LFAC) transmission system has
been proposed as a new power transmission technology to
reduce the losses of transmission network and controlling the
reactive power using Flexible AC transmission device. A
LFAC Transmission lines operates at 16.7Hz frequency for
transmission of power from source to load and use two
Frequency converters at source and load side. The normal
operation of power system depends on the reactive power
flowing through the power transmission lines, which can be
adjusted by a flexible AC transmission device; Static
synchronous compensator. LFAC transmission lines with
STATCOM controller improve the Power system voltage
stability under various disturbances and enhance the power
transmission capability as compare to HVAC transmission.
The simulations are done in Matlab Simulink 2017a .The
Output of Matlab Simulink model shows that voltage will
become Stable and reactive power is compensated for best
performance for power system.
Analysis of multi terminal hvdc transmission system feeding very weak ac netw...eSAT Journals
Abstract This paper presents a line commutated converter (LCC) based multi-terminal HVDC transmission (MTDC) system feeding very weak AC networks with hybrid reactive power compensators (RPC’s) at the inverter AC side. The hybrid compensator is accomplished by the equal mixing of any two of the following compensators: synchronous compensator (SC); static var compensator (SVC); static synchronous compensator (STATCOM). The four-terminal HVDC transmission system model is implemented in the Matlab with the firefly algorithm based optimal proportional integral (PI) controller for rectifiers and inverters control. The transient performances of hybrid RPC’s (SC+SVC, SVC+STATCOM and SC+STATCOM) are studied under various fault conditions and the results are compared with the performance of the SC, SVC and STATCOM to focus the high quality of the hybrid compensators. The simulation results authorize that the equivalent mixture of SC and STATCOM has a steady and fastest response. The results also reveal the supremacy of the firefly algorithm based optimal PI controller over the conventional PI controller. The harmonic present in the inverter side AC quantities is also calculated under steady state operation to assure the quality of power supply. Keywords: MTDC, Very weak AC system, Hybrid RPC, PI controller, Firefly Algorithm.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Average current control of DC-DC Cuk Converters as Power Factor CorrectorIJERA Editor
The era of electronic devices in all loads due to the manufacturing technologies replaced many conventional electrical or mechanical loads including lighting loads where Light Emitting Diodes (LEDs) is becoming an emerging technique with many advantages. High frequency switching dc-dc converter is a new technology to control the load and the supply side simultaneously. Due to additional harmonics generated by these switching converters power factor correction has become a necessity in utility side. This paper focuses on the power factor correction of the supply side when employing an ideal LED load with dc-dc Cuk converter. This paper also illustrates the controlling of the power factor correction employing high switching frequency dc-dc converters. The control loops employed are discussed and the strategy for designing the compensator is also explained. The simulated results have been shown to ascertain the accepted performance of the power factor correction converter.
Mitigation of Voltage Sag/Swell with Fuzzy Control Reduced Rating DVRIJERD Editor
Power quality has been an issue that is becoming increasingly pivotal in industrial electricity
consumers point of view in recent times. Modern industries employ Sensitive power electronic equipments,
control devices and non-linear loads as part of automated processes to increase energy efficiency and
productivity. Voltage disturbances are the most common power quality problem due to this the use of a large
numbers of sophisticated and sensitive electronic equipment in industrial systems is increased. This paper
discusses the design and simulation of dynamic voltage restorer for improvement of power quality and
reduce the harmonics distortion of sensitive loads. Power quality problem is occurring at non-standard
voltage, current and frequency. Electronic devices are very sensitive loads. In power system voltage sag,
swell, flicker and harmonics are some of the problem to the sensitive load. The compensation capability
of a DVR depends primarily on the maximum voltage injection ability and the amount of stored
energy available within the restorer. This device is connected in series with the distribution feeder at
medium voltage. A fuzzy logic control is used to produce the gate pulses for control circuit of DVR and the
circuit is simulated by using MATLAB/SIMULINK software.
Performance Evaluation of Three Different Inverter Configurations of DVR for ...ijeei-iaes
The voltage events namely voltage sags and voltage swells represent the most common, frequent and important power quality events in today’s power system. Dynamic voltage restorer (DVR) is one of the key components used to mitigate the supply voltage quality disturbances in terms of voltage sags and swells in the distribution system. It consists of an energy storage unit, a voltage source inverter, a filter, a coupling transformer and the control system. This paper presents three different inverter configurations of dynamic voltage restorer (DVR) for mitigation of voltage events such as voltage sags and swells with sudden addition or removal of the nonlinear load. These three configurations are voltage source inverter based DVR (VSI-DVR), current source inverter based DVR (CSI-DVR) and impedance or Z-source inverter based DVR (ZSI-DVR). The d-q control technique is used to control the operation of the DVR. The response of ZSI-DVR for mitigation of voltage sags and swells are investigated and compared with VSI-DVR and CSI-DVR using MATLAB/SIMULINK environment.
HIPDN: A POWER DISTRIBUTION NETWORK FOR EFFICIENT ON-CHIP POWER DELIVERY AND ...csijjournal
While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power
Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated
Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety
margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model
demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to
evaluate a PDN and its IVRs.
Hearing loss is one of the most common human impairments. It is estimated that by year 2015 more
than 700 million people will suffer mild deafness. Most can be helped by hearing aid devices depending on the
severity of their hearing loss. This paper describes the implementation and characterization details of a dual
channel transmitter front end (TFE) for digital hearing aid (DHA) applications that use novel micro
electromechanical- systems (MEMS) audio transducers and ultra-low power-scalable analog-to-digital
converters (ADCs), which enable a very-low form factor, energy-efficient implementation for next-generation
DHA. The contribution of the design is the implementation of the dual channel MEMS microphones and powerscalable
ADC system.
Almost all electronic components require a DC power supply at present days. The needs of DC power supplies from low voltage scales, medium voltages such as generators, to high voltage scales for high voltage electricity transmission. The improvement of PI controller performances is presented in this paper. The adaptation gains improve transient response of DC-DC Boost Converter several operating conditions. Massachusetts Institute of Technology (MIT) rule is applied as an adaptive mechanism to determine the optimal control parameters in some conditions. The used adaptive control technique is Direct Model Reference Adaptive Control (MRAC), this method as able to control system in some various input voltage. The proposed method has a stable response and able to reach the model reference smoothly. However, the response of the system has instantaneously overshoot and follows the response back of model reference. The responses of proposed controller have short period of rise time, settling time, and overshoot.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Average current control of DC-DC Cuk Converters as Power Factor CorrectorIJERA Editor
The era of electronic devices in all loads due to the manufacturing technologies replaced many conventional electrical or mechanical loads including lighting loads where Light Emitting Diodes (LEDs) is becoming an emerging technique with many advantages. High frequency switching dc-dc converter is a new technology to control the load and the supply side simultaneously. Due to additional harmonics generated by these switching converters power factor correction has become a necessity in utility side. This paper focuses on the power factor correction of the supply side when employing an ideal LED load with dc-dc Cuk converter. This paper also illustrates the controlling of the power factor correction employing high switching frequency dc-dc converters. The control loops employed are discussed and the strategy for designing the compensator is also explained. The simulated results have been shown to ascertain the accepted performance of the power factor correction converter.
Mitigation of Voltage Sag/Swell with Fuzzy Control Reduced Rating DVRIJERD Editor
Power quality has been an issue that is becoming increasingly pivotal in industrial electricity
consumers point of view in recent times. Modern industries employ Sensitive power electronic equipments,
control devices and non-linear loads as part of automated processes to increase energy efficiency and
productivity. Voltage disturbances are the most common power quality problem due to this the use of a large
numbers of sophisticated and sensitive electronic equipment in industrial systems is increased. This paper
discusses the design and simulation of dynamic voltage restorer for improvement of power quality and
reduce the harmonics distortion of sensitive loads. Power quality problem is occurring at non-standard
voltage, current and frequency. Electronic devices are very sensitive loads. In power system voltage sag,
swell, flicker and harmonics are some of the problem to the sensitive load. The compensation capability
of a DVR depends primarily on the maximum voltage injection ability and the amount of stored
energy available within the restorer. This device is connected in series with the distribution feeder at
medium voltage. A fuzzy logic control is used to produce the gate pulses for control circuit of DVR and the
circuit is simulated by using MATLAB/SIMULINK software.
Performance Evaluation of Three Different Inverter Configurations of DVR for ...ijeei-iaes
The voltage events namely voltage sags and voltage swells represent the most common, frequent and important power quality events in today’s power system. Dynamic voltage restorer (DVR) is one of the key components used to mitigate the supply voltage quality disturbances in terms of voltage sags and swells in the distribution system. It consists of an energy storage unit, a voltage source inverter, a filter, a coupling transformer and the control system. This paper presents three different inverter configurations of dynamic voltage restorer (DVR) for mitigation of voltage events such as voltage sags and swells with sudden addition or removal of the nonlinear load. These three configurations are voltage source inverter based DVR (VSI-DVR), current source inverter based DVR (CSI-DVR) and impedance or Z-source inverter based DVR (ZSI-DVR). The d-q control technique is used to control the operation of the DVR. The response of ZSI-DVR for mitigation of voltage sags and swells are investigated and compared with VSI-DVR and CSI-DVR using MATLAB/SIMULINK environment.
HIPDN: A POWER DISTRIBUTION NETWORK FOR EFFICIENT ON-CHIP POWER DELIVERY AND ...csijjournal
While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power
Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated
Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety
margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model
demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to
evaluate a PDN and its IVRs.
Hearing loss is one of the most common human impairments. It is estimated that by year 2015 more
than 700 million people will suffer mild deafness. Most can be helped by hearing aid devices depending on the
severity of their hearing loss. This paper describes the implementation and characterization details of a dual
channel transmitter front end (TFE) for digital hearing aid (DHA) applications that use novel micro
electromechanical- systems (MEMS) audio transducers and ultra-low power-scalable analog-to-digital
converters (ADCs), which enable a very-low form factor, energy-efficient implementation for next-generation
DHA. The contribution of the design is the implementation of the dual channel MEMS microphones and powerscalable
ADC system.
Almost all electronic components require a DC power supply at present days. The needs of DC power supplies from low voltage scales, medium voltages such as generators, to high voltage scales for high voltage electricity transmission. The improvement of PI controller performances is presented in this paper. The adaptation gains improve transient response of DC-DC Boost Converter several operating conditions. Massachusetts Institute of Technology (MIT) rule is applied as an adaptive mechanism to determine the optimal control parameters in some conditions. The used adaptive control technique is Direct Model Reference Adaptive Control (MRAC), this method as able to control system in some various input voltage. The proposed method has a stable response and able to reach the model reference smoothly. However, the response of the system has instantaneously overshoot and follows the response back of model reference. The responses of proposed controller have short period of rise time, settling time, and overshoot.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
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Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
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Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
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Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
This paper proposes a single-bit ADC system based Proportional and Integral (PI) controller to maintain a desired level of power transfer efficiency in Capacitive Power Transfer (CPT) systems. In this paper, a simple single-bit ADC system i.e., Single-Bit Modulator (SBM) is considered as an alternative to the commonly used multi-bit ADC systems. Unique features of employing SBM are 1) its ability to convert analog signals into single-bit signals and 2) its easy integrability in digital chips with linear variable differential transformers (LVDTs) such as FPGAs. A SBM based PI (SBM-PI) controller is designed to judicially interface with the single-bit output of SBM. The proposed (SBM-PI) controller guarantees less hardware resources, latency and regulates the output voltage to provide the desired power transfer efficiency. The behavior of SBM-PI controller is compared to that of a conventional multi-bit controller, with the results of both controllers being identical. The effectiveness of the proposed controller with SBM is further demonstrated using the experimental prototype of CPT by implementing a SBM-PI controller using $16$ MHz ATmega8 microcontroller. The experimental results from a laboratory prototype illustrate that SBM-PI controller successfully regulates the output voltage of CPT to control the power flow.
A Review on Optimization Techniques for Power Quality Improvement using DSTAT...ijtsrd
As demand for electricity has risen exponentially, power production and transmission are affected by scarce energy, environmental constraints and other losses. Soft computing methods to fix the sag, swell and disruption of the supply voltage in the distributed device. At present, a broad variety of highly versatile controls that leverage on newly available power electronics components are evolving for custom power applications. Control electronic equipment intended to improve the stability and efficiency of electricity flows in low voltage distribution networks. The control algorithm is used to derive the fundamental weighted value of the active and reactive power components. Using a digital signal processor, DSTATCOM is built and its output as a DSTATCOM is found to be satisfactory for different types of loads. Amit Radhakrishna Parhad | Pramod Kumar Rathore "A Review on Optimization Techniques for Power Quality Improvement using DSTATCOM (Neural Network Approach)" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd42403.pdf Paper URL: https://www.ijtsrd.comengineering/electrical-engineering/42403/a-review-on-optimization-techniques-for-power-quality-improvement-using-dstatcom-neural-network-approach/amit-radhakrishna-parhad
Field Programmable Gate Array (FPGA) - Based Pulse Width Modulation for Singl...IJSRD
Active filtering of electric power has now become a mature technology for harmonic and reactive power compensation in two-wire (single phase), three-wire (three phase without neutral), and four-wire (three phase with neutral) ac power networks with nonlinear loads. This paper presents the simulations of Field programmable gate array (FPGA) - based single phase hybrid active power filters of two different configurations using Xilinx system generator. The former one with the hybrid combination of series active power filter and shunt passive filter is designed to mitigate the distortions in source voltage and source current due to the voltage source type harmonic load and the latter one with the hybrid combination of shunt active power filter and shunt passive filter is designed to mitigate the harmonics in source current due to the current source type harmonic load.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions to decrease power consumption while maintaining the quick transient response to signal variations. LDO voltage regulators, as power management devices should adjust to modern technological and industrial trends. To increase the current capability with a minimum standby quiescent current under small-signal operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout. As a result, the efficiency gets increased.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism
reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of
IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions
to decrease power consumption while maintaining the quick transient response to signal variations. LDO
voltage regulators, as power management devices should adjust to modern technological and industrial
trends. To increase the current capability with a minimum standby quiescent current under small-signal
operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the
dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout.
As a result, the efficiency gets increased.
Simulation of D-STATCOM to study Voltage Stability in Distribution systemijsrd.com
This paper presents the simulation of D-statcom to understand the improvement of voltage stability [1] of distribution system. The power circuits of the D-STATCOM and distribution networks are made up of simpower system blocks, while the control circuits made with the simulink blocks The STATCOM is applied to regulate transmission voltage to allow greater power flow in a voltage limited transmission network, in the same manner as a static var compensator (SVC), the STATCOM has further potential by giving an inherently faster response and greater output to a system with depressed voltage and offers improved quality of supply. The main applications of the STATCOM are; Distribution STATCOM (D-STATCOM) exhibits high speed control of reactive power to provide voltage stabilization and other type of system control. The DSTATCOM protects the utility transmission or distribution system from voltage sag and /or flicker caused by rapidly varying reactive current demand. During the transient conditions the D-STATCOM provides leading or lagging reactive power to active system stability, power factor correction and load balancing.
Analysis of Total Harmonic Distortion (THD) Level of Distribution Network Usi...IJERA Editor
The modern sensitive, Non-linear and sophisticated load affects the power quality. Dynamic Voltage Restorer (DVR) provides the fast, flexible and efficient solution to improve the power quality for such distribution network [8]. The active power, reactive power, variation of voltage, flicker, harmonics, and electrical behavior of switching operations are the major source of affecting power quality. The intent of this paper is to demonstrate the improvements obtained with DVR in power system network using MATLAB/SIMULINK. In this paper, an overview of the DVR, its functions, configurations, components, control strategies are reviewed. The Simulation results are presented to illustrate the performance of DVR in Total Harmonic Distortion (THD). The results showed clearly the performance of using DVR in improving THD level.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCUITRY O PERATING A T S UBTHRESHOLD
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
DOI : 10.5121/vlsic.2015.6201 1
ADAPTIVE SUPPLY VOLTAGE MANAGEMENT FOR
LOW POWER LOGIC CIRCUITRY OPERATING AT
SUBTHRESHOLD
Rehan Ahmed1
1
Department of Electrical and Computer Engineering, Oklahoma State University,
Stillwater,OK, USA
ABSTRACT
With the rise in demand of portable hand held devices and with the rise in application of wireless sensor
networks and RFID reduction of total power consumption has become a necessity. To save power we
operate the logic circuitry of our devices at sub-threshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage hence the threshold variation causes profound variation
of ION and IOFF the ratio of which affect the speed of a circuit drastically. So to mitigate this problem we
present a adaptive power management circuit which will determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to regulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter.
KEYWORDS
Adaptive; Low power; Switch Capacitor; Converter; Sub-threshold
1. INTRODUCTION
This paper discusses about the supply voltage management for logic parts which represents the
microcontroller and the digital circuitry of hand held or portable devices. Most these hand held
or portable devices used do not need to run at very high speed and are also desired to consume
low power so it would run for longer. Thus considering the above reasoning the digital or the
logic parts should be operated in subthreshold. Circuits operating in subthreshold are found to
consume less energy for active operation and dissipate less leakage power also with new process
technology subthreshold circuit designing has gain much more favour. In severely energy
constrained system like in case of passive RFID, medical implantable device, wearable sensors
or portable devices where conserving energy is the primary objective and the speed is high
enough, subthreshold circuits are ideal for this type of applications. For transistor operating in
subthreshold the gate tunnelling current, gate induce drain current, DIBL effect, reverse bias
diode leakage from the source and drain to the bulk leakage effects become negligible, hence all
these contribute to lower power[1]. In subthreshold transistor channel is not inverted and current
flow is by diffusion where the current is given by
(1)
ID represent drain current IS specific current, UT thermal voltage, n ideality factor and VTH is the
threshold voltage. Equation (1) shows ID varies exponentially with the (VGS – VTH) term. As
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
2
CMOS technology is continuously scaled down, the effect of temperature and process variation
are becoming more prominent. Along with these in deep submicron processes the effects such
as short channel effect, reverse short channel effect [2], narrow channel effect and reverse
narrow channel effect [3] causes variation in VTH. The VTH variation causes the variation of ION
and IOFF, the ratio of which affect the speed of a circuit. As the drain current ID varies
exponentially with VTH in subthreshold, the effect is more profound. Thus this problem of VTH
variation due to process, temperature and technology can be mitigated by overdesigning the
circuits which is not cost effective and also consumes excess power. Alternate methods to
compensate VTH variation are 1) adaptive body biasing [4,5,6] 2) adaptive supply voltage [7,8]
and 3) adaptive body biasing and supply voltage in tandem. In this work adaptive supply
voltage to compensate VTH variation has been applied. This concept of dynamic [9,10]supply
voltage scaling is well documented approach in power reduction where the supply voltage is
determined according to the speed the circuit needs to support. In this work discussed this
technique is being applied to compensate for the reduction in reliability due to device VTH
variability. The supply voltage is increased dynamically to mask the variation effect of VTH to a
value which ensure the systems target performance [19,20]. As a result in cases where the
threshold voltage is higher (slow slow process) the supply voltage is increased and additional
power is consumed to ensure reliability. The discussed adaptive supply voltage management
circuit is designed to supply the controller of a smart passive RFID operating at 2MHz.
2. System Description
2.1. Critical Path Monitoring Circuit
Timing of a circuit is determined based on the performance requirement, power dissipation,
technology limitation and design architecture. Hence once the cycle time is fixed and the design
begins, a number of timing paths within the integrated circuit exceeds the cycle time. These path
called the critical paths must be retimed to meet the cycle time. The critical paths are
benchmarks of system timing as such critical path monitoring (CPM) can provide real time
effects due to the VTH variation. As a result in adaptive supply voltage scaling (ASV) designing
an accurate Critical path is very important. These critical path are monitored by generation of a
feedback signal with which the supply voltage is controlled at or near its optimal value so that
the circuit operate correctly at the target speed. CPMs needs to be located in the areas where the
most severe variation is likely to occur. Inaccuracy in CPM will result in system failure [11].
Figure 1 Schematic of CPM circuit
In developing the CPM several critical path replicas are implemented in order to better
represent the critical path behavior. All replica paths selections are ANDed so as to select the
longest delay path among the CPRs which represent the worst case of the CPM. Figure 1 shows
a CPM schematic, the circuit composed of D flipflops, critical path replicas and timing checker.
In this circuit a signal is entered which goes through all the CPRs but the output appears from
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
3
the worst of all the CPRs as mentioned before confirming the worst delay. The output finally
reaches the timing checker which is composed of a D flipflop, and AND gate, the output of
which is applied to the reference selector controller. In the reference controller during each
cycle if the output of the timing checker is “0” the supply voltage is increased by 50mVuntil the
output is “1” In this case the reference voltage is start with 350mV and the maximum is limited
to 500mV. Single cycle of the reference selector controller circuit consists of three states or
three clock cycle. First a signal is applied through the CPRs in the second state it checks
whether the supply voltage is sufficient for the signal through the CPRs to meet the
timing and generates output S0 and S1 of a two bit counter accordingly. Finally in the
third state everything is reset and state 1 start again. While designing the CPM identical
timing delay is inserted in the cock network to compensate for the ANDs in the CPRs.
Table I gives the reference voltage selected for different S0 and S1 combination
Table 1. Reference voltage controller output
Frequency
applied
S0 S1 Vref
2 MHz 1 0 450mV
1Mhz 0 1 400mV
750 KHz 0 1 400mV
500KHz 0 1 400mV
250 KHz 0 0 350mV
2.2. DC-DC Power Converter
The DC-DC power converter is a part of the power management circuit. The DC-DC converter
converts the unregulated DC input voltage to a regulated DC output voltage. This regulated
voltage can be either step-up or step-down. The DC-DC converter can be broadly divided in to
three category a) Linear regulator b) Inductor based switch mode regulator c) Capacitor based
switch mode regulator, however the working principle of all these regulators is same. The
output voltage is regulated with reference to a known reference voltage, with the help of a
closed loop feedback controller. Some of the specs that can be used to characterize a DC-DC
power converter are a) Efficiency b) Line regulation c) Load regulation and d) noise which are
explained briefly below. One of the important parameter of a DC-DC converter is efficiency
(2)
Where Pout is the output power, Pin is the total input power and Ploss is the power loss of the
converter itself. Ideally voltage conversion should take place without any loss but due to various
power loss factors, switch resistance, parasitic Cs etc. practical efficiency is lower than the ideal
value, so efficiency is a important factor especially in case like where we want to operate on
low power. For a DC-DC converter the other two important parameters to measure the
regulation performance are load regulation and line regulation
(3)
and
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
4
(4)
Lastly switching noise characteristic of the DC-DC converter is another critical spec. As in
many low power applications like wireless sensors containing RF transmitter component or
some other devices having noise sensitive components, so if the converter has large noise
component, this noise can couple with the devices and cause problem. Hence for noise sensitive
application low noise power supply is desired.
The different type of regulator that we mentioned before and the reason for choosing the switch
capacitor based converter instead of the other two is discussed below.
a) Linear regulator: Linear regulators are active linear analog circuits that are used to convert a
noisy raw or unregulated DC power source in to well regulated power source. As a linear
regulator does not have any reactive (magnetic or capacitive) components and in addition to that
it has a simple design. Hence the linear regulator are well suitable for analog or noise sensitive
applications. One of the architecture is the low dropout (LDO) regulator shown in figure 2. The
drop out voltage refers to the minimum voltage drop between input and output voltages required
to maintain the Vout and dictates efficiency. The LDO consist of an error amplifier and a pass
transistor, acting as a voltage controlled current source. The error amplifier continuously
monitors the output voltage against a reference voltage. Based on the regulation error, the
amount of current delivered to the load is controlled to maintain the output voltage at the desire
Figure 2 Low dropout Linear regulator
value. High efficiency is achieved only for low drop out voltage but the efficiency drops
drastically for high dropout value thus in this case where unregulated voltage is between 900mV
and 1.2V and the regulated voltage is say approximately 450mV the LDO is not a suitable
choice.
b) Inductor Base Switch Mode Power Converter: Inductor base switch mode power converter
consist of a power stage and a closed loop feedback controller to regulate the output voltage.
The power stages consist of switches along with an inductor-based temporary energy storage
element. This is achieved by storing the input energy temporarily during the charge phase of the
inductor and then releasing that energy to the output at a different voltage during the discharge
phase. Figure 3 illustrates the power stage implementations for the common inductor base
switch mode converters. The output voltage is regulated by a feedback controller which
determines the duty cycle of the power stage to maintain the desired output voltage, regardless
of line, load or component variations. These converters are highly sophisticated, multi-mode
power delivery modules, capable of operating at efficiencies of over 90 % for a wide range of
power levels. The major disadvantage of inductor base power converters is its difficulty for on
chip integration. Another problem with the inductor base converter is the EMI (electromagnetic
induction) due to the inductor.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
5
Figure 3 Power stage topology of Switch mode buck converter
2.3. Step-Down Voltage conversion Using Switch Capacitor DC-DC Conversion
For the power regulation in this system, power stage of the switch capacitor (SC) DC-DC
converter for step-down voltage conversion is implemented. In the step-down SC converter, the
pumping capacitors are placed between the input and the output of the converter during the
charge phase and during the discharge phase, the pumping capacitors are placed in parallel with
the output filtering capacitor. The number of pumping capacitor used in SC converter
determines the number of gain ratios (GRs) attained
ܖܑ܄ − ܜܝܗ܄
ܖܑ܄ − ܜܝܗ܄
(a)1/3
ܖܑ܄−ܜܝܗ܄
ܖܑ܄−ܜܝܗ܄
(b)1/3 (c)1/2
(d)1/2 (e)2/3 (f)2/3
Figure. 4 Charge phase and discharge phase capacitor configuration of different GR
Having higher number of capacitor will allow us to have more GRs but it would also increase
the complexity of the system along with the area of the converter. The topology outlined in [12]
is used where only two pumping capacitor are used to provide gain ratio of 1/3, 1/2 and 2/3 this
topology also helps us minimize the bottom plate capacitor loss. The configuration of one of
these gain ratios are discussed below. Figure 4(a) and (b) shows the capacitor configuration for
GR=1/3 during the charge phase both the pumping capacitor CP1 and CP2 are connected in
series between the input and the output node. This connection charges the capacitor to (Vin-
Vout)/2 . During the discharge phase the CP1 and CP2 are connected in parallel with Cout and
Vout is calculated as
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.2, April 2015
6
(5)
(6)
The other configurations are achieved in similar fashion. A SC converter’s efficiency is related
to its voltage conversion gain. As the conversion gain is fixed in SC so when the input power is
highly variable, the efficiency could drop dramatically. Hence, a reconfigurable SC converter
with variable conversion gain is desirable. The reconfiguration of the converter is done by use
of nine switches as shown in Figure 4. By systematically turning the switches on/off, all of the
above mentioned capacitor configurations can be implemented. GR of 2/3 required seven
switches, GR of 1/2 required eight switches and finally GR of 1/3 required seven switches. The
circuit or the switch operations for all the GRs are shown in Figure 5 and TABLE II. Now the
controller selects the appropriate GR based upon the input voltage and the reference voltage. As
each cycle is divided in to two phases, charging phase ϕ and discharging phase ϕ! TABLE II
present the gate voltage signals to implement all the GRs where ϕ and ϕ! are non-overlapping
clocks.
Table 2.
GR S1 S2 S3 S4 S5 S6 S7 S8 S9
1/3 ϕ off Φ! ϕ off ϕ Φ! ϕ Φ!
1/2 ϕ ϕ Φ! ϕ ϕ ϕ Φ! ϕ off
2/3 ϕ ϕ Φ! off ϕ ϕ off ϕ ϕ
Figure. 5 Switch capacitor power stage with reconfigurable multiple step-down GRs
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The efficiency of any voltage converter can be expressed as
(7)
For SC converter equation (7).can be written as
(8)
Where Iout is the average output current required at the regulated voltage. The Ploss is the power
loss in the converter in the power stage which includes i) redistribution loss ii) conduction loss,
iii)switching loss, and iv)reversion loss. Vin is the raw input voltage, Iin is the input current and
Iq is the controller current.
Redistribution loss occurs due to the fact that energy is lost when two capacitors with different
voltages are connected together, reversion loss is a form of redistribution loss where charges are
lost from the output capacitor Cout to power stage capacitors if proper attention is not paid in
timing the on and off operation of the switches. To avoid any reversion loss a non overlapping
clock is used to control the charge and discharge phase on, off operation of the switches. The
two main contributors to the loss factor are the conduction loss and switching loss [13]. In SC
converters, the switches in the power stage are implemented using MOSFET transistors. The
transistors are operated in the triode region where the current voltage relationship is given by
(9)
In (9) µ is the mobility of the carriers, COX is the oxide thickness, W is the width of the
transistor, L is the length of the transistor, Vth is the threshold voltage and VGS is the gate to
source voltage. Hence when current flows through the transistor the Ron resistance causes the
conduction loss. This loss can be minimized by increasing the width of the transistor but by
increasing the width to reduce Ron increases Cgs the gate to source capacitance. Hence the
switching loss will increase which is discussed next. Since these parasitic capacitances are
switched during each switching period, the switching loss is given by (10).
(10)
Where fs is the switching frequency. From the equation (10) to reduce switching loss, W and L
need to be minimized as well as the gate to source voltage. For switching transistor, minimum
allowed L is used. However, reducing W has detrimental effect of conduction loss but there
exists an optimal point for W and fs where the total conduction and switching loss reaches a
minimum.
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Figure. 6 Typical voltage wave form observed across pumping capacitor CP
The loss calculation is done in this paper in a similar fashion as in [14] as depicted in figure 6 .
CP is charged and discharged exponentially to VH and VL during the charge time tc and the
discharge time td, respectively. τ is the charge and discharge time constant. The net charge (∆Q)
to the load IL is thus
(11)
(12)
(13)
Now using equation (12) and (13) where β,γ,δ,ζ are constants we get
(14)
Now replacing (VH – VL) with ∆V in equation (14) and solving for Vout we get
(15)
From equation (15) then we can write the variation of Vout is
(16)
So power loss due to this variation is
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(17)
Another major power loss is due to the switching loss as discussed previously depend on the
size of the switch and the frequency thus the total power due to switching.
(18)
Where Cox is the unit oxide capacitance, σ is fabrication process related coefficient and Li, Wi
are the length and width of the ith switch. To reduce the switching power loss we have to reduce
the parasitic capacitance so we choose the Length L to be minimum, so total power loss,
(19)
The time tc and td are dependent on the turn-on resistance in the charge and discharge path
where total Ron is given by
(20)
Where M and stand for the total number of power transistor in the charge and discharge path.
From equation (19) and (20) we see that the total power loss is dependent on switching
frequency fs and Wj. Hence we need to choose Wj and fs such that we have least power loss and
thus achieve high efficiency. As we see from Table II the GR 1/2 uses eight of the switches so
to optimize we plot the Ploss with respect to Wj and fs with the help of matlab programming for
this GR. The plot is shown in figure 7
Figure. 7 Mesh plot of power loss with respect to fS and width
2.5. Control Circuit
The controller of the switch converter is a bang bang control or Hysteric control. The output
voltage of the converter is maintained within the hysteric band centred about the reference
voltage. The hysteric controller is in-expensive, simple and easy-to-use architecture. The
benefits of hysteretic control are that it offers fast load transient response and eliminates the
need for feedback-loop compensation and displays inherently stable performance [15,16] .
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Figure 8 shows the control circuit block diagram. The reference voltage from the CPM is fed to
a hysteric comparator, which controls the clock switch of the power stage of the converter and
regulate the output voltage by switching the clock on and off. The comparator has a Hysteresis
of 15mV and works at 10.4MHz which is four times the clocking frequency of the SC converter
If output voltage Vout is at or below the level of the reference voltage Vref minus the hysteresis
voltage VHYS, output of the hysteretic comparator is high and Q is turned on. This is the power
stage on-state and it causes the output voltage to increase. When the output voltage Vout
reaches or exceeds the reference Vref plus the hysteresis VHYS, the output of the hysteretic
comparator turns low and then Q is turned off. This is the power stage off-state, and it causes
the output voltage to decrease as the filter capacitor bleed. This hysteretic method of control
keeps output voltage within the hysteresis band around the reference voltage. Whenever there is
voltage variation caused by a load transient, the output is recovered as quickly as the power
filter allows which is determined by the output capacitor Cout which has a large value to support
large transient current and low output ripple. In addition to its fast transient response, this
control scheme provides for simple design without any control loop stability concerns [17,18].
The controller algorithm is shown in Figure 9 the controller first takes the digital output from
the CPM and selects the reference voltage. The SC power stage clock is on and the GR of the
converter is 1/3, the output voltage starts rising. In the mean time the comparator goes on
comparing the Vout to the Vref as long as Vout < Vref the power stage clock is on when Vout>Vref
the clock is switched off and the load is switched on During the comparison a counter checks
the number of cycle its taking to reach the steady state that is when the clock is switched off for
the first time, if the counter is reaches seven then the GR is increased by one step otherwise as
said before the GR is kept same and the clock is switched off and the load is switched on. After
the steady state is reached for the first time the comparator checks Vout when it reaches or
exceeds the reference Vref plus the hysteresis VHYS, the output of the hysteretic comparator turns
low and the clock is off. The load current in the mean time bleeds the output capacitor and the
Vout starts falling when Vout is at or below the level of the reference Vref minus the hysteresis
VHYS the clock is again turned on Now after the first steady state case the power stage clock is
on for more than four clock cycle the GR is again increased by one step from its present value
as because the GR is not sufficient to sustain the load. In this way by switching the clock on and
off the converter is maintained within the hysteric band
Figure. 8 Block diagram of the control circuit
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Figure. 9 Control algorithm of the converter
3.RESULTS
The converter was designed and simulated with IBM180nm process. All the simulation were
done on cadence. The converter was designed considering a fully integrated solution to power a
state machine working with subthreshold supply voltage and con summing average current of
4.5µA in this simulation we have constant Vin of 1V , Vref of 400mVand the load current is
changed from 0µA to 6µA then to 9µA and then again to 6µA. It can be seen that first the gain
ratio is changed from 1/3 to 1/2 before the load is switched on after that Vout remain within
395mV to 409mV thus we can see the control is stable load regulation is good . The simulation
result is shown in figure 10.
Figure. 10 Simulation results of the load regulation of the converter
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After the load regulation the simulation for line regulation is done. In this simulation the load is
kept constant and the reference voltage is same as 400mV and the Vin is changed from 1.2V to
900mV and then again to 1.2V. In this case also first the GR is changed from 1/3 to 1/2 and
Figure. 11 Simulation results of the line regulation of the converter
after that Vout is maintained between 395mV and 430mV in this case the ripple is a little higher
but is less than 10% which is sufficient for the circuit it is used for the simulation result is
shown in figure 11. The highest efficiency we achieve is around 86%. Which is quite high
compared to the LDO efficiency which is only 41% while supplying a regulated voltage of
450mV@ 6µA from a raw voltage of 900mV [21]
4. CONCLUSIONS
A adaptive power management circuit for the logic circuitry of an RFID operating in sub-
threshold is presented in this paper. The adaptive technique is applied to mitigate the affect of
threshold variation. Also the to regulate the power we have used the switch capacitor DC-DC
power converter instead of the LDO which has a very low efficiency as the dropout voltage is
high in this case or the Inductor Base Switch Mode Power Converter which has the problem of
bulky coil and EMI noise. From above we see that our adaptive circuit is working and we can
achieve around 86% efficiency with less than 10% ripple in the regulated voltage. The design is
done with 180nm IBM process and is ready for fabrication.
Papers in this format must not exceed twenty (20) pages in length. Papers should be submitted
to the secretary AIRCC. Papers for initial consideration may be submitted in either .doc or .pdf
format. Final, camera-ready versions should take into account referees’ suggested amendments.
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