This document presents a general framework for formally verifying digital electronic circuits. It discusses representing circuits as finite state machines and using Linear Temporal Logic (LTL) to specify properties to verify. Key points:
- Digital circuits and computer programs are similar in nature, so methods used to verify programs can also verify circuits.
- A circuit can be modeled as a finite state machine by creating a state for every combination of inputs to each logic gate.
- LTL allows specifying temporal properties of the circuit to verify, using operators like "Next", "Until", "Eventually", and "Always".
- The framework was tested on sample circuits, proving properties using a symbolic model checker on the LTL specifications