This document summarizes a research paper that presents a method for detecting stuck-at faults in digital circuits at the register transfer level (RTL) using the concept of textio in VHDL. It begins with an introduction to the need for high-level fault simulation due to increasing design complexity. It then discusses related work involving adding buffers, using validation test sets, and automatic test pattern generation. The document outlines the proposed RTL fault model and fault injection methodology. It presents results of applying the textio concept to detect stuck-at faults and compares output files to determine fault locations. The conclusion states that this textio method allows easier fault coverage estimation than prior methods and leads to better efficiency in detecting stuck-at faults in RT
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
Fault Modeling for Verilog Register Transfer Levelidescitation
As the complexity of Very Large Scale Integration
(VLSI) increases, testing becomes tedious. Currently fault
models are used to test digital circuits at gate level or at levels
lower than gate. Modeling faults at these levels, leads to
increase in the design cycle time period. Hence, there is a
need to explore new approaches for modeling faults at higher
levels. This paper proposes fault modeling at the Register
Transfer Level (RTL) for digital circuits. Using this level of
modeling, results are obtained for fault coverage, area and
test patterns. A software prototype, FEVER, has been developed
in C which reads a RTL description and generates two output
files: one a modified RTL with test features and two a file
consisting of set of test patterns. These modified RTL and test
patterns are further used for fault simulation and fault
coverage analysis. Comparison is performed between the RTL
and Gate level modeling for ISCAS benchmarks and the
results of the same are presented. Results are obtained using
Synopsys, TetraMax and it is shown that it is possible to achieve
100% fault coverage with no area overhead at the RTL level
In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, First is Functional Testing, which undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response. It does not consider how the circuit is designed, but only that it gives the correct output during test and second one is Fault Modelling in whichto consider the possible Faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.The faults which are likely to occur on the wafer during the manufacture of the ICs, and compute the result on the circuit output(s) with or without each fault present. Each of the final series of tests is then designed to show that a particular fault is present or not.
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
Fault Modeling for Verilog Register Transfer Levelidescitation
As the complexity of Very Large Scale Integration
(VLSI) increases, testing becomes tedious. Currently fault
models are used to test digital circuits at gate level or at levels
lower than gate. Modeling faults at these levels, leads to
increase in the design cycle time period. Hence, there is a
need to explore new approaches for modeling faults at higher
levels. This paper proposes fault modeling at the Register
Transfer Level (RTL) for digital circuits. Using this level of
modeling, results are obtained for fault coverage, area and
test patterns. A software prototype, FEVER, has been developed
in C which reads a RTL description and generates two output
files: one a modified RTL with test features and two a file
consisting of set of test patterns. These modified RTL and test
patterns are further used for fault simulation and fault
coverage analysis. Comparison is performed between the RTL
and Gate level modeling for ISCAS benchmarks and the
results of the same are presented. Results are obtained using
Synopsys, TetraMax and it is shown that it is possible to achieve
100% fault coverage with no area overhead at the RTL level
In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, First is Functional Testing, which undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response. It does not consider how the circuit is designed, but only that it gives the correct output during test and second one is Fault Modelling in whichto consider the possible Faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.The faults which are likely to occur on the wafer during the manufacture of the ICs, and compute the result on the circuit output(s) with or without each fault present. Each of the final series of tests is then designed to show that a particular fault is present or not.
Formal Method for Avionics Software VerificationAdaCore
This talk will give examples of Airbus use of Formal Methods to verify avionics software, and summarises the integration of Formal Methods in the upcoming ED-12/DO-178 issue C. Firstly, examples of verification based on theorem proving or abstract interpretation will show how Airbus has already taken advantage of the use of Formal Methods to verify avionics software. Secondly, we will show how Formal Method for verification has been introduced in the upcoming issue C of ED-12/DO-178.
Formal Method for Avionics Software VerificationAdaCore
This talk will give examples of Airbus use of Formal Methods to verify avionics software, and summarises the integration of Formal Methods in the upcoming ED-12/DO-178 issue C. Firstly, examples of verification based on theorem proving or abstract interpretation will show how Airbus has already taken advantage of the use of Formal Methods to verify avionics software. Secondly, we will show how Formal Method for verification has been introduced in the upcoming issue C of ED-12/DO-178.
Air pollution is the introduction of particulates, biological molecules, or other harmful materials into Earth's atmosphere, causing disease, death to humans, loss of breath, damage to other living organisms such as food crops, or the natural or built environment. Air pollution may come from anthropogenic or natural sources.
Extract the ancient letters from decoratedIJERA Editor
Nowadays, large databases of ornaments of the hand-press period are available and need efficient retrieval tools
for history specialists and general users. This article deals with document images analysis. The purpose of our
work is to automatically determine the letter represented in an ornamental letter image. Our process is divided
into two parts: Wavelet transformation: Segmentation of the ornamental letter followed by a recognition step.
The segmentation process uses multi-resolution analysis to filter background decorations followed by
binarisation and morphologic reconstruction of the expected letter.
Keywords - segmentation, multiresolution analysis, ornemental lettres, Wavelet transform
Energy Efficient Wireless Sensor Network Using Network Coding Based Multipath...IJERA Editor
Network Coding is most promising aspect of WSN. This Network Coding method is combined with multipath routing protocol to form NCMR protocol.(network coding based multipath routing protocol).This protocol is used to obtain energy efficient wireless sensor network.. These protocol leads to decrease the number of constrain routes & the total time of transmission. This protocol is applied on unicast and multicast network separately. And comparison is done with traditional multipath routing protocol for same unicast and multicast network. Simulation result shows energy consumption of NCMR multicast is lower than NCMR unicast and also than TMR unicast as well as multicast. This work is proved by the simulation analysis results. The used multipath model is based on braided multipath routing, and the network coding method is random linear network coding (practical network coding). In braided network multiple paths to the sink nodes are created for each source node, and the packets encoded at source nodes are transmitted through the braided multipath network model. Then, intermediate nodes re-encode these received packets and transfer these new packets to next cluster. Finally, the multiple sink nodes decode the packets received from different paths and recover the original data. Results of the analysis show that multicast NCMR provides more reliability. We compare multicast NCMR routing protocol with NCMR unicast & also with traditional multipath routing protocol for unicast and multicast networks, in terms of the packet loss, energy consumption, successful delivery ratio & end to end delay when a packet is transmitted Some special simulations are carried out specially for NCMR multicast i.e. effect of number of nodes on energy consumption, packet loss & end to end delay.
Optimization of a Shell and Tube Condenser using Numerical MethodIJERA Editor
The purpose of this study was to investigate the effect of installation of the tube external surfaces, their parameter and variable in a shell-and-tube condenser. Variation of heat transfer coefficient with each variable of shell and tube condenser was measured each test. The optimization tube outside diameter size was analyzed and use extended surface area attached tube with tube material and tube layout and arrangement (Number of tube a triangular or hexagonal arrangement) on shell-and tube condenser. The computer programming was used to get faster output in less time. Results suggest that mean heat transfer coefficient in variable condition were mainly at velocity is fixed. And also average additional surfaces and tube layout and the arrangement comparison with the quantity of the heat transfer.
Polynomial Function and Fuzzy Inference for Evaluating the Project Performanc...IJERA Editor
The objectives of this paper are two folds. The first one is to improve the time forecasting produced from the well known Earned Value Management (EVM), using the polynomial function. The time prediction observed from the polynomial model, which is compared against that observed from the most common method for time forecasting (critical path method), is a more accurate (mean absolute percentage of error is less than 2%) than that observed from the conventional deterministic forecasting methods (CDFMs). The second is to evaluate and forecast the overall project performance under uncertainty using the fuzzy inference. As the uncertainty is inherent in real life projects, the polynomial function and fuzzy inference model (PFFI) can assist the project managers, to estimate the future status of the project in a more robust and reliable way. Two examples are used to illustrate how the new method can be implemented in reality.
Automatic Road Extraction from Airborne LiDAR : A ReviewIJERA Editor
LiDAR is the powerful Remote Sensing Technology for the acquisition of 3D information from terrain surface. This paper surveys the state of the art on automated road feature extraction from airborne Light Detection and Ranging (LiDAR) data. It presents a bibliography of nearly 50 references related to this topic. This includes work related to various main approaches used for extracting road from LiDAR data, Feature extraction based on classification and filtering.
A New Approach to Romanize Arabic WordsIJERA Editor
Romanization of Arabic words has been acquired the interest of the researchers due to its importance in many
fields such as security and terrorism fighting, translation, religious purposes, etc.
In this paper, a proposed method was presented to solve the drawbacks of available methods such as lack of
reverse recognition, using of extra letters and punctuation characters, and neglecting the correlation of the letters
in a word.
This method was implemented and tested using a sample of 100 undergraduate Iraqi students and 150 Arabic
words which romanized using five well-known methods in addition to the proposed one. The test showed that
the proposed method dominants the rest method from the recognition and reverse recognition process in
considerable ratio.
High Frequency Soft Switching Of PWM Boost Converter Using Auxiliary Resonant...IJERA Editor
This thesis presents High frequency Soft Switching DC-DC boost Converter. The circuit consists of a general Boost Converter with an additional resonant circuit which has a switch, inductor, capacitor and a diode.In general Boost Converter circuits have snubber circuits where switching losses are dissipated in external passive resistors; which is known as hard switching. As the switching frequency of PWM converters is increased its switching losses and conduction losses also increases. This restricts the use of PWM technique. New Zero Voltage Transition-Zero Current Transition (ZVT-ZCT) PWM converter equipped with the snubber provides the most desirable features of both ZVT and ZCT converters presented previously. Moreover all semiconductors devices operate with soft switching and hence losses are reduced.
Synthesis, Electrical and Optical Properties of Nickel Sulphate Hexa Hydrate ...IJERA Editor
L-Arginine doped Nickel SulphateHexa Hydrate (NSH) single crystalswere grown by slow evaporation
techniquefor different molar concentrations, viz., (0.2 to 1 mole% in steps of 0.2).The grown crystals were
subjected to various studies.XRD data were collected from powder samples of the crystals.ACelectrical
measurementswerecarriedoutatvarioustemperaturesrangingfrom40-750C. Resultsindicate anincrease
oftheelectricalparameterswiththeincreaseoftemperature.The dielectric value suggests that the L-Arginine doped
NSH single crystal is good for microelectronic application. The UV-Vis-NIR spectral studies were performed to
analyze the optical absorption of the grown crystals in the range 200 – 1100nm. Results obtained were
presented.
Design and Analysis of the Effect of a Modified Valve with Helical Guideways ...IJERA Editor
The in-cylinder flow of an Internal Combustion Engine(ICE) has drawn much attention of the automotive
researchers and scientists in the present time. A good swirl promotes fast combustion and improves the
efficiency. Based upon this concept, this paper describes the results of a study conducted to investigate the
effects of a “modified valve with helical guide ways” on the performance of combustion. Small internal
combustion engine is designed to be part of a very efficient vehicle to enter a consumption marathon. The
engine should run at low speeds, in order to have low mechanical losses but combustion should be fast, enabling
good combustion efficiency. Therefore, high turbulence is required prior to combustion within the cylinder,
hence the concept of swirl is introduced and its effect on the combustion within the cylinder has been
ascertained in the present work. Assessment of the effect of swirl on combustion performance within the
cylinder requires excessive experimentation by modifying the design of various components of combustion
chamber. Therefore, in the present work using the concept of CFD the simulation of combustion phenomenon
has been carried out and the output parameters in the form of swirl ratio has been assessed. The modelling of
combustion chamber has been carried out using CATIA software and the same is imported to analysis software
ANSYS- CFX module. Here, the performance of the model is assessed by the swirl ratio. The swirl ratio of the
modified valve (Valve with helical guide ways) is obtained as 1.45 which is much higher than a normal valve
with swirl ratio 0.65 as assessed from the present work.
An Improved Parallel Activity scheduling algorithm for large datasetsIJERA Editor
Parallel processing is capable of executing a large number of tasks on a multiprocessor at the same time period, and it is also one of the emerging concepts. Complex and computational problems can be resolved in an efficient way with the help of parallel processing. The parallel processing system can be divided into two categories depending on the nature of tasks such are homogenous parallel system and the heterogeneous parallel processing system. In the homogeneous environment, the number of processors required for executing different tasks is similar in capacity. In case of heterogeneous environments, tasks are allocated to various processors with different capacity and speed. The main objective of parallel processing is to optimize the execution speed and to shorten the duration of task execution with independent of environment. In this proposed work, an optimized parallel project selection method was implemented to find the optimal resource utilization and project scheduling. The execution speeds of the task increases and the overall average execution time of the task decreases by allocating different tasks to various processors with the task scheduling algorithm.
Dimensional and Constructional Details of Components, Fundamentals of TNM Met...IJERA Editor
For the improvement in thermal design of squirrel cage induction (SCIM) motor, it is essential to know details
of the methods for evaluation of thermal distribution in a SCIM motor. A presentation of various details of
methods of basics of heat transfer that occur in a SCIM motor is done in this report. SCIM motors have wide
applications and thus their construction is completely influenced by the starting characteristics specified by the
operating loads. General constraints of a motor and specification of 30 KW motor are presented in this report as
a case study of constraints. As the next step the Thermal Network Method (TNM) has been explained.
Ultrasonic and Volumetric Investigations of -Butyrolactone with Aliphatic Al...IJERA Editor
Densities () and speeds of sound (u) have been determined for the binary liquid mixtures of -butyrolactone (GBL) with 1-propanol (1-Pro), 2-propanol (2-Pro), 1-butanol (1-But) and 2-butanol (2-But) at 303.15, 308.15, and 313.15 K and entire composition range. From the experimental results, the excess molar volume (VE), and deviation in isentropic compressibility (s) were calculated. The computed properties have been fitted to a Redlich-Kister type polynomial equation to derive binary coefficients and standard deviations.
Fault Modeling of Combinational and Sequential Circuits at Register Transfer ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan
designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper
proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used
communication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)
testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89
S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGA
emulator. The emulation results are compared to other verification methodologies (RTL Simulation,
Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTL
simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software
applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertz
range as accomplished in transaction-based emulation. In addition, the integration of scan
testing and acceleration/emulation platforms allows more complex DFT methods to be developed and
tested on a large scale system, decreasing the time to market for products.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED...VLSICS Design
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...ijcisjournal
In this paper methods for testing both software and hardware faults are implemented in analog and digital
signal circuits are presented. They are based on the wavelet transform (WT). The limit which affected by
faults detect ability, for the reference circuits is set by statistical processing data obtained from a set of
faults free circuits .In wavelet analysis it has two algorithm one is based on a discrimination factor using
Euclidean distances and the other mahalanobis distances, are introduced both methods on wavelet energy
calculation. Simulation result from proposed test methods in the testing known analog and digital signal
circuit benchmark are given. The results shows that effectiveness of existing methods two test metrics
against three other test methods, namely a test method based on rms value of the measured signal, a test
method utilizing the harmonic magnitude component of the measured signal waveform
Enhanced Skewed Load and Broadside Power Reduction in Transition Fault TestingIJERA Editor
This Paper Proposes the T-algorithm technique to optimize the testing Skewed Load and Broadside architecture. And the architecture used to the compare the test pattern results. In this architecture, T-algorithm used to optimize the testing architecture. This architecture compare the test pattern output for the required any type of combinational architecture. The optimization process mainly focused by gate optimization for secure architecture. The proposed system to use the T-algorithm, to optimize the testing clocking level for the required test patterns. This technique to replace the flip flop and the mux arrangement. To reduce the flip flops in Skewed Load architecture. And to develop the accuracy for testing architecture. The proposed system consists of the secure testing architecture and includes the XOR-gate architecture. So the modification process applied by the Broadside and over all Skewed Load architecture. The proposed technique to check the scanning results for the testing process. The testing architecture mainly used to the error attack for the scanning process and the scanning process work with any type of testing architecture. The scanning process to be secure using the T-algorithm for the Skewed Load architecture. And to develop the testing process for the fault identification process. The diagnosis technique to detect error for the scanning process in any type combinational architecture. The T-algorithm used to reduce the circuit complexity for the testing architecture and the testing architecture used to reduce the delay level. And the future process, this technique used to reduce the gate level for the sticky comparator architecture and to modify the clocking function for the testing process. This technique to develop the accuracy level for the testing process compare to the present methodology.
Coding Schemes for Implementation of Fault Tolerant Parrallel FilterIJAAS Team
Digital filters are utilized as a one of flag handling and correspondence frameworks. At times, the unwavering quality of those frameworks is basic, and blame tolerant channel executions are needed. Throughout the years, numerous systems that endeavor the channels' structure and properties to accomplish adaptation to internal failure have been proposed. As innovation scales, it empowers more unpredictable frameworks that join many channels. In those perplexing frameworks, it is regular that a portion of the channels work in parallel. A plan in view of big rectification coding has been as of late proposed to protect parallel channels. In that plan, each channel is deal with as a bit, and excess channels that go about as equality check bits are acquainted with distinguish and rectify blunders. In this short, applying coding systems to secure parallel channels is tended to in a broader manner. This decreases the assurance overhead and makes the quantity of excess channels autonomous of the quantity of parallel channels. The proposed technique is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for a field-programmable gate array implementation.
Design for Testability in Timely Testing of Vlsi CircuitsIJERA Editor
Even though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system.Two main issues related to test and security domain are scan-based attacks and misuse of JTAG interface. Design for testability presents effective and timely testing of VLSI circuits. The project is to test the circuits after design and then reduce the area, power, delay and security of misuse. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self-test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both. BIST is usually performed using pseudorandom pattern generators (PRPGs). Among the advantages of pseudorandom BIST are: (1) the low cost compared to testing from automatic test equipment (ATE). (2) The speed of the test, which is much faster than when it is applied from ATE. (3) The applicability of the test while the circuit is in the field, and (4) the potential for high quality of test.
Online and Offline Testing Of C-Bist Using Sramiosrjce
Built-in self test techniques constitute a class of schemes that provide the capability of performing atspeed
testing with high fault coverage hence; they constitute an attractive solution to the problem of testing
VLSI devices. Concurrent BIST schemes perform testing during the circuit normal operation without imposing a
need to set the circuit offline to perform the test; therefore they can circumvent problems appearing in offline
BIST techniques. In this brief, a novel input vector monitoring concurrent BIST architecture has been presented,
based on the use of a SRAM-cell like register for storing the information of whether an input vector has
appeared or not during normal operation. The evaluation criteria for this class of schemes are the hardware
overhead and the CTL, i.e., the time required for the test to complete, while the circuit operates normally. The
simulation results shown to be more efficient than previously proposed Concurrent BIST techniques in terms of
hardware overhead and CTL.
Co-Simulation Interfacing Capabilities in Device-Level Power Electronic Circu...IJPEDS-IAES
Power electronic circuit simulation today has become increasingly more demanding in both
the speed and accuracy. Whilst almost every simulator has its own advantages and disadvantages,
co-simulations are becoming more prevalent. This paper provides an overview of
the co-simulation capabilities of device-level circuit simulators. More specifically, a listing
of device-level simulators with their salient features are compared and contrasted. The
co-simulation interfaces between several simulation tools are discussed. A case study is
presented to demonstrate the co-simulation between a device-level simulator (PSIM) interfacing
a system-level simulator (Simulink), and a finite element simulation tool (FLUX).
Results demonstrate the necessity and convenience as well as the drawbacks of such a comprehensive
simulation.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
Search and Society: Reimagining Information Access for Radical Futures
C044061518
1. Ms. Nainaa. Udgedr et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.15-18
www.ijera.com 15 | P a g e
Detection of Stuck at Fault Indigital Circuits at Register Transfer
Logic (RTL)
Ms. Nainaa. Udgedr, S. A. Ladhake, Prof. P. D. Gawande
Assistant Professor Principle Faculty of Electr. &Telecom SipnaCOET, Amravati (M.H.)
Assosicate Professor Sipna COET, Amravati (M.H.)
Faculty of Electr. & Telecom. Sipna COET Amravati (M.H.)
Abstract
Due to the increasing complexity of modern circuit design, verification has become the major bottleneck of the
entire design process. Most efforts are to verify the correctness of the initial Register-Transfer Level (RTL)
descriptions written in Hardware Description Language (HDL).Major drawback of high level design
methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault
models - compared to sophisticated models available for low level description levels such as logic gate level.
Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis
is typically performed only after final logic synthesis.So in this paper, we detect the stuck-at fault using the
concept of textio.
Keywords-stuck-atfaults; fault coverage ;testpoints; validation sets
I. Introduction
Sinceintegrated circuit designs are
accordinglybecoming more and more complex. As a
result of this, VLSI testing has becomeexpensive in
terms of cost. Existinggatelevelfault simulation
techniques exhibitpoor performance standards
whenapplied to such designs and are unsuitable for
earlytestabilityanalysis or fault simulations. Also test
generation and fault simulation efforts in the post
synthesis phase do not contribute to the improvement
in the design. Therefore a design methodology for
fault simulation athigherlevels of abstraction
ishighlydesired.
Test patterns for large VLSI systems are
oftendeterminedfrom the knowledge of the circuit
function. A fault simulator isthenused to find the
effectiveness of the test patterns in detectinggate-
level “stuck-at” faults. Existinggate-levelfault
simulation techniques sufferprohibitivelyexpensive
performance penalties whenapplied to the modern
VLSI systems of larger sizes. Also, findings of such
test generation and fault simulation efforts in the post
logic-synthesis phase are toolate in the design cycle
to beuseful for design-for-test (DFT)
relatedimprovements in the architecture. Therefore,
an effective register-transferlevel (RTL) fault model
ishighlydesirable.
Basicallyfaultmodellingconsists of three
fundamentals terms i.e. defect, fault & error. Defect -
A defect is the unintended difference between the
implemented hardware and its intended design
Defects occur either during manufacture or during the
use of devices the use of devices Fault - A
representation of a defectat the abstracted function
level Error - A wrong output signal produced by a
defective system. An error is caused by a Faultor a
design error The problems of ideal tests are : Ideal
tests detect all defects produced in the manufacturing
process manufacturing process. Also,Ideal tests pass
all functionally good devices. „Very large numbers
and varieties of possible defectsneed to
betested.Difficult to generate tests for some real
defects. †
The problems of Real tests are ; Real tests
„Based on analyzablefaultmodels, whichmay not map
on real defects,Incompletecoverage of modeledfaults
due to high complexity,Some good chips are rejected.
The fraction (or percentage) of such chips is called
the yield loss „Some bad chips pass tests. The
fraction (or percentage) of bad chips among all
passing chips iscalled the defectlevel.
So in thispaperwe are emphasising on the detection
of stuck-atfaults in RTL circuits using the feature of
vhdllangauage i.e. textio, withoutcompromising in
faultcoverage.
II. Related work
Various methods are implemented to detect
the stuck-at fault in digital circuits.
A. Adding Buffer to each ports of RTL Circuits.
The very first method is adding buffer to
each ports of RTL circuits to create a new faulty
circuit[7].
RESEARCH ARTICLE OPEN ACCESS
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1. Firstlytestbench is developed and the simulation
is first run on a good circuit and then on each of
the faulty circuits using any simulator.
2. The outputs obtained in each case of the faulty
circuits are compared with the output of the good
circuit to determine which faults are detected.
That is the new faulty circuit and the fault free
circuit is simulated and the outputs so obtained
are compared. The fault list is tabulated.
3. The ratio of the numbers of RTL faults detected
to the total number of RTL faults gives the RTL
fault coverage.
B. Using Validation Test Sets.
Next method is that in which validation test
sets are used to generate test sequences that detect a
majority of stuck-at faults in the datapath[1].
1. The scheme first derives the controller behaviors
from validation test sequences and reuses them
for simplifying justification/propagation analysis
corresponding to precomputedtest
vectors/responses of datapath RTL modules.
2. A heuristic is used to identify controller
behaviors that are compatible with a given set of
precomputed test vectors/responses. It requires
only a single pass through the CDFG
corresponding to a validation test sequence and
is accu- rate, resulting in a small number of test
generation runs.
3. Test generation is performed at the RTL and the
controller behavior is prespecified,which results
in very small ltest generationtimes.First step is
identification of compatible controller behaviors
consisting of Augmented Fault Simulation to
Derive Activation-Detection Time Frame Pair
and Analysis of Requirements to Identify
Compatible Faults. Next step is SAT-based RTL
ATPG is used to obtain a test sequence that
reuses the controller behavior to justify and
propagate the precomputed test vector and
response to primary inputs and outputs,
respectively.
SAT- based RTL ATPG uses an ILA model
of the circuit under test.The circuit is unrolled for a
predetermined number of cycles determined by the
number of vectors in the validation test sequence
from which the controller behavior is extracted. Test
generation is performed on the entire circuit
description comprising the controller and datapath by
first identifying the paths from the inputs of the
module under test to primary inputs and from the
output of the module under test to primary outputs in
the ILA model. These paths are then translated into
Boolean clauses by translating the functionality of the
individual modules in these paths. Once the Boolean
clauses that capture the RTL test generation problem
and the controller behavior are generated, a SAT
solver is invoked to resolve these clauses. If the
solver returns with a satisfiable solution, then a test
sequence can be extracted from the Boolean variable
assignments corresponding to the primary inputs.
This sequence is guaranteed to deliver the
precomputed test vector to the inputs of the
corresponding RTL module and propagate the fault
effect from the output of the module to a primary
output. If the Boolean clauses are not satisfiable, then
test generation fails, indicating that the targeted
precomputed test vector/response cannot be
justified/propagated by reusing the controller
behavior that was found to be compatible by using
the heuristic.
C. Implementation of Automatic Test Paterrn
Generation.
Next method for detection of stuck-at fault
consisting of an algorithm for generating test patterns
automatically from functional register-transfer level
(RTL) circuits that target detection of stuck-at faults
in the circuit at the logic level.
1. In order to do this, a data structure named
assignment decision diagram are used[5]. The
algorithm is very versatile and can tackle almost
any type of single- clock design, although
performance varies according to the design style.
The first step is to convert each process and
concurrent RTL statements in each leaf
component of the circuit into ADDs.
2. After that, each ADD is selected and its I
nternals targeted for testing. First the arithmetic
operations are targeted, then logic arrays, then
untagged registers, latches, and memories, then
untagged ADNs, and finally random logic blocks
and black boxes.
During testing of each RTL element, a nine-
valued symbolic RTL justification and propagation is
done to trace outpaths from the PIs to the element
inputs and element outputs to POs to obtain a
symbolic test environment for the module. The
search is a branch and bound type of search with
backtracking and has a backtrack limit and search
time limit that may be adjusted. It requires hierarchy
traversal in case of a hierarchical design.
III. RTL Fault Model, Fault-Injection
and Fault Simulation
Hardware description languages (HDLs) are
used to model VLSI circuits. HDL constructs are
classified into three types: structural, register-transfer
level (RTL) and behavioral. RTL constructs represent
a subset of HDL constructs with the corresponding
design guidelines meant to ensure the consistent
synthesis of gate-level netlists by logic synthesis
tools. With event scheduling and resource allocation
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information built-in, an RTL model represents the
micro-architecture of a circuit.
Properties of the RTL fault model:
• Language operators (which map onto Boolean
components in the gate-level netlist) are assumed
to be fault-free.
• Variables (which map onto signal lines in the
gate-level netlist) contain faults:
• a stuck-at-zero (s-a-0) fault when the logic level
is fixed at value 0
• a stuck-at-one (s-a-1) fault when the logilevel is
fixed at value 1
• The proposed RTL fault model follows the
single fault assumption and therefore only one
fault is applied at a time when a test set is
evaluated.
• The RTL fault-list of a module contains input as
well as fan-out faults. RTL variables that are
used more than once in executable statements or
the instantiations of lower level modules of the
design-hierarchy are considered to have fan-out.
Input faults of a module at the RT level have
one-to-one equivalence to input faults of the
module at the gate-level. The fan-out faults of
variables inside a module at the RT level
represent a subset of the fan-out faults of a
possible gate-level implementation.
3.1 Fault Model And Fault Injection
The definition of the RTL fault model and
the fault- injection algorithm encompasses modeling
of faults for synthetic, Boolean and logical operators,
sequential elements and fan-out/stem variables, as
well as the collapsing of RTL faults. RTL faults are
depicted with crosses (“x”) in Figure 1. When RTL
constructs contain synthetic operators, faults are
injected only on the input variables of such operators.
During logic synthesis, the synthetic operators are
replaced by combinational circuits implementing the
respective functions, e.g., adder, subtracter,
comparator, etc. The internal details of such functions
represented by synthetic operators are not available at
the RT level and therefore only the subset of the
checkpoint faults of the gate-level representation of
these operators, namely, the primary input faults are
modeled. When a function is represented using RTL
constructs that contain Boolean operators, faults are
injected on variables that form Boolean equations.
Some internal signals of these constructs are
available at the RT level and therefore RTL faults are
placed at primary inputs and internal nodes including
signal stems and fan-outs. The post-synthesis gate-
level representation of such a construct may be
structurally different from the RTL Boolean
representation. However, some RTL faults have
equivalent faults in a collapsed gate-level fault-list of
any post-synthesis design.
3.2 Fault Simulation
The operation of DUT is analysised on the
basis of inputs and outputs. The variation in the
output indicates the presence of fault in the circuit.
The steps of testing are demonstrated in the
below flow diagram:
The faulty circuit is simulated first using software
modelsim.After this,detection of fault is done by
analysis the individual paths of transmission of
output inside the circuit, they are known as test
points.
In our circuit four testpoints are there.Finally, the
results of good cicuit i.e. expected results and the
results of faulty circuit i.e. actual results , both are
compared by simulating the circuit in which expected
results are taken as inputs of the circuit.
The values of signals sf_test1, sf_test2, sf_test3,
sf_test4 indicateds the presence of stuck-at faults in
the circuit. The signals values ie. sf_test1, sf_test2,
sf_test3, sf_test4, for faulty circuit has the values of
testpoints, which indicates the fault :
IV. Results
A versatileRTL-ATPG algorithm is
presented that can generate test vectors for almostany
Textio
(ATPG)
.vhd
code
Design under test
(DUT)
Expectedresult
(.txt file)Actual
result(.txtfile
)
Comparision of two result(.txt file)
4. Ms. Nainaa. Udgedr et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.15-18
www.ijera.com 18 | P a g e
type of single-clock functional RTL design. The
algorithmuses a data structure called ADD that helps
it to tackle controland data flow in an unified fashion
and a nine-valued algebrathat helps it to do
justification and propagation at the RTL.
Here, we are using the concept of textio for
the detection of stuck-at fault in the circuit.” Textio”
is one of the easier way of fault modelling and fault
coverage is calculated without any consicounses.
Below given output file which is generated
after comparison of actual results and expected
results indicates the presence of stuck-at fault.
In the above table of output, A,B,C,D&
RESET are taken as inputs.Test1,Test2,Test3,Test4
are taken as the test points of the circuit. The values
of outputs i.e. SF_Test1, SF_Test2, SF_Test3,
SF_Test4 indicates the presences of stuck-at fault in
the circuit.If there is the fault for any one of the
inputs then, SF_Test1,SF_Test2,SF_Test3,SF_Test4
takes the values of Test1,Test2,Test3,Test4 otherwise
it has the null ’z’ value.
Since for the set of 15 inputs, we get the
proper outputs and fault is detected for any particular
combination of inputs,therefore fault coverage for
given circuit is 100%.
V. Conclusion
The very first method to fault modelling
methodology has used a validation test sets to
generate test sequence that have goos stuck-at fault
coverage for RTL circuits.This method results in very
small test generation times.
After this method,RTL-ATPG algorithm
was presented to generate test vectors for single clock
functional RTL design.thealgoritm uses a data
structure called ADD.
But here in this paper concept of textio is
used to detect the stuck-at fault in RTL circuit.Also,
this method results in easier estimation of fault
coverage.This leads to the better efficiency of this
method than previously used methods of fault
coverage in RTL circuits.
References
[1] R. C. Ho and M. A. Horowitz, “Validation
coverageanalysis for complex digital
designs,” in Proc. Int. Conf. Comput.-Aided
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[2] I. Ghosh, A. Raghunathan, and N. K. Jha,
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[3] D. J. Moundanos, J. A. Abraham, and Y. V.
Hoskote, “Abstraction techniques for
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[4] IndradeepGhosh and Srivaths Ravi, “On
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[5] IndradeepGhosh and MasahiroFujita,
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UsingAssignmentDecisionDiagrams” ieee
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[6] L. Lingappan and N. K. Jha,
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circuits,” in Proc. VLSI Test Symp., May
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[7] SumaM.S. ,K.S.Gurumurthy “FaultCoverage
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[8] SarveshPrabhu, Michael S. Hsiao,
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