This document compares four different multiplier designs from the perspectives of power consumption, delay, and area usage. It finds that a carry save adder (CSA) multiplier achieves the lowest power consumption of 0.198mW and delay of 6psec, making it suitable for low-power applications. A modified Booth encoder (MBE) multiplier requires the smallest area of 4030μm2. In general, the four multiplier designs show tradeoffs between power, speed, and area depending on the specific implementation and modification techniques used.

1. 1
A Comparative Study of Different Multiplier Designs
Aisha Abdallah
Department of Electrical and Computer Engineering, University of Sharjah
ABSTRACT
In this paper, a comparative study of different multiplier
designs has been presented. It shows various
multiplication techniques and discusses the modification
that is applied to the multiplication methods. An
overview about four selected multiplier designs is
provided. They are compared from VLSI design
performance; speed, power, and area, and the best
performance is highlighted. The lowest power
consumption is shown in selected CSA multiplier, also
with the lowest delay with the values 0.198mW and
6psec, respectively. Hence, it is used for low-power
applications. In other hand, the smallest area is achieved
by selected MBE with 4030 μm2
.
1. INTRODUCTION
Arithmetic logic operations, such as multiplication and
addition, are one of the dominant concern in digital
signal processing (DSP), multimedia, 3D graphics,
microprocessor, application-specific integrated circuit
(ASIC),…etc [1-3]. In DSP field, the binary
multiplication is the most important operation in the
hardware. Thus, multiplication method must not
consume much execution time of the hardware. There
are many DSP algorithms that depend on multiplication,
such as digital filters, Discrete Cosine Transform (DCT),
and Fast Fourier Transform (FFT). Searching for ace
multiplier lands on three features; high-speed and low-
power. These features have tradeoff among them, but a
compromise design can be achieved. There are three
basic steps in multiplication which are partial products
generation, partial products additions (reduction), and
final addition [4]. There are many different and modified
architecture designs of multiplier. This paper will
present a comparison among different multipliers from
three important considerations of VLSI design which are
power, area, and delay. This paper is organized as
follows. Section 2 gives basic background about several
multiplication techniques. Overview about four different
designed multipliers is provided in Section 3. Section 4
summarizes the comparison of the discussed multipliers.
The conclusion is drawn in Section 5.
2. MULTIPLICATION TECHNIQUES
There are various techniques to do binary multiplication.
Also, there exist many modifications done to these
techniques. Binary array multiplier, shown in Figure 1,
consists of AND gates, half adders, and full adders. For
N-bit×N-bit unsigned numbers, it needs N2
AND gates,
N half adders, and N(N-2) full adders [5]. It uses ripple
carry adder in which the carry-out of each adder is
rippled to be the carry-in for the next adder. To multiply
both unsigned and signed numbers, radix-4 Modified
Booth Encoder (MBE) is one of the methods to do that.
It groups three consecutive bits of the multiplier and
matches each group to partial products table, given by
Table 1 [1]. Thus, it reduces number of partial products
and so the numbers of adders. Carry Save Adder (CSA)
multiplier consists of half adders and full adders. It is
similar to ripple carry adder but the carry-out vector is
saved to be combined with the output of sum later. The
half adder can be designed as depicted in Figure 2,
which is known as multiplexing method. It is built using
CPL (Complementary Pass-transistor Logic) that reduces
number of transistors and consists only of NMOS. Thus,
it provides low capacitance and yields to high speed (low
delay) and low power. Also, half adder can be
implemented using MCIT (Multiplexing Control Input
Technique). It has less number of transistors comparing
with CMOS but it is more than CPL [2]. Another type of
multiplier is Braun multiplier, which consists of array of
N2
AND gates and array of N(N-1) full adder. It is used
only for unsigned numbers. The generated partial
products are inputs to cascaded CSA. A modified version
of Braun multiplier is called Baugh-Wooley multiplier,
in which it is used for unsigned and signed numbers
represented in 2’complement [2].
3. OVERVIEW ABOUT FOUR DIFFERENT
DESIGNED MULTIPLIERS
Four types of multipliers which are proposed in [1], [2],
[3], and [4] will be discussed and compared from
different point of view of VLSI design parameters; area,
delay, and power, and used technology. Each design
shows a modification done on the conventional
multiplier to enhance its performances.

2. 2
Figure 1. Binary array multiplier [5].
Figure 2. Half adder using CPL [2].
3.1. A logarithmic time method of 2’s complement
representation
A fast MBE is achieved by using a new 2’s complement
representation, given in [1]. It starts by finding
conversion signal which groups, starting from LSB, two
consecutive bit each level; 2, 4, 8,…,2n. After each
group, if the rightmost digit is ‘1’ in each group then it
masks the left-bits to ‘1’, otherwise they are unchanged.
Then 2’s complement is obtained by adding the final
conversion signal to the input. This leads to have a well-
organized diamond-shape of partial product tree. The
last row in multiplication scheme is 2’s complement with
partial product selection. Figure 3 summarizes the new
technique to find 2’s complement. Using 3-5 coder
selects the possible input value using Table 1. The 2’s
complement is generated concurrently with MBE and 3-
5 coder. This technique reduces partial products rows
and minimizes the total multiplication operating time
[1].
3.2. Multipliers using a Shannon-based adder
The Shannon-based adder relies on Shannon Theorem,
which basically uses the multiplexers to represent the
function as a sum of two sub-functions in term of one or
more input variables and its negation. In [2], this
proposed type of adder is applied to Braun, Baugh-
Wooley, and CSA multipliers. Figure 4 shows the
Shannon-based adder used in [2]. Using X-OR and X-
NOR gates constructed by CPL offers less number of
transistors in the sum circuit but the overall number of
transistors is large [2]. For the same multiplier type, the
designed adder grabs the best performance among other
adders; i.e. MCIT, CPL-12T, and mixed Shannon except
in the area and number of transistors where mixed
Shannon is preferable. The lowest power dissipation and
delay is obtained by CSA because it uses half-adder
circuit. The significant advantages of the proposed
multipliers show in low power dissipation and high
speed comparing to other 8x8 multipliers.
3.3. Pair-wise algorithm
The introduced pair-wise algorithm in [3] reduces the
8x8 bits complex mathematic multiplication in two steps
without using encoder; generation of partial products and
partial products addition. Each number in multiplication
is separated into even and odd numbers, each one n-bit,
so that the addition of them gives the original number.
Then, multiplication of the two numbers, represented in
even and odd, is done pairwise. The results are Pee, Peo,
Poe, and Poo. Each result has even partial products is
divided into a sum of even and odd and added using 3:2
adder to make reduction in number of partial products.
The result at this stage is A and B. x7y1, x2y7, x2y8, and
x7y2, are sparse bits are to M and N which are originally
13-bit and 15-bit zeros, respectively. Poo is grouped with
M and N to get another two numbers. The final result is
obtained as the output of CLA. The addition step is
depicted in Figure 5. The multiplier consists of full
adder, half adder, and CLA. The proposed full adder
circuit is X-OR constructed using CPL-10T. This design
gives low power dissipation and high speed as the
comparison done in [3].
3.4. Modified binary array multiplier
In [5], the traditional binary array multiplier is altered by
replacing the last full adder with the CLA adder. It
provides a fast computation for the carry-in of each
previous stage. The sum and carry for a four bit adder is
expressed as in (1-2), respectively. Equation (3-4)
defines two terms; the generation carry and propagation
carry, respectively. Gi occurs when carry-out is generated
Groups of multiplier
digits Partial products
000 0
001 1*multiplicand
010 1*multiplicand
011 2*multiplicand
100 -2*multiplicand
101 -1*multiplicand
110 -1*multiplicand
111 0
Table 1. Radix-4 Modified Booth Encoder [1]

3. 3
Figure 3. A new technique of finding 2’complement [1].
Figure 4. The proposed Shannon-based adder cell [2]
Figure 5. The partial product addition [3]
internally in the full adder. Pi is produced when carry-in
appears. For 4-bit adder, this can be shown as (5-8).
The speed in the conventional array multiplier depends
on propagation time of carries in all stages, while, using
CLA adder, it eliminates the propagation delay of the
carries realized in the addition. The carry-out bits are
found ahead based on inputs and initial carry-in without
waiting for the full adder output to be found in each
stage. Thus, a faster partial product is generated and a
speeder adder is obtained.
Sum = Xi ⊕Yi ⊕ Ci (1)
Cout,i+1 = Gi + Pi · Ci (2)
Gi = Xi·Yi (3)
Pi = Xi ⊕ Yi. (4)
Cout,1 = G0 + P0 · C0 (5)
Cout,2 = G1 + P1 · Cout,1 (6)
Cout,3 = G2 + P2 · Cout,2 (7)
Cout,4 = G3 + P3 · Cout,3. (8)
4. COMPARISON OF THE FOUR TYPES OF
MULTIPLIER DESIGNS
Different techniques and modifications have been
discussed to preform multiplication. Each one provides
advantages and tradeoffs among several parameter
performances. Power, area, and delay are the three
essential performances in VLSI design. The comparison
among the discussed multipliers is summarized in Table
1 and Table 2. All references simulate and test for 8-
bitx8-bit multiplier except [4]. The lowest delay and
lowest power dissipation is resulted from [2] using CSA
multiplier, in which delay is 6psec and power dissipation
is 0.198mW. Thus, this multiplier is preferable for high
speed and low power devices. Reference [1] is the good
path to implement multiplier in an area consideration
environment, where the occupied area is 4030μm2
.
1. CONCLUSION
In this paper, different types of multipliers are compared.
Each one shows a new method or a modification on
traditional multipliers. They are implemented using
different technologies. The lowest power consumption is
CSA multiplier [2], also with the lowest delay with the
values 0.198mW and 6psec, respectively. Hence, it is
used for low-power applications. Obviously, the smallest
area is achieved by MBE [1] with 4030 μm2
.
Table 1. Comparison of discussed multipliers showing
their types, modification, and process.
Reference
Type of
multiplier
Type of modification Process
[1]
MBE
(8-bitx8-bit)
Fast multiplication
in 2’s complement
representation
Artisan
TSMC
0.13μm
[2]
Baugh-
Wooley
(8-bitx8-bit) Shannon-based
adder
90nm
CMOS
Braun
(8-bitx8-bit)
CSA
(8-bitx8-bit)
[3]
Pair-wise
algorithm
(8-bitx8-bit)
10-transistor full
adder cell
6
Metal
0.18μm
Digital
CMOS
[4]
Array
(4-bitx4-bit)
CLA adder -
+

4. 4
Table 2. Comparison of discussed multipliers from VLSI
design parameter performances.
Type of
multiplier
Power
consumption
(mW)
Delay (ps) Area (μm2
)
MBE
(8-bitx8-bit)
6.3876 3030 4030
Baugh-
Wooley
(8-bitx8-bit)
0.816 37 6230
Braun
(8-bitx8-bit)
0.307 16 21672
CSA
(8-bitx8-bit)
0.198 6 32316
Pair-wise
algorithm
(8-bitx8-bit)
0.64 1256 14267
Array
(4-bitx4-bit)
68.49 16620 -
REFERENCES
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2009.
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2013.
[5] S. R. Vaidya, and D. R. Dandekar, “Performance
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