SlideShare a Scribd company logo
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
Flexible DSP Accelerator Architecture Exploiting
Carry-Save Arithmetic
Abstract:
Hardware acceleration has been proved an extremelypromising implementation strategy for the
digital signal processing (DSP)domain. Rather than adopting a monolithic application-specific
integratedcircuit design approach, in this brief, we present a novel acceleratorarchitecture
comprising flexible computational units that support theexecution of a large set of operation
templates found in DSP kernels.We differentiate from previous works on flexible accelerators by
enablingcomputations to be aggressively performed with carry-save (CS) formatteddata.
Advanced arithmetic design concepts, i.e., recoding techniques,are utilized enabling CS
optimizations to be performed in a larger scopethan in previous approaches.The proposed
architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
Perform the other temple of the FCU.
Existing system:
Modern embedded systems target high-end application domainsrequiring efficient
implementations of computationally intensivedigital signal processing (DSP) functions. The
incorporation ofheterogeneity through specialized hardware accelerators improvesperformance
and reduces energy consumption. Althoughapplication-specific integrated circuits (ASICs) form
the ideal accelerationsolution in terms of performance and power, their inflexibilityleads to
increased silicon complexity, as multiple instantiated ASICsare needed to accelerate various
kernels. Many researchers haveproposed the use of domain-specific coarse-grained
reconfigurable accelerators in order to increase ASICs’ flexibility withoutsignificantly
compromising their performance.
The aforementioned reconfigurable architectures excludearithmetic optimizations during the
architectural synthesis andconsider them only at the internal circuit structure of
primitivecomponents, e.g., adders, during the logic synthesis. However,research activities have
shown that the arithmeticoptimizations at higher abstraction levels than the structuralcircuit one
significantly impact on the datapath performance. In, timing-driven optimizations based on
carry-save (CS) arithmetic were performed at the post-Register Transfer Level (RTL) design
stage. In, common subexpression eliminationin CS computations is used to optimize linear DSP
circuits. Verma et al. developed transformation techniques on theapplication’s DFG to maximize
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
the use of CS arithmetic prior theactual datapath synthesis. The aforementioned CS
optimizationapproaches target inflexible datapath, i.e., ASIC, implementations. Recently, Xydis
et al. proposed a flexible architecturecombining the ILP and pipelining techniques with the CS-
awareoperation chaining. However, the entire aforementioned solutions featurean inherent
limitation, i.e., CS optimization is bounded to mergingonly additions/subtractions. A CS to
binary conversion is insertedbefore each operation that differs from addition/subtraction,
e.g.,multiplication, thus, allocating multiple CS to binary conversionsthat heavily degrades
performance due to time-consuming carrypropagations.
Disadvantages:
 high the area
 high the power
Proposed system:
The proposed flexible accelerator architecture is shown in Fig. 1.Each FCU operates directly on
CS operands and produces data inthe same form1 for direct reuse of intermediate results. Each
FCU operates on 16-bit operands. Such a bit-length is adequate for themost DSP datapaths, but
the architectural concept of the FCUcan be straightforwardly adapted for smaller or larger bit-
lengths.The number of FCUs is determined at design time based on theILP and area constraints
imposed by the designer. The CStoBinmodule is a ripple-carry adder and converts the CS form
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
to the two’scomplement one. The register bank consists of scratch registers andis used for storing
intermediate results and sharing operands amongthe FCUs. Different DSP kernels (i.e., different
register allocationand data communication patterns per kernel) can be mapped ontothe proposed
architecture using post-RTL datapath interconnectionsharing techniques. The control unit drives
the overallarchitecture (i.e., communication between the data port and theregister bank,
configuration words of the FCUs and selection signalsfor the multiplexers) in each clock cycle.
Structure of the Proposed Flexible Computational Unit:
The structure of the FCU (Fig. 2) has been designed to enablehigh-performance flexible
operation chaining based on a library of operation templates. Each FCU can be configured to
anyof the T1–T5 operation templates shown in Fig. 3.
Figure 1 : Abstract form of the flexible datapath.
The proposedFCU enables intra-template operation chaining by fusing the additionsperformed
before/after the multiplication and performs any partialoperation template of the following
complex operations:
W∗ = A × (X∗ + Y∗) + K∗ (1)
W∗ = A × K∗ + (X∗ + Y ∗). (2)
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
Figure 2 : FCU.
The following relation holds for all CS data: X∗ = {XC, XS} =XC + XS. The operand A is a two’s
complement number. Thealternative execution paths in each FCU are specified after
properlysetting the control signals of the multiplexers MUX1 and MUX2 (Fig. 2). The
multiplexer MUX0 outputs Y ∗ when CL0 = 0(i.e., X∗ + Y ∗ is carried out) or Y ∗ when X∗ − Y
∗ is requiredand CL0 = 1. The two’s complement 4:2 CS adder produces theN∗ = X∗ +Y ∗ when
the input carry equals 0 or the N∗ = X∗ −Y ∗when the input carry equals 1. The MUX1
determines if N∗ (1) orK∗ (2) is multiplied with A. TheMUX2 specifies if K∗ (1) or N∗ (2)is
added with the multiplication product. The multiplexer MUX3accepts the output of MUX2 and
its 1’s complement and outputsthe former one when an addition with the multiplication product
isrequired (i.e., CL3 = 0) or the later one when a subtraction is carriedout (i.e., CL3 = 1). The 1-
bit ace for the subtraction is added in theCS adder tree.
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
Figure 3 : FCU template library.
The multiplier comprises a CS-to-MB module, which adopts arecently proposed techniqueto
recode the 17-bit P∗ in itsrespective MB digits with minimal carry propagation. The
multiplier’sproduct consists of 17 bits. The multiplier includes a compensationmethod for
reducing the error imposed at the product’s accuracy bythe truncation technique. However, since
all the FCU inputsconsist of 16 bits and provided that there are no overflows, the16 most
significant bits of the 17-bit W∗ (i.e., the output of theCarry-Save Adder (CSA) tree, and thus, of
the FCU) are inserted inthe appropriate FCU when requested.
Advantages:
 high degrees of computational density
 reduce the area
 reduce the power
Software implementation:
 Modelsim
 Xilinx ISE

More Related Content

What's hot

A comparative study of different multiplier designs
A comparative study of different multiplier designsA comparative study of different multiplier designs
A comparative study of different multiplier designs
Hoopeer Hoopeer
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
IJSRD
 
High Performance MAC Unit for FFT Implementation
High Performance MAC Unit for FFT Implementation High Performance MAC Unit for FFT Implementation
High Performance MAC Unit for FFT Implementation
IJMER
 
Aw4102359364
Aw4102359364Aw4102359364
Aw4102359364
IJERA Editor
 
Implementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select AdderImplementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select Adder
inventionjournals
 
Modified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystemsModified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystems
IAEME Publication
 
J0166875
J0166875J0166875
J0166875
IOSR Journals
 
Low power & area efficient carry select adder
Low power & area efficient carry select adderLow power & area efficient carry select adder
Low power & area efficient carry select adder
Sai Vara Prasad P
 
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
Performance Analysis of OFDM Transceiver with Folded FFT and LMS FilterPerformance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
idescitation
 
B1030610
B1030610B1030610
B1030610
IJERD Editor
 
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable CoefficientsTranspose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
IRJET Journal
 
A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...
jpstudcorner
 
Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersImplementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select Adders
Kumar Goud
 
Array multiplier
Array multiplierArray multiplier
Array multiplier
Mathew George
 
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD Editor
 
Design and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select AdderDesign and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select Adder
ijsrd.com
 
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesFPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
Editor IJMTER
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adder
KUMARASWAMY JINNE
 
Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...
jpstudcorner
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
IJERD Editor
 

What's hot (20)

A comparative study of different multiplier designs
A comparative study of different multiplier designsA comparative study of different multiplier designs
A comparative study of different multiplier designs
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
 
High Performance MAC Unit for FFT Implementation
High Performance MAC Unit for FFT Implementation High Performance MAC Unit for FFT Implementation
High Performance MAC Unit for FFT Implementation
 
Aw4102359364
Aw4102359364Aw4102359364
Aw4102359364
 
Implementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select AdderImplementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select Adder
 
Modified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystemsModified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystems
 
J0166875
J0166875J0166875
J0166875
 
Low power & area efficient carry select adder
Low power & area efficient carry select adderLow power & area efficient carry select adder
Low power & area efficient carry select adder
 
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
Performance Analysis of OFDM Transceiver with Folded FFT and LMS FilterPerformance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filter
 
B1030610
B1030610B1030610
B1030610
 
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable CoefficientsTranspose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
 
A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...
 
Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersImplementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select Adders
 
Array multiplier
Array multiplierArray multiplier
Array multiplier
 
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
 
Design and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select AdderDesign and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select Adder
 
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesFPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adder
 
Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
 

Similar to Flexible dsp accelerator architecture exploiting carry save arithmetic

FPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT AlgorithmFPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT Algorithm
cscpconf
 
FPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT AlgorithmFPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT Algorithm
cscpconf
 
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 CompressorA Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
IJERD Editor
 
M367578
M367578M367578
M367578
IJERA Editor
 
Design and Implementation of an Embedded System for Software Defined Radio
Design and Implementation of an Embedded System for Software Defined RadioDesign and Implementation of an Embedded System for Software Defined Radio
Design and Implementation of an Embedded System for Software Defined Radio
IJECEIAES
 
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformationIaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd Iaetsd
 
D0341015020
D0341015020D0341015020
D0341015020
inventionjournals
 
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead TreeIRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
IRJET Journal
 
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORMDESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
sipij
 
My paper
My paperMy paper
Field programmable gate array implementation of multiwavelet transform based...
Field programmable gate array implementation of multiwavelet  transform based...Field programmable gate array implementation of multiwavelet  transform based...
Field programmable gate array implementation of multiwavelet transform based...
IJECEIAES
 
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
IOSRJECE
 
Implementation of High Speed OFDM Transceiver using FPGA
Implementation of High Speed OFDM Transceiver using FPGAImplementation of High Speed OFDM Transceiver using FPGA
Implementation of High Speed OFDM Transceiver using FPGA
MangaiK4
 
Analysis of Women Harassment inVillages Using CETD Matrix Modal
Analysis of Women Harassment inVillages Using CETD Matrix ModalAnalysis of Women Harassment inVillages Using CETD Matrix Modal
Analysis of Women Harassment inVillages Using CETD Matrix Modal
MangaiK4
 
Copy of colloquium 3 latest
Copy of  colloquium 3 latestCopy of  colloquium 3 latest
Copy of colloquium 3 latest
shaik fairooz
 
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEA NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
cscpconf
 
Paper id 37201520
Paper id 37201520Paper id 37201520
Paper id 37201520
IJRAT
 
Iaetsd multioperand redundant adders on fpg as
Iaetsd multioperand redundant adders on fpg asIaetsd multioperand redundant adders on fpg as
Iaetsd multioperand redundant adders on fpg as
Iaetsd Iaetsd
 
An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filterAn fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter
eSAT Publishing House
 
An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter
eSAT Journals
 

Similar to Flexible dsp accelerator architecture exploiting carry save arithmetic (20)

FPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT AlgorithmFPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT Algorithm
 
FPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT AlgorithmFPGA based Efficient Interpolator design using DALUT Algorithm
FPGA based Efficient Interpolator design using DALUT Algorithm
 
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 CompressorA Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor
 
M367578
M367578M367578
M367578
 
Design and Implementation of an Embedded System for Software Defined Radio
Design and Implementation of an Embedded System for Software Defined RadioDesign and Implementation of an Embedded System for Software Defined Radio
Design and Implementation of an Embedded System for Software Defined Radio
 
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformationIaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformation
 
D0341015020
D0341015020D0341015020
D0341015020
 
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead TreeIRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
IRJET- Flexible DSP Accelerator Architecture using Carry Lookahead Tree
 
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORMDESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORM
 
My paper
My paperMy paper
My paper
 
Field programmable gate array implementation of multiwavelet transform based...
Field programmable gate array implementation of multiwavelet  transform based...Field programmable gate array implementation of multiwavelet  transform based...
Field programmable gate array implementation of multiwavelet transform based...
 
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...
 
Implementation of High Speed OFDM Transceiver using FPGA
Implementation of High Speed OFDM Transceiver using FPGAImplementation of High Speed OFDM Transceiver using FPGA
Implementation of High Speed OFDM Transceiver using FPGA
 
Analysis of Women Harassment inVillages Using CETD Matrix Modal
Analysis of Women Harassment inVillages Using CETD Matrix ModalAnalysis of Women Harassment inVillages Using CETD Matrix Modal
Analysis of Women Harassment inVillages Using CETD Matrix Modal
 
Copy of colloquium 3 latest
Copy of  colloquium 3 latestCopy of  colloquium 3 latest
Copy of colloquium 3 latest
 
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEA NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCE
 
Paper id 37201520
Paper id 37201520Paper id 37201520
Paper id 37201520
 
Iaetsd multioperand redundant adders on fpg as
Iaetsd multioperand redundant adders on fpg asIaetsd multioperand redundant adders on fpg as
Iaetsd multioperand redundant adders on fpg as
 
An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filterAn fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter
 
An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter An fpga implementation of the lms adaptive filter
An fpga implementation of the lms adaptive filter
 

Recently uploaded

list of states and organizations .pdf
list of  states  and  organizations .pdflist of  states  and  organizations .pdf
list of states and organizations .pdf
Rbc Rbcua
 
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel ChartSatta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
➒➌➎➏➑➐➋➑➐➐Dpboss Matka Guessing Satta Matka Kalyan Chart Indian Matka
 
GKohler - Retail Scavenger Hunt Presentation
GKohler - Retail Scavenger Hunt PresentationGKohler - Retail Scavenger Hunt Presentation
GKohler - Retail Scavenger Hunt Presentation
GraceKohler1
 
Zodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
Zodiac Signs and Food Preferences_ What Your Sign Says About Your TasteZodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
Zodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
my Pandit
 
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
BBPMedia1
 
Business storytelling: key ingredients to a story
Business storytelling: key ingredients to a storyBusiness storytelling: key ingredients to a story
Business storytelling: key ingredients to a story
Alexandra Fulford
 
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
❼❷⓿❺❻❷❽❷❼❽ Dpboss Kalyan Satta Matka Guessing Matka Result Main Bazar chart
 
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
taqyea
 
2022 Vintage Roman Numerals Men Rings
2022 Vintage Roman  Numerals  Men  Rings2022 Vintage Roman  Numerals  Men  Rings
2022 Vintage Roman Numerals Men Rings
aragme
 
Lundin Gold Corporate Presentation - June 2024
Lundin Gold Corporate Presentation - June 2024Lundin Gold Corporate Presentation - June 2024
Lundin Gold Corporate Presentation - June 2024
Adnet Communications
 
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
Ksquare Energy Pvt. Ltd.
 
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women MagazineEllen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
CIOWomenMagazine
 
The Genesis of BriansClub.cm Famous Dark WEb Platform
The Genesis of BriansClub.cm Famous Dark WEb PlatformThe Genesis of BriansClub.cm Famous Dark WEb Platform
The Genesis of BriansClub.cm Famous Dark WEb Platform
SabaaSudozai
 
DearbornMusic-KatherineJasperFullSailUni
DearbornMusic-KatherineJasperFullSailUniDearbornMusic-KatherineJasperFullSailUni
DearbornMusic-KatherineJasperFullSailUni
katiejasper96
 
IMG_20240615_091110.pdf dpboss guessing
IMG_20240615_091110.pdf dpboss  guessingIMG_20240615_091110.pdf dpboss  guessing
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
Niswey
 
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian MatkaDpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
dpbossdpboss69
 
Discover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling ServiceDiscover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling Service
obriengroupinc04
 
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
taqyea
 
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
Lacey Max
 

Recently uploaded (20)

list of states and organizations .pdf
list of  states  and  organizations .pdflist of  states  and  organizations .pdf
list of states and organizations .pdf
 
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel ChartSatta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
Satta Matka Dpboss Matka Guessing Kalyan Chart Indian Matka Kalyan panel Chart
 
GKohler - Retail Scavenger Hunt Presentation
GKohler - Retail Scavenger Hunt PresentationGKohler - Retail Scavenger Hunt Presentation
GKohler - Retail Scavenger Hunt Presentation
 
Zodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
Zodiac Signs and Food Preferences_ What Your Sign Says About Your TasteZodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
Zodiac Signs and Food Preferences_ What Your Sign Says About Your Taste
 
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
NIMA2024 | De toegevoegde waarde van DEI en ESG in campagnes | Nathalie Lam |...
 
Business storytelling: key ingredients to a story
Business storytelling: key ingredients to a storyBusiness storytelling: key ingredients to a story
Business storytelling: key ingredients to a story
 
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Fin...
 
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
一比一原版(QMUE毕业证书)英国爱丁堡玛格丽特女王大学毕业证文凭如何办理
 
2022 Vintage Roman Numerals Men Rings
2022 Vintage Roman  Numerals  Men  Rings2022 Vintage Roman  Numerals  Men  Rings
2022 Vintage Roman Numerals Men Rings
 
Lundin Gold Corporate Presentation - June 2024
Lundin Gold Corporate Presentation - June 2024Lundin Gold Corporate Presentation - June 2024
Lundin Gold Corporate Presentation - June 2024
 
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
PM Surya Ghar Muft Bijli Yojana: Online Application, Eligibility, Subsidies &...
 
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women MagazineEllen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women Magazine
 
The Genesis of BriansClub.cm Famous Dark WEb Platform
The Genesis of BriansClub.cm Famous Dark WEb PlatformThe Genesis of BriansClub.cm Famous Dark WEb Platform
The Genesis of BriansClub.cm Famous Dark WEb Platform
 
DearbornMusic-KatherineJasperFullSailUni
DearbornMusic-KatherineJasperFullSailUniDearbornMusic-KatherineJasperFullSailUni
DearbornMusic-KatherineJasperFullSailUni
 
IMG_20240615_091110.pdf dpboss guessing
IMG_20240615_091110.pdf dpboss  guessingIMG_20240615_091110.pdf dpboss  guessing
IMG_20240615_091110.pdf dpboss guessing
 
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
Unlocking WhatsApp Marketing with HubSpot: Integrating Messaging into Your Ma...
 
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian MatkaDpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian Matka
 
Discover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling ServiceDiscover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling Service
 
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
一比一原版新西兰奥塔哥大学毕业证(otago毕业证)如何办理
 
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
How are Lilac French Bulldogs Beauty Charming the World and Capturing Hearts....
 

Flexible dsp accelerator architecture exploiting carry save arithmetic

  • 1. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Abstract: Hardware acceleration has been proved an extremelypromising implementation strategy for the digital signal processing (DSP)domain. Rather than adopting a monolithic application-specific integratedcircuit design approach, in this brief, we present a novel acceleratorarchitecture comprising flexible computational units that support theexecution of a large set of operation templates found in DSP kernels.We differentiate from previous works on flexible accelerators by enablingcomputations to be aggressively performed with carry-save (CS) formatteddata. Advanced arithmetic design concepts, i.e., recoding techniques,are utilized enabling CS optimizations to be performed in a larger scopethan in previous approaches.The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Enhancement of the project: Perform the other temple of the FCU. Existing system: Modern embedded systems target high-end application domainsrequiring efficient implementations of computationally intensivedigital signal processing (DSP) functions. The incorporation ofheterogeneity through specialized hardware accelerators improvesperformance and reduces energy consumption. Althoughapplication-specific integrated circuits (ASICs) form the ideal accelerationsolution in terms of performance and power, their inflexibilityleads to increased silicon complexity, as multiple instantiated ASICsare needed to accelerate various kernels. Many researchers haveproposed the use of domain-specific coarse-grained reconfigurable accelerators in order to increase ASICs’ flexibility withoutsignificantly compromising their performance. The aforementioned reconfigurable architectures excludearithmetic optimizations during the architectural synthesis andconsider them only at the internal circuit structure of primitivecomponents, e.g., adders, during the logic synthesis. However,research activities have shown that the arithmeticoptimizations at higher abstraction levels than the structuralcircuit one significantly impact on the datapath performance. In, timing-driven optimizations based on carry-save (CS) arithmetic were performed at the post-Register Transfer Level (RTL) design stage. In, common subexpression eliminationin CS computations is used to optimize linear DSP circuits. Verma et al. developed transformation techniques on theapplication’s DFG to maximize
  • 2. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications the use of CS arithmetic prior theactual datapath synthesis. The aforementioned CS optimizationapproaches target inflexible datapath, i.e., ASIC, implementations. Recently, Xydis et al. proposed a flexible architecturecombining the ILP and pipelining techniques with the CS- awareoperation chaining. However, the entire aforementioned solutions featurean inherent limitation, i.e., CS optimization is bounded to mergingonly additions/subtractions. A CS to binary conversion is insertedbefore each operation that differs from addition/subtraction, e.g.,multiplication, thus, allocating multiple CS to binary conversionsthat heavily degrades performance due to time-consuming carrypropagations. Disadvantages:  high the area  high the power Proposed system: The proposed flexible accelerator architecture is shown in Fig. 1.Each FCU operates directly on CS operands and produces data inthe same form1 for direct reuse of intermediate results. Each FCU operates on 16-bit operands. Such a bit-length is adequate for themost DSP datapaths, but the architectural concept of the FCUcan be straightforwardly adapted for smaller or larger bit- lengths.The number of FCUs is determined at design time based on theILP and area constraints imposed by the designer. The CStoBinmodule is a ripple-carry adder and converts the CS form
  • 3. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications to the two’scomplement one. The register bank consists of scratch registers andis used for storing intermediate results and sharing operands amongthe FCUs. Different DSP kernels (i.e., different register allocationand data communication patterns per kernel) can be mapped ontothe proposed architecture using post-RTL datapath interconnectionsharing techniques. The control unit drives the overallarchitecture (i.e., communication between the data port and theregister bank, configuration words of the FCUs and selection signalsfor the multiplexers) in each clock cycle. Structure of the Proposed Flexible Computational Unit: The structure of the FCU (Fig. 2) has been designed to enablehigh-performance flexible operation chaining based on a library of operation templates. Each FCU can be configured to anyof the T1–T5 operation templates shown in Fig. 3. Figure 1 : Abstract form of the flexible datapath. The proposedFCU enables intra-template operation chaining by fusing the additionsperformed before/after the multiplication and performs any partialoperation template of the following complex operations: W∗ = A × (X∗ + Y∗) + K∗ (1) W∗ = A × K∗ + (X∗ + Y ∗). (2)
  • 4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Figure 2 : FCU. The following relation holds for all CS data: X∗ = {XC, XS} =XC + XS. The operand A is a two’s complement number. Thealternative execution paths in each FCU are specified after properlysetting the control signals of the multiplexers MUX1 and MUX2 (Fig. 2). The multiplexer MUX0 outputs Y ∗ when CL0 = 0(i.e., X∗ + Y ∗ is carried out) or Y ∗ when X∗ − Y ∗ is requiredand CL0 = 1. The two’s complement 4:2 CS adder produces theN∗ = X∗ +Y ∗ when the input carry equals 0 or the N∗ = X∗ −Y ∗when the input carry equals 1. The MUX1 determines if N∗ (1) orK∗ (2) is multiplied with A. TheMUX2 specifies if K∗ (1) or N∗ (2)is added with the multiplication product. The multiplexer MUX3accepts the output of MUX2 and its 1’s complement and outputsthe former one when an addition with the multiplication product isrequired (i.e., CL3 = 0) or the later one when a subtraction is carriedout (i.e., CL3 = 1). The 1- bit ace for the subtraction is added in theCS adder tree.
  • 5. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Figure 3 : FCU template library. The multiplier comprises a CS-to-MB module, which adopts arecently proposed techniqueto recode the 17-bit P∗ in itsrespective MB digits with minimal carry propagation. The multiplier’sproduct consists of 17 bits. The multiplier includes a compensationmethod for reducing the error imposed at the product’s accuracy bythe truncation technique. However, since all the FCU inputsconsist of 16 bits and provided that there are no overflows, the16 most significant bits of the 17-bit W∗ (i.e., the output of theCarry-Save Adder (CSA) tree, and thus, of the FCU) are inserted inthe appropriate FCU when requested. Advantages:  high degrees of computational density  reduce the area  reduce the power Software implementation:  Modelsim  Xilinx ISE