Fully serial multipliers can play an important role in the implementation of DSP algorithms in resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin count and moderate throughput rates. In this paper two structures that implement the fully serial multiplication operation are presented. One significant aspect of the new designs is that they are systolic and require near communication links only. They are superior in speed and area usage to similar architectures in the literature. The paper also present a new fully serial multiplier optimized for area-time2 efficiency with better performance than available architectures in the open literature.
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Low-Complexity Redundant Multiplier Architecture for Finite...ijcisjournal
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is
employed in applications like cryptography for data encryption and decryptionto deal with discrete
mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because
of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized
using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low
area and power when compared to the previous structures using the same representation.
Graph based transistor network generation method for supergate designIeee Xpert
Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design
High performance pipelined architecture of elliptic curve scalar multiplicati...Ieee Xpert
High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m)
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESidescitation
Secure data transmission is very important in any communication systems.
Network Security provides many techniques for efficient data transmission through
unprotected network. Cryptography provides a method for securing the transmission of
information by the process of encryption. Encryption converts the message in to unreadable
form (Cipher Text) . Decryption converts this Cipher Text back to original message.
Advanced Encryption Standard (AES) has been used as the first choice of cryptographic
algorithm for many security based applications because of the high level of security and
flexibility of implementation in hardware and software. This paper presents an area
efficient, low power design for AES based on an 8-bit data path making it suitable for
wireless security applications. It has a significant power-area-latency performance
improvements over other existing AES designs. For high performance applications, AES S-
box and inverse S-box implemented using composite field Arithmetic (CFA). Also low
resource Mixcolumn structure is used in this structure. The 8 bit data path architecture is
implemented in XILINX 13.2 and simulated using MODELSIM 6.5 software. Also the
power and area calculation is done with the help of SYNOPSYS software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Low-Complexity Redundant Multiplier Architecture for Finite...ijcisjournal
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is
employed in applications like cryptography for data encryption and decryptionto deal with discrete
mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because
of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized
using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low
area and power when compared to the previous structures using the same representation.
Graph based transistor network generation method for supergate designIeee Xpert
Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design Graph based transistor network generation method for supergate design
High performance pipelined architecture of elliptic curve scalar multiplicati...Ieee Xpert
High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m)
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast ...Kumar Goud
Abstract— Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process; one of them is Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. In this paper Wallace tree construction is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. In this paper Wallace tree is constructed by traditional method and with the help of compressor techniques such as 4:2 compressor, 5:2 compressor, 6:2 compressor, 7:2 compressor. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity.
Index Terms—Component, formatting, style, styling, insert. (key words)
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
A high performance fir filter architecture for fixed and reconfigurable appli...Ieee Xpert
A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications
An Efficient High Speed Design of 16-Bit Sparse-Tree RSFQ AdderIJERA Editor
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast ...Kumar Goud
Abstract— Designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Speed of the multiplier can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in a multiplication process; one of them is Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. In this paper Wallace tree construction is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. In this paper Wallace tree is constructed by traditional method and with the help of compressor techniques such as 4:2 compressor, 5:2 compressor, 6:2 compressor, 7:2 compressor. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity.
Index Terms—Component, formatting, style, styling, insert. (key words)
Low Power Implementation of Booth’s Multiplier using Reversible GatesIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Power Optimization using Reversible Gates for Booth’s MultiplierIJMTST Journal
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers’ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth’s multiplier in reversible mode. So that power is optimised Booth’s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
A high performance fir filter architecture for fixed and reconfigurable appli...Ieee Xpert
A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications A high performance fir filter architecture for fixed and reconfigurable applications
An Efficient High Speed Design of 16-Bit Sparse-Tree RSFQ AdderIJERA Editor
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of Mix and Inverse Mix Column for AES Algorithmijsrd.com
advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In order to reduce the area consumption and to increase the speed mix and inverse mix column transformation can be used as a single module .This paper contains design of new architecture, its simulation and implementation results and comparison with previous architecture.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
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Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Compressor based approximate multiplier architectures for media processing ap...IJECEIAES
Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced up to 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Designing a Novel High Performance Four-to-Two Compressor Cell Based on CNTFE...IJECEIAES
Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore, it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high-performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Implementation of FinFET technology based low power 4×4 Wallace tree multipli...TELKOMNIKA JOURNAL
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
Comparative Study of Low Power Low Area Bypass Multipliers for Signal Process...IJERA Editor
This paper presents a comparative study of 1-dimensional bypassing multipliers on basis of delay, area and power. If we can reduce the power consumption of the multiplier block, then we can reduce the power consumption of various digital signal processing chips and communication systems. In 2-dimensional bypass multiplier is presented the effective analysis of Slices, Lut, Cost & area is achieved. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL using Xilinx 12.4 ISE. Results are showed and it is verified using the Spartan-3E and Synopsys respectively.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unitrahulmonikasharma
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
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Area Efficient and Reduced Pin Count Multipliers
1. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 1
Area Efficient and Reduced Pin Count Multipliers
Omar Nibouche o.nibouche@tu.edu.sa
College of Computers and Information Technology
Taif University
POB 888 Taif 21964, KSA
Abstract
Fully serial multipliers can play an important role in the implementation of DSP algorithms in
resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin
count and moderate throughput rates. In this paper two structures that implement the fully serial
multiplication operation are presented. One significant aspect of the new designs is that they are
systolic and require near communication links only. They are superior in speed and area usage to
similar architectures in the literature. The paper also present a new fully serial multiplier optimized
for area-time
2
efficiency with better performance than available architectures in the open
literature.
Keywords: Educed Pin Count, Serial Multiplication, Area-Time
2
.
1. INTRODUCTION
There is a crucial advantage offered by bit-serial processors over their parallel counterpart, which
lies in the very efficient use of chip area. They are particularly suitable for applications that require
slow to moderate speeds and in batch mode applications. By contrast, bit-parallel processors are
useful for fast speed systems, but at the expense of larger a area usage and thus they are more
expensive [1-2].
Traditional bit serial multiplier structures suffer from an inefficient generation of partial products,
which leads to hardware overuse and slow speed systems. In this paper, two structures for bit serial
multiplication are presented. The first structure, called structure I, is the first fully serial multiplier
reported in the literature with comparable performance - in terms of speed- to existing serial-parallel
multipliers. The second structure, termed structure II, requires an extra multiplexer in the clock path;
thus making it slower, but has the merit of reducing the latency of the multiplier.
The remainder of the paper is organised as follows: in section 2, the previous work in the literature is
reviewed, while section 3 describes the new structures for fully serial multiplication. Section 4 is
concerned with an optimisation of the multiplier of Structure I in terms of area-time
2
efficiency. A
comparison of performance is shown in section 5 and conclusions are given in section 6.
2. BIT SERIAL MULTIPLIERS: A REVIEW
One of the early bit serial multipliers was proposed by [3]. It generates the partial products in a
recursive fashion. Consider the multiplication of two n-bit positive numbers A and B as follows:
∑
−=
=
=
1
0
2
ni
i
i
iaA (1)
and
∑
−=
=
=
1
0
2
ni
i
i
ibB (2)
2. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 2
Let Pi represents the partial product computed after the i
th
bit is fed [3]. Pi is given by:
i
2
111 22 ba)AbB(aPP i
i
i-ii-i
i
i-i +++= (3)
where Ai and Bi represent the value of the operands A and B, respectively, and by considering only
bits from the Least Significant Bit (LSB) to the i
th
bit, that is,
Ai = A mod 2
i+1
(4)
and
Bi = B mod 2
i+1
(5)
with the initial values P-1 = A-1 = B-1 = 0.
The generation of the partial product, using equation (3), and their assignment to the multiplier cells
is shown in Table 1 below:
Cycle P Cell 1 Cell 2
1
2
3
4
5
6
7
8
a3
b3
Cell 3 Cell 4
a2
b3
+a3
b2
P0
a2b2
a1
b1
a0
b0
a1b2+a2b1
a0
b1
+a1
b0
a0
b2
+a2
b0
a1
b3
+a3
b1
a0
b3
+a3
b3
P1
P2
P3
P4
P5
P6
P7
TABLE 1: Multiplication Scheme of [3].
From the above table, each cell generates two new bit-products every cycle. To cope with this
constraint, The Basic Cell (BC) of the multiplier proposed by [3] is built around a 5 to 3 counter. The
counter is capable of accumulating five inputs of the same weight to a sum-bit (Sout) of the same
weight as the inputs, i.e.2
0
, 1
st
carry-bit (C
1
out) of a weight of 2
1
and 2
nd
carry-bit (C
2
out) of a weight of
2
2
. In particular, the sum-bit is calculated through a tree of EXOR gate to reduce the propagation
delay within the cell. The BC of the multiplier is shown in Figure 1. The multiplier uses n identical
cells to perform the multiplication of two n-bit numbers in 2n cycles, as it can be seen in Figure 2.
3. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 3
SoutC1
out C2
out
Cin
Sin
ai
bi
control
5to3 counter
Sout
Cout
Latch
FA
FA
HA
22
21
20
20
2020
20
20
(b) (a)
FIGURE 1 (a): 5 to 3 Counter Made of Two FAs and One HA (b). The BC of [3].
BC n BC 2 BC 1
ai
Si
0
control
bi
FIGURE 2: The n-bit Multiplier by [3].
In [4], modifications were carried out on the multiplication scheme of Table 1 to make a more efficient
use of the hardware. In fact, the multiplier proposed by [4] uses only half the number of cells required
by [3]. To achieve this, the partial products generated by the last n/2 cells in [3] were reallocated to
the first n/2 cells and rescheduled at cycle n+1. In this way, a full utilisation of cells 1 to n/2 can be
achieved, as it can be shown in Table 2.
Cycle P Cell 1 Cell 2
1
2
3
4
5
6
7
8
a3
b3
a2b3+a3b2
P0
a2
b2
a1
b1
a0b0
a1b2+a2b1
a0b1+a1b0
a0b2+a2b0
a1
b3
+a3
b1
a0
b3
+a3
b3
P1
P2
P3
P4
P5
P6
P7
TABLE 2: Multiplication Scheme by [4].
4. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 4
The multiplier was modified using little extra hardware: two n/2 shift registers are used to store the
n/2 most significant bits of the data words A and B and n/2 multiplexers. The BC of the modified
multiplier d is shown in Figure 3. The multiplier structure as proposed by [4] is shown in Figure 4.
This architecture has reduced the number of 5 to 3 counters by 50%, as well as reducing the number
of latches by 33%. The clock path equals the delay of a multiplexer, a gated counter and a latch.
1
0
5to3 counter
Sout
C1
out
C2
out
Cin
Sin
ai
bi
control
Cout Sout
Latch
FIGURE 3: The BC of [4].
BC N/2 BC 2 BC 1
1
0 ai
Si
0
control
1
0
n/2 Shift Register
n/2 Shift Register bi
FIGURE 4: The n-bit Multiplier by [4].
3. THE NEW FULLY SERIAL MULTIPLIERS
Although about 50% of the area used in [3] has been saved by [4], the throughput rate has not
been increased. On the contrary, it has decreased as a multiplexer was added to the structure
making the clock period of the multiplier in [4] equivalent to the delay of a multiplexer, an AND
gate, a 5 to 3 counter and a latch. To remedy this problem, two new structures are proposed.
3.1. Structure I
In order to reduce the clock path as described above, the multiplication algorithm has been modified.
It generates the bit-products associated with cells 2 to n at the (n+1)
th
cycle. The scheduling of the
tasks of the first cell is kept unchanged, but the latency of the multiplier is increased to n cycles. The
multiplication scheme is shown in Table 3 for 4-bit operands. The multiplication operation can be
divided into two parts, which can easily be done by rewriting the product of the two numbers, A and
B, in the following way:
ji
ni
i
nj
j
jibaBaB*A +
−=
=
−=
=
∑ ∑+= 2
1
1
1
0
0
(6)
5. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 5
To keep working under the constraints of sending one bit of each operand at a time, the term a0B
in equation (6) is generated by the first cell of the multiplier during the first n cycles. At this stage,
the other cells only propagate the partial products already generated by the first cell. At the
(n+1)
th
cycle, all the operand bits have been fed and the term ji
ni
i
nj
j
ji ba +
−=
=
−=
=
∑ ∑ 2
1
1
1
0
can be generated
during the last n cycles. The clock period is equivalent to the delay of a FA, an AND gate and a
latch, as shown in Figure 5. Therefore, Structure I achieves similar speed performances when
compared with serial-parallel multipliers.
3.2. Structure II
The 5 to 3 counters have been widely used in the literature [3-6]. Basically, such a counter
reduces 5 bits of the same weight to three bits: a result-bit of the same weight as the inputs (a
weight of 2
0
), a carry-bit, which has a weight of 2
1
, and a far carry-bit that has a weight of 2
2
. It is
clear that while the sum of the inputs is up to 5, the sum of the outputs is up to 6, and as such,
two representations of the outputs are excluded. Therefore, it is clearly more appropriate to
reduce the 5 inputs to 3 outputs: a result-bit of the same weight as the inputs, and 2 carry-bits of
twice the weight of the result-bit. For this purpose, a new cell has been developed by using two
FAs as shown in Figure 6. The first FA is used to accumulate two bit products with a carry feedback.
The second FA is used to generate a result-bit from the result of the first FA, the result-bit from the
adjacent cell and a carry feedback. The two carry-bits generated by the new cell are fed back and
accumulated with the bit-products of the next cycle. The sum-bit of the first FA is registered, and thus
making the clock period equivalent to the delay of a multiplexer, an AND gate, a FA and a latch. The
multiplier structure implements directly the algorithm shown in Table 2. The multiplier requires only
n/2 cells for the multiplication of two n-bit numbers. It is also modular and needs near communication
links only.
TABLE 3: Structure I Multiplication Scheme For 4-bit Operands.
Cycle P Cell 1 Cell 2 Cell 3 Cell 4
1 a0b0
2 a0b1
3 a0b2
4 P0 a0b3
5 P1 a3b0 a2b0 a1b0
6 P2 a3b1 a2b1 a1b1
7 P3 a3b2 a2b2 a1b2
8 P4 a3b3 a2b3 a1b3
9 P5
10 P6
11 P7
6. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 6
result
control
0 FA FA FA FA
1
0n Shift Register
ai
bi
control
Latch
00010001
FIGURE 5: Structure I bit-bit Serial Multiplier.
ai
bi
control
Sin
Sout
1
0
FA
FA
FIGURE 6: The Basic Cell of Structure II Fully Serial Multiplier
4. AREA-TIME2
EFFICIENT BIT-BIT SERIAL MULTIPLIER
In this section, a new multiplier structure, which is capable of multiplexing two multiplication
operations into Structure I is proposed. This has the merit of doubling the throughput rate at the
expense of extra hardware consisting of 2n multiplexers and n latches. By optimizing the
multiplier for area-time
2
efficiency, the problem of lost cycles is circumvented. The lost cycles are
the cycles needed for carry propagation once the generation of the partial-products is finished.
The best structure in the literature that can multiplex two multiplication operations into the same
multiplier was described in [7]. The algorithm presented in [7] is an improvement made on the
multiplication scheme of Table 2. Starting from this multiplication scheme, it reassigns and
reschedules the partial products generated by the (n/4+1)th cell and above starting at (n+n/4)th
cycle to the cells from 1 to n/4 at the (n+n/2)th cycle, respectively. This has the effect of freeing
n/4 most significant cells at the (n+n/4)th cycle and thereafter. The multiplication scheme adopted
by [7] to achieve this operation is shown in Table 5.
7. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 7
Cycle P Cell 1 Cell 2
1 P0
2 P1
3 P2
4 P3
5 P4
6 P5
7 P6
8 P7
a3b3
a2b3+a3b2
a2b2
a13+a3b1a0b3+a3b0
a1b2+a2b1
a1b1
a0b0
a0b1+a1b0
a0b2+a2b0
TABLE 5: Multiplication Scheme of [7].
Although the work presented in [7] can be applied to the multiplier of Structure II, it is easier to
optimize the multiplier of Structure I for area-time
2
efficiency. One can clearly observe that the
result from the first cell is not accumulated with the bit products of the other cells until the (n+1)
th
cycle. Therefore, instead of feeding the result of the first cell to its neighbouring cell, it is delayed
by n cycles using n latches before being accumulated with the rest of the partial products, as can
be seen in Figure 7. In this way, the first cell is used for n cycles to generate the bit-products of
the first multiplication operation, then is reinitialised during one cycle before being used to
generate the bit-products of the second multiplication operation for a duration of another n cycles
and so on. The remaining cells operate almost in the same fashion. The key point is that they
generate and accumulate the bit products of the first pair of operands only when the first cell has
finished producing its bit-products. This operation lasts for n cycles before the propagation of the
partial results is switched to the multiplexers, which allows the cells to generate and accumulate
the bit-product of the second pair of data. Consequently, two multiplication operations can be
multiplexed into this multiplier every 2n cycles. The proposed architecture is depicted in Figure 6.
5. COMPARISON OF PERFORMANCE
A performance comparison of the new proposed architectures with similar structures available in
the literature [3,4] in terms of area usage and the speed of the multipliers is presented in Table 6.
In terms of speed, the multiplier of Structure I has a clock period equivalent to the delay of a FA, an
AND gate and a latch, and as such operates at faster speeds. Furthermore, the multiplier of
Structure II has a clock period of a multiplexer, an AND gate, a FA and a latch which makes it faster
than the multiplier described in [3]. In terms of area usage, the improvements introduced in [4] on the
multiplier of [3] have resulted in saving half the total number of cells. In terms of FPGA area usage
and in the case of n-bit operands, Structure I is mapped into 5n/2 slices of a virtex-4 FPGA and
Structure II uses 2n slices. The multiplier given in [3] is mapped into 5n slices while the multiplier
described in [4] requires 2n slices. These results clearly show the advantages of the new structures
in terms of both speed and area usage.
8. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 8
FAFA FA
ai
control
bi
1
0
1
0
1
0
1
0
1
0
1
0
FA
n Shift Register
FIGURE 7: The New Area-Time
2
Efficient Multiplier.
Multiplier in [3] Multiplier in [4] Structure I Structure II
Basic Cell
counter + 2 AND
gates+
multiplexer + 6
latches
Counter + 2 AND
gates + 6 latches
+ multiplexer
FA + AND gate +
4 latches
2 Fas + 2 AND
gates +
multiplexer + 6
latches
n-bit multiplier area
usage
n BCs
n/2 BCs + n +
latches
n BCs + n latches
n/2 BCs + n
latches
Longest path
AND gate +
counter +
multiplexer +
latch
AND gate +
counter +
multiplexer +
latch
AND gate + FA +
latch
AND gate + FA +
multiplexer +
latch
Latency 1 cycle 1 cycle n cycles 2 cycles
n-bit multiplier area
usage in FPGA
Virxtex-4
5n slices 2n slices 5n/2 slices 2n slices
TABLE 6: Performance Comparison.
Multiplier in [7] New multiplier
Basic Cell
counter + 2 AND gates+
multiplexer + 6 latches
FA + AND gate + 4 latches
n-bit multiplier area
usage
3n/4 BCs + 2n latches
≈63n gates (100%)
n BCs + 4n latches + 2n
multiplexers ≈66n gates
(104%)
Longest path
AND gate + counter +
multiplexer + latch
AND gate + FA + latch
TABLE 8: Performance Comparison of Area-Time
2
Efficient Structures.
Table 8 shows a comparison of performance in terms of hardware usage and speed between the
new area-time
2
efficient multiplier and the multiplier described in [7]. An estimation of the area
usage for both structures made on the number of gates is also shown. It is assumed that the area
of the 5 to 3 counter is equal to that of two FAs and a Half Adder, as shown in Figure 1a, which
has the same behavior as the 5 to 3 counter. The area usages of both structures are almost
similar, but the BCs and the longest path have not been changed. It is worth pointing out the
reason behind the choice of the multiplication scheme of Table 4. One may comment that a
"parallel to serial converter" added to a bit serial-parallel multiplier transforms it to a fully serial
multiplier with identical features to those of Structure I multiplier. Had this approach been
adopted, once the multiplier is optimised for area-time
2
efficiency, an extra n multiplexers would
9. Omar Nibouche
International Journal of Engineering (IJE), Volume (7) : Issue (1) : 2013 9
have been added to the multiplier. These multiplexers are to be added in the path of the data
making its clock path equal to the delay of a multiplexer, a gated FA and a latch; making it slower
than the multiplier derived from Structure I.
6. CONCLUSIONS
In this paper, new structures for reduced pin count multiplication architectures have been presented.
These multipliers are systolic and scalable, thus suitable for VLSI implementation. They are both
modular and need near communication links only. Structure I is the first bit-bit serial multiplier with
speed performances similar to existing serial-parallel multipliers. In Structure II, the basic cell has
been modified to a more appropriate 5 to 3 counter, thus increasing the throughput rate of the
multiplier. Structure I has been optimised for Area-Time
2
efficiency, which has resulted in doubling
the throughput rate.
7. REFERENCES
[1] K.K. Parhi, "VLSI Digital Signal Processing Systems: Design and Implementation", A Wiley-
Interscience Publication, 1999.
[2] A. Aggoun, A. Farwan, M.K. Ibrahim and A.S. Ashur, “Radix-2
n
Serial-Serial Multipliers”, IEE
proc. Circuits, Devices and Systems, vol. 151, issue 6, pp. 503-509, Dec. 2004.
[3] P. Ienne, and M. Viredaz, “A bit-serial multipliers and squarers”, IEEE Trans. Computer, 1994,
43, (12), pp.1445-1450.
[4] A. Aggoun, A.S. Ashur, and M.K. Ibrahim, “Area-Time efficient serial-serial multipliers”, IEEE
International Symp. On Circuits and Systems (ISCAS), pp.V-585-588, GENEVA, May 2000.
[5] N. Strader and V. Rhyne, “A canonical bit-sequential multiplier”, IEEE Trans. Computer, 1982,
vol. 31, pp. 691-626.
[6] J. Scanlon and W. Fuchs, “'High-performance bit-serial multiplication”, in Proc. IEEE ICCD'86,
Rye Brook, NY, Oct. 1986.
[7] A.S. Ashur, “New Efficient Multiplication Structure and their Applications”. Ph.D. thesis, Dept.
of Electrical and Electronic Eng., the University of Nottingham, 1996.