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A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Graph-Based Transistor Network Generation Method for
Supergate Design
Abstract:
Transistor network optimization represents an effective way of improving VLSI circuits. In
VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are
strongly related to the number of transistors. This proposed architecture described an efficient
graph-based method to generate optimized transistor (switch) networks. The proposed
architecture of this paper will be planned to implemented and also analysis the output current,
output voltage, area using Dsch31 and micro wind.
Enhancement of the project:
Existing System:
I N VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are
strongly related to the number of transistors (switches). Hence, transistor arrangement
optimization is of special interest when designing standard cell libraries and custom gates.
Switch based technologies, such as CMOS, FinFET, and carbon nanotubes, can take advantage
of such an improvement. Therefore, efficient algorithms to automatically generate optimized
transistor networks are quite useful for designing digital integrated circuits (ICs).
Several methods have been presented in the literature for generating and optimizing transistor
networks. Most traditional solutions are based on factoring Boolean expressions, in which only
series–parallel (SP) associations of transistors can be obtained from factored forms. On the other
hand, graph-based methods are able to find SP and also non-SP (NSP) arrangements with
potential reduction in transistor count. Despite the efforts of previous works, there is still a room
for improving the generation of transistor networks.
Disadvantages:
 Usage of number of transistor is high.
 Power and area are high
Proposed System:
The proposed method comprises two main modules: 1) the kernel identification and 2) the switch
network composition. The former receives an ISOP F and identifies individual NSP and SP
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
switch networks, representing sub functions of f. The latter composes those networks into a
single network by performing logic sharing. The provided output is an optimized switch network
representing the target function f.The execution flow of the method is presented in Fig. 2.
Figure 1 : Execution flow of the proposed method.
Kernel Identification
During the kernel identification module, an intermediate data structure called kernel is used to
search for possible SP and NSP networks. A kernel of an ISOP F with m cubes is an undirected
graph G = (V, E), where vertices in V = {v1, v2, . . . ,vm} represent distinct cubes of F. An edgee
= (vi , v j ) ∈ E, i j , exists if and only if vi ∩ v j ∅.Such edge e is labeled vi ∩ v j. Using the
kernel structure, it is possible to determine the relationship among cubes of Fin order to perform
logic sharing. This way, each step of the kernel identification module aims to extract kernels
from F that leads to optimized switch count.
The kernel identification module is divided in four steps; each step of this first module is detailed
presented below.
1. Non-series–Parallel Kernel Finder:
Let f be a Boolean function given in ISOP form F =c1 + ··· +cm, where m denotes the number
of cubes in F. In order to identify NSP kernels, the combination of m cubes are taken four at a
time, i.e., four-combination of cubes. The sum of such four cubes results in an ISOP H, which
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
represents h that is a sub-function of f. A kernel with four vertices is obtained from H. To ensure
that the generated kernel results in a NSP switch network, two rules must be checked.
Rule 1: Let Ev be the set of edges connected to the vertex v ∈V. For each cube (vertex) v ∈V, all
literals from v must be shared through the edges e ∈ Ev.
Rule 2: The kernel obtained from H must be isomorphic to the graph shown in Fig. 3. Such a
graph template is referred as NSP kernel.
Figure 2 : NSP kernel template.
Figure 3 : Resulting switch network
2. Series–Parallel Kernel Finder:
Let F1 be an ISOP form that represents all the cubes of F that were not used to build switch
networks in the NSP kernel finder step. To identify SP kernels, combination of m1cubes from F1
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
are taken four at a time. A kernel with four vertices is then obtained. To ensure that the obtained
kernel results in a valid SP network, Rule 1 and the following Rule 3 must be checked.
Rule 3: The obtained kernel must be isomorphic to the graph shown in Fig. 5. Such a graph
template is referred as SP kernel.
Figure 4 : SP kernel template
Figure 5 : Resulting switch network
3. Redundant Cube Insertion:
In some cases, it is useful to build NSP arrangements with redundant cubes instead of using SP
associations. Thus, when there still cubes not represented through NSP and SP networks, the
redundant cube insertion step tries to build NSP kernels by combining remaining cubes with
redundant cubes. Let F be an ISOP representing the Boolean function f. A cube c is redundant if
F + c =f. Consider a switch network representing an ISOP f. An implementation of a redundant
cube cin such a network leads to a redundant logic path, i.e., the path does not contribute to the
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
logic behavior of the network. Even though, redundant paths allow efficient logic sharing in NSP
networks.
The redundant cube insertion step works over an ISOP F 2 representing the cubes that were not
implemented by NSP and SP kernel finder steps. To obtain NSP kernels with redundant cubes,
combinations ofm2cubes are taken three at a time, wherem2is the number of cubes in F2. A
kernel with three vertices is then obtained for each combination. Thus, a fourth cube (vertex) vz
is inserted into the kernel according to the following rule.
Rule 4: Let Ev be the set of edges connected to the vertex v ∈ V. For each cube (vertex) v ∈ V,
the literals from v that were not shared through the edges e ∈ Ev are inserted in vz.
4. Branched Network Generation:
Cubes from ISOP F are removed when a network implementation representing it is found. Even
though previous steps are very efficient in finding logic sharing, there may still cubes not
represented through any of the found networks. In this sense, the remaining cubes in F3 are
implemented as a single switch network. Therefore, the branched network generation step
translates each remaining cube in F3 to a branch of switches associate in series.
Network Composition
The network composition module receives the function F and a list of partial switch networks S,
generated during the kernel identification module. This module composes the networks from S in
an iterative process by performing logic sharing among such networks. The target network starts
empty and, for each network s ∈ S a parallel association is performed together with simple and
complex sharing strategies. The simple and the complex switch sharing are applied in order to
remove redundant switches in the target network.
The simple and the complex switch sharing steps are presented in the following sections
1) Simple Sharing
2) Complex Sharing together with their respective time complexities.
1. Simple Sharing:
Basically, the method traverses the switch network searching for equivalent switches, i.e.,
switches that are controlled by the same literal. The network is then restructured in such a way
that one common node between equivalent switches is available. In some cases, the equivalent
switches must be swapped in the networks in order to share a common node. When a common
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
node between equivalent switches is available, only one switch is necessary, leading to a
reduction in the number of switches.
2. Complex Sharing:
The complex sharing step receives a preprocessed network provided by the previous step and
tries to perform additional optimizations. As mentioned in the simple sharing step, after finding
equivalent switches, the procedure checks if the candidate switches have a common node that
enables sharing. However, there are some cases where a common node is not directly found due
to the position of the switches in the network. Hence, in order to improve the switch sharing,
straightforward SP switch compressions are performed, as shown in Fig. 6 (a) and (b),
respectively. Then, simple switch sharing is applied over the compressed network.
Figure 6 : (a) Series switch compression. (b) Parallel switch compression.
Transistor stack bounding
Switch networks can be exploited by switch-based technologies, which present some restrictions
or guidelines to be followed by designers. For example, in the conventional CMOS design
technology, the maximum number of stacked transistors is usually limited to four. Such
restriction is done in order to avoid performance degradation. Notice that there is a lower bound
on the stacked transistors in switch networks. This lower bound corresponds to the minimum
decision chain (MDC) property of the represented Boolean functions. In this sense, an interesting
feature to control (or to limit) the number of stacked transistors was included in our method. The
method can operate in two execution modes, bounded and unbounded, as described below.
1. Bounded Mode
In this execution mode, a bound variable is used as reference to control the maximum number of
transistors in series. The bound value must be equal or greater than the number of literals of the
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
smallest cube from F, i.e., the maximum number of literals in a single cube. When the method is
running in the bounded mode, the kernel identification module accepts only switch networks in
which maximum stacked transistors do not exceed the bound value. Hence, the networks
satisfying such a bound are added to the list S of found networks. This control is also performed
during the network composition module when applying switch sharing, since it can increase the
transistor stack.
2. Unbounded Mode
When running in the unbounded mode, there is no restriction of transistor stacking, i.e., the
bound variable is not considered. Basically, just the total transistor count of the network is taken
as metric cost. Hence, there are cases that the networks generated through the unbounded mode
result fewer transistors when compared with bounded solutions. Moreover, these different modes
are quite useful to explore the tradeoff between circuit area and performance.
Advantages:
 reduction in the number of transistor
 improve the area and power consumption
Software implementation:
 Dsch31
 micro wind.

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Graph based transistor network generation method for supergate design

  • 1. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Graph-Based Transistor Network Generation Method for Supergate Design Abstract: Transistor network optimization represents an effective way of improving VLSI circuits. In VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are strongly related to the number of transistors. This proposed architecture described an efficient graph-based method to generate optimized transistor (switch) networks. The proposed architecture of this paper will be planned to implemented and also analysis the output current, output voltage, area using Dsch31 and micro wind. Enhancement of the project: Existing System: I N VLSI digital design, the signal delay propagation, power dissipation, and area of circuits are strongly related to the number of transistors (switches). Hence, transistor arrangement optimization is of special interest when designing standard cell libraries and custom gates. Switch based technologies, such as CMOS, FinFET, and carbon nanotubes, can take advantage of such an improvement. Therefore, efficient algorithms to automatically generate optimized transistor networks are quite useful for designing digital integrated circuits (ICs). Several methods have been presented in the literature for generating and optimizing transistor networks. Most traditional solutions are based on factoring Boolean expressions, in which only series–parallel (SP) associations of transistors can be obtained from factored forms. On the other hand, graph-based methods are able to find SP and also non-SP (NSP) arrangements with potential reduction in transistor count. Despite the efforts of previous works, there is still a room for improving the generation of transistor networks. Disadvantages:  Usage of number of transistor is high.  Power and area are high Proposed System: The proposed method comprises two main modules: 1) the kernel identification and 2) the switch network composition. The former receives an ISOP F and identifies individual NSP and SP
  • 2. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications switch networks, representing sub functions of f. The latter composes those networks into a single network by performing logic sharing. The provided output is an optimized switch network representing the target function f.The execution flow of the method is presented in Fig. 2. Figure 1 : Execution flow of the proposed method. Kernel Identification During the kernel identification module, an intermediate data structure called kernel is used to search for possible SP and NSP networks. A kernel of an ISOP F with m cubes is an undirected graph G = (V, E), where vertices in V = {v1, v2, . . . ,vm} represent distinct cubes of F. An edgee = (vi , v j ) ∈ E, i j , exists if and only if vi ∩ v j ∅.Such edge e is labeled vi ∩ v j. Using the kernel structure, it is possible to determine the relationship among cubes of Fin order to perform logic sharing. This way, each step of the kernel identification module aims to extract kernels from F that leads to optimized switch count. The kernel identification module is divided in four steps; each step of this first module is detailed presented below. 1. Non-series–Parallel Kernel Finder: Let f be a Boolean function given in ISOP form F =c1 + ··· +cm, where m denotes the number of cubes in F. In order to identify NSP kernels, the combination of m cubes are taken four at a time, i.e., four-combination of cubes. The sum of such four cubes results in an ISOP H, which
  • 3. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications represents h that is a sub-function of f. A kernel with four vertices is obtained from H. To ensure that the generated kernel results in a NSP switch network, two rules must be checked. Rule 1: Let Ev be the set of edges connected to the vertex v ∈V. For each cube (vertex) v ∈V, all literals from v must be shared through the edges e ∈ Ev. Rule 2: The kernel obtained from H must be isomorphic to the graph shown in Fig. 3. Such a graph template is referred as NSP kernel. Figure 2 : NSP kernel template. Figure 3 : Resulting switch network 2. Series–Parallel Kernel Finder: Let F1 be an ISOP form that represents all the cubes of F that were not used to build switch networks in the NSP kernel finder step. To identify SP kernels, combination of m1cubes from F1
  • 4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications are taken four at a time. A kernel with four vertices is then obtained. To ensure that the obtained kernel results in a valid SP network, Rule 1 and the following Rule 3 must be checked. Rule 3: The obtained kernel must be isomorphic to the graph shown in Fig. 5. Such a graph template is referred as SP kernel. Figure 4 : SP kernel template Figure 5 : Resulting switch network 3. Redundant Cube Insertion: In some cases, it is useful to build NSP arrangements with redundant cubes instead of using SP associations. Thus, when there still cubes not represented through NSP and SP networks, the redundant cube insertion step tries to build NSP kernels by combining remaining cubes with redundant cubes. Let F be an ISOP representing the Boolean function f. A cube c is redundant if F + c =f. Consider a switch network representing an ISOP f. An implementation of a redundant cube cin such a network leads to a redundant logic path, i.e., the path does not contribute to the
  • 5. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications logic behavior of the network. Even though, redundant paths allow efficient logic sharing in NSP networks. The redundant cube insertion step works over an ISOP F 2 representing the cubes that were not implemented by NSP and SP kernel finder steps. To obtain NSP kernels with redundant cubes, combinations ofm2cubes are taken three at a time, wherem2is the number of cubes in F2. A kernel with three vertices is then obtained for each combination. Thus, a fourth cube (vertex) vz is inserted into the kernel according to the following rule. Rule 4: Let Ev be the set of edges connected to the vertex v ∈ V. For each cube (vertex) v ∈ V, the literals from v that were not shared through the edges e ∈ Ev are inserted in vz. 4. Branched Network Generation: Cubes from ISOP F are removed when a network implementation representing it is found. Even though previous steps are very efficient in finding logic sharing, there may still cubes not represented through any of the found networks. In this sense, the remaining cubes in F3 are implemented as a single switch network. Therefore, the branched network generation step translates each remaining cube in F3 to a branch of switches associate in series. Network Composition The network composition module receives the function F and a list of partial switch networks S, generated during the kernel identification module. This module composes the networks from S in an iterative process by performing logic sharing among such networks. The target network starts empty and, for each network s ∈ S a parallel association is performed together with simple and complex sharing strategies. The simple and the complex switch sharing are applied in order to remove redundant switches in the target network. The simple and the complex switch sharing steps are presented in the following sections 1) Simple Sharing 2) Complex Sharing together with their respective time complexities. 1. Simple Sharing: Basically, the method traverses the switch network searching for equivalent switches, i.e., switches that are controlled by the same literal. The network is then restructured in such a way that one common node between equivalent switches is available. In some cases, the equivalent switches must be swapped in the networks in order to share a common node. When a common
  • 6. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications node between equivalent switches is available, only one switch is necessary, leading to a reduction in the number of switches. 2. Complex Sharing: The complex sharing step receives a preprocessed network provided by the previous step and tries to perform additional optimizations. As mentioned in the simple sharing step, after finding equivalent switches, the procedure checks if the candidate switches have a common node that enables sharing. However, there are some cases where a common node is not directly found due to the position of the switches in the network. Hence, in order to improve the switch sharing, straightforward SP switch compressions are performed, as shown in Fig. 6 (a) and (b), respectively. Then, simple switch sharing is applied over the compressed network. Figure 6 : (a) Series switch compression. (b) Parallel switch compression. Transistor stack bounding Switch networks can be exploited by switch-based technologies, which present some restrictions or guidelines to be followed by designers. For example, in the conventional CMOS design technology, the maximum number of stacked transistors is usually limited to four. Such restriction is done in order to avoid performance degradation. Notice that there is a lower bound on the stacked transistors in switch networks. This lower bound corresponds to the minimum decision chain (MDC) property of the represented Boolean functions. In this sense, an interesting feature to control (or to limit) the number of stacked transistors was included in our method. The method can operate in two execution modes, bounded and unbounded, as described below. 1. Bounded Mode In this execution mode, a bound variable is used as reference to control the maximum number of transistors in series. The bound value must be equal or greater than the number of literals of the
  • 7. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications smallest cube from F, i.e., the maximum number of literals in a single cube. When the method is running in the bounded mode, the kernel identification module accepts only switch networks in which maximum stacked transistors do not exceed the bound value. Hence, the networks satisfying such a bound are added to the list S of found networks. This control is also performed during the network composition module when applying switch sharing, since it can increase the transistor stack. 2. Unbounded Mode When running in the unbounded mode, there is no restriction of transistor stacking, i.e., the bound variable is not considered. Basically, just the total transistor count of the network is taken as metric cost. Hence, there are cases that the networks generated through the unbounded mode result fewer transistors when compared with bounded solutions. Moreover, these different modes are quite useful to explore the tradeoff between circuit area and performance. Advantages:  reduction in the number of transistor  improve the area and power consumption Software implementation:  Dsch31  micro wind.