SlideShare a Scribd company logo
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
High-Performance Pipelined Architecture of Elliptic
Curve Scalar Multiplication Over GF(2m
)
Abstract:
This paper proposes an efficient pipelined architecture of elliptic curve scalar multiplication
(ECSM) over GF(2m). The architecture uses a bit-parallel finite field (FF) multiplier accumulator
(MAC) based on the Karatsuba–Ofman algorithm. The Montgomery ladder algorithm is
modified for better sharing of execution paths. The data path in the architecture is well designed,
so that the critical path contains few extra logic primitives apart from the FF MAC. In order to
find the optimal number of pipeline stages, scheduling schemes with different pipeline stages are
proposed and the ideal placement of pipeline registers is thoroughly analyzed. We implement
ECSM over the five binary fields recommended by the National Institute of Standard and
Technology on Xilinx Virtex-4 and Virtex-5 field-programmable gate arrays. The three-stage
pipelined architecture is shown to have the best performance, which achieves a scalar
multiplication over GF(2163) in 6.1µs using 7354 Slices on Virtex-4. Using Virtex-5, the scalar
multiplication form=163, 233, 283, 409, and 571 can be achieved in 4.6, 7.9, 10.9, 19.4, and 36.5
µs, respectively, which are faster than previous results. The proposed architecture of this paper
analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
Elliptic curve scalar multiplication (ECSM) is the key operation, which dominates the
performance of ECC cryptosystem. Various architectures have been proposed to speed up
ECSM. Most of them explore pipeline and parallelism to improve the working frequency and to
reduce the required number of clock cycles in ECSM. Leong and Leung developed a microcoded
elliptic curve processor, supporting ECSM over GF(2m) for arbitrary m. Sakiyama et al.
proposed a superscalar coprocessor and accelerated ECSM by exploiting instruction-level
parallelism (ILP) dynamically. A pipelined application specific instruction set processor for ECC
was proposed, which performed ECSM over GF(2163) in 19.55 μs on Xilinx XC4VLX200.
Designs implemented high-speed scalar multiplication over a special class of curves, such as
Koblitz curves, binary Edwards curves, and Hessian curves. In this paper, we focus on
optimizing ECSM over generic curves in GF(2m).
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Some designs duplicate arithmetic blocks to maximize the parallelism in ECSM. For GF(2163),
Kim et al. used three Gaussian normal basis multipliers to achieve ECSM in 10 μs on Xilinx
XC4VLX80. Zhang et al. developed three finite-field (FF) cores and a main controller to achieve
ECSM in 7.7 μs on Xilinx XC4VLX80. The best design in performed ECSM in 5.5 μs on Xilinx
Virtex-5 using three digit-serial FF multipliers and one FF divider. Despite high speed, these
deigns require massive logic resources, and thus, they are not practical for FPGA
implementation. Considering the tradeoff between area and speed, many designs use word-serial
or digit-serial FF multipliers to implement ECSM. These designs usually require a large number
of clock cycles for a scalar multiplication. Ansari and Hasan proposed an efficient scheme,
which kept the pseudopipelined word-serial FF multiplier working without idle cycles. A scalar
multiplication over GF(2163) costs 4050 clock cycles and 21 μs on Xilinx XC4VLX200. FF
multipliers with different word sizes (w) were developed, and the best design with w = 55
performed ECSM over GF(2163) in 2751 clock cycles and 9.6 μs on Xilinx XC4VLX200.
Disadvantages:
 Area coverage is high
 Performance speed is slow
Proposed System:
Data Dependence Analysis of ECSM
The modified Montgomery ladder scalar multiplication totally takes m(6M + 5S + 3A) + (11M +
5A + I) operations, where M, S, A, and I denote multiplication, square, addition, and inversion in
GF(2m), respectively, and m is the dimension of the binary field GF(2m). The original
Montgomery ladder scalar multiplication requires (m − 1)(6M + 5S + 3A) + (10M +7A+3S+ I)
operations. The increased operations are due to the merged initialization and the modified
postprocess for better sharing the data path with the main loop. As square and addition are much
cheaper than multiplication, and inversion occurs only once, we can see that optimizing
operations in the main loop, especially the FF multiplication, is the key to realize high-
performance ECSM.
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Fig. 1. Data dependence graph of (a) point addition and (b) point doubling in the Montgomery ladder algorithm.
Each iteration in the main loop performs point addition and point doubling, which take 6M + 5S
+ 3A together. The data dependence of point addition and doubling in the Montgomery ladder
algorithm is shown in Fig. 1. The critical path lies in calculating the X-coordinate of point
addition, which takes 2M + 1S + 2A, as is shaded in Fig. 1. Thus, it may use at most three FF
multipliers to achieve maximum parallelism in scalar multiplication.
PROPOSED ARCHITECTURE OF ELLIPTIC CURVE SCALAR MULTIPLICATION:
we propose the high-performance architecture based on the improved Montgomery ladder scalar
multiplication algorithm, as shown in Fig. 2.
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Fig. 2. Proposed architecture of ECSM.
The proposed ECSM architecture consists of one bit-parallel FF MAC, one FF squarer, a register
bank, a finite-state machine, and a 6 × 18 control ROM. The FF MAC is implemented using the
Karatsuba–Ofman algorithm, and is well pipelined. The n-stage pipelined FF MAC takes n clock
cycles to finish one multiplication. The FF squarer is not pipelined, and one clock cycle is
required to finish one square. The inputs to FF MAC, A, B, and C, and the input to FF squarer, S,
are all registered. Another four registers T1, T2, T3, and T4 are used in the data path for data
caching.
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Fig. 3. Data path of ECSM using a three-stage pipelined FF MAC.
The data path of ECSM using a three-stage pipelined FF MAC is given for example in Fig. 6.
The terms X1, X2, Z1, and Z2 are not presented, because they are the intermediate results of the
FF MAC or FF Squarer. The bold dashed line in Fig. 6 shows the critical path of the three-stage
pipelined architecture, which consists of a pipelined FF MAC, an addition (XOR), and a 4:1
MUX. Data paths with other pipeline stages are similar to Fig. 6 except for different data
connections. Control signals stored in the control ROM are also different. But, the critical path
delay remains unchanged.
Advantages:
 Area reduction
 Speed is increased
A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications
Software implementation:
 Modelsim
 Xilinx ISE

More Related Content

What's hot

IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD Editor
 
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformationIaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd Iaetsd
 
A comparative study of different multiplier designs
A comparative study of different multiplier designsA comparative study of different multiplier designs
A comparative study of different multiplier designs
Hoopeer Hoopeer
 
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable CoefficientsTranspose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
IRJET Journal
 
J0166875
J0166875J0166875
J0166875
IOSR Journals
 
Modified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystemsModified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystems
IAEME Publication
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
IJERD Editor
 
A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...
jpstudcorner
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
IJSRD
 
Aw4102359364
Aw4102359364Aw4102359364
Aw4102359364
IJERA Editor
 
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdlIaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
Iaetsd Iaetsd
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adder
KUMARASWAMY JINNE
 
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
VLSICS Design
 
FinalReport
FinalReportFinalReport
FinalReport
LONGJIA NIU
 
Eq36876880
Eq36876880Eq36876880
Eq36876880
IJERA Editor
 
Research Inventy : International Journal of Engineering and Science is publis...
Research Inventy : International Journal of Engineering and Science is publis...Research Inventy : International Journal of Engineering and Science is publis...
Research Inventy : International Journal of Engineering and Science is publis...
researchinventy
 
Multiplier and Accumulator Using Csla
Multiplier and Accumulator Using CslaMultiplier and Accumulator Using Csla
Multiplier and Accumulator Using Csla
IOSR Journals
 
Development of an adaptive and a switched beam
Development of an adaptive and a switched beamDevelopment of an adaptive and a switched beam
Development of an adaptive and a switched beam
marwaeng
 
B1030610
B1030610B1030610
B1030610
IJERD Editor
 

What's hot (19)

IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
 
Iaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformationIaetsd pipelined parallel fft architecture through folding transformation
Iaetsd pipelined parallel fft architecture through folding transformation
 
A comparative study of different multiplier designs
A comparative study of different multiplier designsA comparative study of different multiplier designs
A comparative study of different multiplier designs
 
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable CoefficientsTranspose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
Transpose Form Fir Filter Design for Fixed and Reconfigurable Coefficients
 
J0166875
J0166875J0166875
J0166875
 
Modified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystemsModified montgomery modular multiplier for cryptosystems
Modified montgomery modular multiplier for cryptosystems
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
 
A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...A novel area efficient vlsi architecture for recursion computation in lte tur...
A novel area efficient vlsi architecture for recursion computation in lte tur...
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
 
Aw4102359364
Aw4102359364Aw4102359364
Aw4102359364
 
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdlIaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
Iaetsd vlsi architecture for exploiting carry save arithmetic using verilog hdl
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adder
 
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
 
FinalReport
FinalReportFinalReport
FinalReport
 
Eq36876880
Eq36876880Eq36876880
Eq36876880
 
Research Inventy : International Journal of Engineering and Science is publis...
Research Inventy : International Journal of Engineering and Science is publis...Research Inventy : International Journal of Engineering and Science is publis...
Research Inventy : International Journal of Engineering and Science is publis...
 
Multiplier and Accumulator Using Csla
Multiplier and Accumulator Using CslaMultiplier and Accumulator Using Csla
Multiplier and Accumulator Using Csla
 
Development of an adaptive and a switched beam
Development of an adaptive and a switched beamDevelopment of an adaptive and a switched beam
Development of an adaptive and a switched beam
 
B1030610
B1030610B1030610
B1030610
 

Similar to High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m)

PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
csandit
 
Efficient register renaming and recovery for high-performance processors.
Efficient register renaming and recovery for high-performance processors.Efficient register renaming and recovery for high-performance processors.
Efficient register renaming and recovery for high-performance processors.
Jinto George
 
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGAHigh-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
JAYAPRAKASH JPINFOTECH
 
Overview of signal integrity simulation for sfp+ interface serial links with ...
Overview of signal integrity simulation for sfp+ interface serial links with ...Overview of signal integrity simulation for sfp+ interface serial links with ...
Overview of signal integrity simulation for sfp+ interface serial links with ...
Conference Papers
 
J045075661
J045075661J045075661
J045075661
IJERA Editor
 
Design and Implementation of an Efficient Carry Skip Adder
Design and Implementation of an Efficient Carry Skip AdderDesign and Implementation of an Efficient Carry Skip Adder
Design and Implementation of an Efficient Carry Skip Adder
IRJET Journal
 
Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...
jpstudcorner
 
Iaetsd gmsk modulation implementation for gsm in dsp
Iaetsd gmsk modulation implementation for gsm in dspIaetsd gmsk modulation implementation for gsm in dsp
Iaetsd gmsk modulation implementation for gsm in dsp
Iaetsd Iaetsd
 
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESCFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
idescitation
 
FEAS_Poster_2016_WNCS_Tina
FEAS_Poster_2016_WNCS_TinaFEAS_Poster_2016_WNCS_Tina
FEAS_Poster_2016_WNCS_Tina
Tina Mirfakhraie
 
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and Development
IJERD Editor
 
F1074145
F1074145F1074145
F1074145
IJERD Editor
 
Implementation of High Throughput Radix-16 FFT Processor
Implementation of High Throughput Radix-16 FFT ProcessorImplementation of High Throughput Radix-16 FFT Processor
Implementation of High Throughput Radix-16 FFT Processor
IJMER
 
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
IRJET Journal
 
IRJET- The RTL Model of a Reconfigurable Pipelined MCM
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET- The RTL Model of a Reconfigurable Pipelined MCM
IRJET- The RTL Model of a Reconfigurable Pipelined MCM
IRJET Journal
 
Implementation of OFDM System Using Various Channel Modulation Schemes
Implementation of OFDM System Using Various Channel Modulation SchemesImplementation of OFDM System Using Various Channel Modulation Schemes
Implementation of OFDM System Using Various Channel Modulation Schemes
IJCSIS Research Publications
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
IJERD Editor
 
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
IRJET Journal
 
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSPERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
VLSICS Design
 
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSPERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
VLSICS Design
 

Similar to High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m) (20)

PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
PERFORMANCE COMPARISON DCM VERSUS QPSK FOR HIGH DATA RATES IN THE MBOFDM UWB ...
 
Efficient register renaming and recovery for high-performance processors.
Efficient register renaming and recovery for high-performance processors.Efficient register renaming and recovery for high-performance processors.
Efficient register renaming and recovery for high-performance processors.
 
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGAHigh-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
 
Overview of signal integrity simulation for sfp+ interface serial links with ...
Overview of signal integrity simulation for sfp+ interface serial links with ...Overview of signal integrity simulation for sfp+ interface serial links with ...
Overview of signal integrity simulation for sfp+ interface serial links with ...
 
J045075661
J045075661J045075661
J045075661
 
Design and Implementation of an Efficient Carry Skip Adder
Design and Implementation of an Efficient Carry Skip AdderDesign and Implementation of an Efficient Carry Skip Adder
Design and Implementation of an Efficient Carry Skip Adder
 
Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...Low cost high-performance vlsi architecture for montgomery modular multiplica...
Low cost high-performance vlsi architecture for montgomery modular multiplica...
 
Iaetsd gmsk modulation implementation for gsm in dsp
Iaetsd gmsk modulation implementation for gsm in dspIaetsd gmsk modulation implementation for gsm in dsp
Iaetsd gmsk modulation implementation for gsm in dsp
 
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AESCFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
CFA based SBOX and Modified Mixcolumn Implementation of 8 Bit Datapath for AES
 
FEAS_Poster_2016_WNCS_Tina
FEAS_Poster_2016_WNCS_TinaFEAS_Poster_2016_WNCS_Tina
FEAS_Poster_2016_WNCS_Tina
 
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and Development
 
F1074145
F1074145F1074145
F1074145
 
Implementation of High Throughput Radix-16 FFT Processor
Implementation of High Throughput Radix-16 FFT ProcessorImplementation of High Throughput Radix-16 FFT Processor
Implementation of High Throughput Radix-16 FFT Processor
 
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...
 
IRJET- The RTL Model of a Reconfigurable Pipelined MCM
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET- The RTL Model of a Reconfigurable Pipelined MCM
IRJET- The RTL Model of a Reconfigurable Pipelined MCM
 
Implementation of OFDM System Using Various Channel Modulation Schemes
Implementation of OFDM System Using Various Channel Modulation SchemesImplementation of OFDM System Using Various Channel Modulation Schemes
Implementation of OFDM System Using Various Channel Modulation Schemes
 
International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)International Journal of Engineering Research and Development (IJERD)
International Journal of Engineering Research and Development (IJERD)
 
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm t...
 
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSPERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
 
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSPERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS
 

Recently uploaded

L'indice de performance des ports à conteneurs de l'année 2023
L'indice de performance des ports à conteneurs de l'année 2023L'indice de performance des ports à conteneurs de l'année 2023
L'indice de performance des ports à conteneurs de l'année 2023
SPATPortToamasina
 
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
concepsionchomo153
 
deft. 2024 pricing guide for onboarding
deft.  2024 pricing guide for onboardingdeft.  2024 pricing guide for onboarding
deft. 2024 pricing guide for onboarding
hello960827
 
Discover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling ServiceDiscover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling Service
obriengroupinc04
 
The Enigmatic Gemini: Unveiling the Dual Personalities
The Enigmatic Gemini: Unveiling the Dual PersonalitiesThe Enigmatic Gemini: Unveiling the Dual Personalities
The Enigmatic Gemini: Unveiling the Dual Personalities
my Pandit
 
Revolutionizing Surface Protection Xlcoatings Nano Based Solutions
Revolutionizing Surface Protection Xlcoatings Nano Based SolutionsRevolutionizing Surface Protection Xlcoatings Nano Based Solutions
Revolutionizing Surface Protection Xlcoatings Nano Based Solutions
Excel coatings
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results
 
Kirill Klip GEM Royalty TNR Gold Copper Presentation
Kirill Klip GEM Royalty TNR Gold Copper PresentationKirill Klip GEM Royalty TNR Gold Copper Presentation
Kirill Klip GEM Royalty TNR Gold Copper Presentation
Kirill Klip
 
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
dpbossdpboss69
 
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
essorprof62
 
Truck Loading Conveyor Manufacturers Chennai
Truck Loading Conveyor Manufacturers ChennaiTruck Loading Conveyor Manufacturers Chennai
Truck Loading Conveyor Manufacturers Chennai
ConveyorSystem
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results
 
8328958814KALYAN MATKA | MATKA RESULT | KALYAN
8328958814KALYAN MATKA | MATKA RESULT | KALYAN8328958814KALYAN MATKA | MATKA RESULT | KALYAN
8328958814KALYAN MATKA | MATKA RESULT | KALYAN
➑➌➋➑➒➎➑➑➊➍
 
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fix
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fixKalyan chart 6366249026 India satta Matta Matka 143 jodi fix
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fix
satta Matta matka 143 Kalyan chart jodi 6366249026
 
japanese language course in delhi near me
japanese language course in delhi near mejapanese language course in delhi near me
japanese language course in delhi near me
heyfairies7
 
MECE (Mutually Exclusive, Collectively Exhaustive) Principle
MECE (Mutually Exclusive, Collectively Exhaustive) PrincipleMECE (Mutually Exclusive, Collectively Exhaustive) Principle
MECE (Mutually Exclusive, Collectively Exhaustive) Principle
Operational Excellence Consulting
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results
 
Kalyan Chart Satta Matka Dpboss Kalyan Matka Results
Kalyan Chart Satta Matka Dpboss Kalyan Matka ResultsKalyan Chart Satta Matka Dpboss Kalyan Matka Results
Kalyan Chart Satta Matka Dpboss Kalyan Matka Results
Satta Matka Dpboss Kalyan Matka Results
 
Dpboss Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Satta Matta Matka Kalyan Chart Indian MatkaDpboss Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Matka
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results
 

Recently uploaded (20)

L'indice de performance des ports à conteneurs de l'année 2023
L'indice de performance des ports à conteneurs de l'année 2023L'indice de performance des ports à conteneurs de l'année 2023
L'indice de performance des ports à conteneurs de l'année 2023
 
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
欧洲杯投注-欧洲杯投注外围盘口-欧洲杯投注盘口app|【​网址​🎉ac22.net🎉​】
 
deft. 2024 pricing guide for onboarding
deft.  2024 pricing guide for onboardingdeft.  2024 pricing guide for onboarding
deft. 2024 pricing guide for onboarding
 
Discover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling ServiceDiscover the Beauty and Functionality of The Expert Remodeling Service
Discover the Beauty and Functionality of The Expert Remodeling Service
 
The Enigmatic Gemini: Unveiling the Dual Personalities
The Enigmatic Gemini: Unveiling the Dual PersonalitiesThe Enigmatic Gemini: Unveiling the Dual Personalities
The Enigmatic Gemini: Unveiling the Dual Personalities
 
Revolutionizing Surface Protection Xlcoatings Nano Based Solutions
Revolutionizing Surface Protection Xlcoatings Nano Based SolutionsRevolutionizing Surface Protection Xlcoatings Nano Based Solutions
Revolutionizing Surface Protection Xlcoatings Nano Based Solutions
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
 
Kirill Klip GEM Royalty TNR Gold Copper Presentation
Kirill Klip GEM Royalty TNR Gold Copper PresentationKirill Klip GEM Royalty TNR Gold Copper Presentation
Kirill Klip GEM Royalty TNR Gold Copper Presentation
 
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
Call 8867766396 Dpboss Matka Guessing Satta Matta Matka Kalyan Chart Indian M...
 
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
❽❽❻❼❼❻❻❸❾❻ DPBOSS NET SPBOSS SATTA MATKA RESULT KALYAN MATKA GUESSING FREE KA...
 
Truck Loading Conveyor Manufacturers Chennai
Truck Loading Conveyor Manufacturers ChennaiTruck Loading Conveyor Manufacturers Chennai
Truck Loading Conveyor Manufacturers Chennai
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
 
8328958814KALYAN MATKA | MATKA RESULT | KALYAN
8328958814KALYAN MATKA | MATKA RESULT | KALYAN8328958814KALYAN MATKA | MATKA RESULT | KALYAN
8328958814KALYAN MATKA | MATKA RESULT | KALYAN
 
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fix
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fixKalyan chart 6366249026 India satta Matta Matka 143 jodi fix
Kalyan chart 6366249026 India satta Matta Matka 143 jodi fix
 
japanese language course in delhi near me
japanese language course in delhi near mejapanese language course in delhi near me
japanese language course in delhi near me
 
MECE (Mutually Exclusive, Collectively Exhaustive) Principle
MECE (Mutually Exclusive, Collectively Exhaustive) PrincipleMECE (Mutually Exclusive, Collectively Exhaustive) Principle
MECE (Mutually Exclusive, Collectively Exhaustive) Principle
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
 
Kalyan Chart Satta Matka Dpboss Kalyan Matka Results
Kalyan Chart Satta Matka Dpboss Kalyan Matka ResultsKalyan Chart Satta Matka Dpboss Kalyan Matka Results
Kalyan Chart Satta Matka Dpboss Kalyan Matka Results
 
Dpboss Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Satta Matta Matka Kalyan Chart Indian MatkaDpboss Satta Matta Matka Kalyan Chart Indian Matka
Dpboss Satta Matta Matka Kalyan Chart Indian Matka
 
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan ChartSatta Matka Dpboss Kalyan Matka Results Kalyan Chart
Satta Matka Dpboss Kalyan Matka Results Kalyan Chart
 

High performance pipelined architecture of elliptic curve scalar multiplication over gf(2m)

  • 1. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m ) Abstract: This paper proposes an efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2m). The architecture uses a bit-parallel finite field (FF) multiplier accumulator (MAC) based on the Karatsuba–Ofman algorithm. The Montgomery ladder algorithm is modified for better sharing of execution paths. The data path in the architecture is well designed, so that the critical path contains few extra logic primitives apart from the FF MAC. In order to find the optimal number of pipeline stages, scheduling schemes with different pipeline stages are proposed and the ideal placement of pipeline registers is thoroughly analyzed. We implement ECSM over the five binary fields recommended by the National Institute of Standard and Technology on Xilinx Virtex-4 and Virtex-5 field-programmable gate arrays. The three-stage pipelined architecture is shown to have the best performance, which achieves a scalar multiplication over GF(2163) in 6.1µs using 7354 Slices on Virtex-4. Using Virtex-5, the scalar multiplication form=163, 233, 283, 409, and 571 can be achieved in 4.6, 7.9, 10.9, 19.4, and 36.5 µs, respectively, which are faster than previous results. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Enhancement of the project: Existing System: Elliptic curve scalar multiplication (ECSM) is the key operation, which dominates the performance of ECC cryptosystem. Various architectures have been proposed to speed up ECSM. Most of them explore pipeline and parallelism to improve the working frequency and to reduce the required number of clock cycles in ECSM. Leong and Leung developed a microcoded elliptic curve processor, supporting ECSM over GF(2m) for arbitrary m. Sakiyama et al. proposed a superscalar coprocessor and accelerated ECSM by exploiting instruction-level parallelism (ILP) dynamically. A pipelined application specific instruction set processor for ECC was proposed, which performed ECSM over GF(2163) in 19.55 μs on Xilinx XC4VLX200. Designs implemented high-speed scalar multiplication over a special class of curves, such as Koblitz curves, binary Edwards curves, and Hessian curves. In this paper, we focus on optimizing ECSM over generic curves in GF(2m).
  • 2. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Some designs duplicate arithmetic blocks to maximize the parallelism in ECSM. For GF(2163), Kim et al. used three Gaussian normal basis multipliers to achieve ECSM in 10 μs on Xilinx XC4VLX80. Zhang et al. developed three finite-field (FF) cores and a main controller to achieve ECSM in 7.7 μs on Xilinx XC4VLX80. The best design in performed ECSM in 5.5 μs on Xilinx Virtex-5 using three digit-serial FF multipliers and one FF divider. Despite high speed, these deigns require massive logic resources, and thus, they are not practical for FPGA implementation. Considering the tradeoff between area and speed, many designs use word-serial or digit-serial FF multipliers to implement ECSM. These designs usually require a large number of clock cycles for a scalar multiplication. Ansari and Hasan proposed an efficient scheme, which kept the pseudopipelined word-serial FF multiplier working without idle cycles. A scalar multiplication over GF(2163) costs 4050 clock cycles and 21 μs on Xilinx XC4VLX200. FF multipliers with different word sizes (w) were developed, and the best design with w = 55 performed ECSM over GF(2163) in 2751 clock cycles and 9.6 μs on Xilinx XC4VLX200. Disadvantages:  Area coverage is high  Performance speed is slow Proposed System: Data Dependence Analysis of ECSM The modified Montgomery ladder scalar multiplication totally takes m(6M + 5S + 3A) + (11M + 5A + I) operations, where M, S, A, and I denote multiplication, square, addition, and inversion in GF(2m), respectively, and m is the dimension of the binary field GF(2m). The original Montgomery ladder scalar multiplication requires (m − 1)(6M + 5S + 3A) + (10M +7A+3S+ I) operations. The increased operations are due to the merged initialization and the modified postprocess for better sharing the data path with the main loop. As square and addition are much cheaper than multiplication, and inversion occurs only once, we can see that optimizing operations in the main loop, especially the FF multiplication, is the key to realize high- performance ECSM.
  • 3. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Fig. 1. Data dependence graph of (a) point addition and (b) point doubling in the Montgomery ladder algorithm. Each iteration in the main loop performs point addition and point doubling, which take 6M + 5S + 3A together. The data dependence of point addition and doubling in the Montgomery ladder algorithm is shown in Fig. 1. The critical path lies in calculating the X-coordinate of point addition, which takes 2M + 1S + 2A, as is shaded in Fig. 1. Thus, it may use at most three FF multipliers to achieve maximum parallelism in scalar multiplication. PROPOSED ARCHITECTURE OF ELLIPTIC CURVE SCALAR MULTIPLICATION: we propose the high-performance architecture based on the improved Montgomery ladder scalar multiplication algorithm, as shown in Fig. 2.
  • 4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Fig. 2. Proposed architecture of ECSM. The proposed ECSM architecture consists of one bit-parallel FF MAC, one FF squarer, a register bank, a finite-state machine, and a 6 × 18 control ROM. The FF MAC is implemented using the Karatsuba–Ofman algorithm, and is well pipelined. The n-stage pipelined FF MAC takes n clock cycles to finish one multiplication. The FF squarer is not pipelined, and one clock cycle is required to finish one square. The inputs to FF MAC, A, B, and C, and the input to FF squarer, S, are all registered. Another four registers T1, T2, T3, and T4 are used in the data path for data caching.
  • 5. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Fig. 3. Data path of ECSM using a three-stage pipelined FF MAC. The data path of ECSM using a three-stage pipelined FF MAC is given for example in Fig. 6. The terms X1, X2, Z1, and Z2 are not presented, because they are the intermediate results of the FF MAC or FF Squarer. The bold dashed line in Fig. 6 shows the critical path of the three-stage pipelined architecture, which consists of a pipelined FF MAC, an addition (XOR), and a 4:1 MUX. Data paths with other pipeline stages are similar to Fig. 6 except for different data connections. Control signals stored in the control ROM are also different. But, the critical path delay remains unchanged. Advantages:  Area reduction  Speed is increased
  • 6. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Software implementation:  Modelsim  Xilinx ISE