This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 32 bit Parallel Prefix Adders IOSR Journals
In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In
general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead
adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix
adders because of their advantages compare to other adders. Parallel prefix adders are faster and area
efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing
addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using
these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 32 bit Parallel Prefix Adders IOSR Journals
In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In
general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead
adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix
adders because of their advantages compare to other adders. Parallel prefix adders are faster and area
efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing
addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using
these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Modified approximate 8-point multiplier less DCT like transformIJERA Editor
Discrete Cosine Transform (DCT) is widely usedtransformation for compression in image and video standardslike H.264 or MPEGv4, JPEG etc. Currently the new standarddeveloped Codec is Highly Efficient Video Coding (HEVC) orH.265. With the help of the transformation matrix the computational cost can be dynamically reduce. This paper proposesa novel approach of multiplier-less modified approximate DCT like transformalgorithm and also comparison with exact DCT algorithm and theapproximate DCT like transform. This proposed algorithm willhave lower computational complexity. Furthermore, the proposedalgorithm will be modular in approach, and suitable for pipelinedVLSI implementation.
A High performance unified BCD adder/SubtractorPrasanna Kumar
Improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary
addition/subtraction without any extra hardware
An efficient hardware logarithm generator with modified quasi-symmetrical app...IJECEIAES
This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.
FPGA Implementation of FIR Filter using Various Algorithms: A RetrospectiveIJORCS
This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Modified approximate 8-point multiplier less DCT like transformIJERA Editor
Discrete Cosine Transform (DCT) is widely usedtransformation for compression in image and video standardslike H.264 or MPEGv4, JPEG etc. Currently the new standarddeveloped Codec is Highly Efficient Video Coding (HEVC) orH.265. With the help of the transformation matrix the computational cost can be dynamically reduce. This paper proposesa novel approach of multiplier-less modified approximate DCT like transformalgorithm and also comparison with exact DCT algorithm and theapproximate DCT like transform. This proposed algorithm willhave lower computational complexity. Furthermore, the proposedalgorithm will be modular in approach, and suitable for pipelinedVLSI implementation.
A High performance unified BCD adder/SubtractorPrasanna Kumar
Improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary
addition/subtraction without any extra hardware
An efficient hardware logarithm generator with modified quasi-symmetrical app...IJECEIAES
This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.
FPGA Implementation of FIR Filter using Various Algorithms: A RetrospectiveIJORCS
This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz. Simulate, synthesize and physical design your adder.
Follow the directions below to create the 32-bit CSA
• Create a 4-bit Carry Look Ahead (CLA) adder
• combine 8-stages of the CLA adder to create the 32-bit CSA
• use 4-bit 2-to-1 mux to choose the sum from each set of CLA
• use 1-bit 2-to-1 mux to select the carry for the next stage
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTERVLSICS Design
This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in
term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
1. International Journal of Research in Advent Technology, Vol.3, No.7, July 2015
E-ISSN: 2321-9637
31
A Novel Design of 32 Bit Unsigned Multiplier Using
Modified CSLA
Chandana Pittala1
, Devadas Matta2
PG Scholar.VLSI System Design 1
, Asst. Prof. ECE Dept. 2
, Vaagdevi College of Engineering,Warangal,India.1, 2
Email: chanda9.p@gmail.com1
, das.deva@gmail.com2
Abstract - In VLSI design speed, power and chip area are the three conflicting constraints, most often
considered in determining the performance and efficiency of the system. In this paper, the VLSI design of a high
performance and low power 32-bit unsigned modified carry select adder (MCSLA) based multiplier using CBL
term is been proposed and compared with the 32-bit unsigned conventional carry select adder (CSLA) based
multiplier. Both the design of multiplier multiplies two 32-bit unsigned integer values and gives a product term
of 64-bit value.The result analysis shows that the power area delay product reduction is possible with the
proposed MCSLA based multiplier when compared to CSLA based multiplier. These two 32-bit unsigned
multipliers are simulated using Modelsim and synthesized using Xilinx.
Index Terms- Area; CSLA; Delay; MCSLA; Power; Unsigned Multiplier; VHDL Modeling & Simulation.
1. INTRODUCTION
As the scale of integration is being growing, more and
more sophisticated signal processing systems are
being implemented on a VLSI chip [3]. The Area
speed of the system remains to be the two major
design tools; power consumption has become a critical
concern in today’s VLSI system design [8]. As we
know millions of instruction per second are performed
in microprocessors. Hence, speed of operation is the
most important constraint to be considered [3]. Due to
device portability, miniaturization of device should be
high and power consumption should be low. So, a
VLSI designer has to optimize these three parameters
in a design [2].
Addition usually impacts widely the overall
performance of digital systems and is a crucial
arithmetic function. In electronic applications, adders
are most widely used as multipliers; Digital Signal
Processor to execute various algorithms like Fast
Fourier Transform (FFT), Finite Impulse Response
(FIR) and Infinite Impulse Response (IIR).The Half-
Adders (HA) are simplest single bit adders [1]. The
full-adders are single bit adders with the provision of
carry input (i/p) and output (o/p). The full-adders are
typically composed of two Half-Adders (HA) hence
are expensive than half-adders in terms of time, area
and interconnection complexity [8]. The common
approach for designing multi-bit adders is to form a
chain of FA blocks by connecting the carry out bit of a
FA to the carry in bit of the next FA block [1],[7][8].
Multiplication is one of the basic arithmetic
operations. Multiplication operation is also called as a
adding and shifting method [5], [8]. Multiplication
operation involves two methods: one is Generation of
partial products and another one is summation. The
speed of multiplication mainly depends on the Partial
product generation and/or summation. Therefore,
using high speed multipliers is a critical requirement
for high performance processors [5], [6], [7].
Our study is focused on the comparative analysis
of adders implemented as a multipliers based on area,
power consumption and time needed for calculation.
In this paper, the VLSI design of 32-bit unsigned
modified carry select adder (MCSLA) based multiplier
using CBL term is been proposed and compared with
the 32-bit unsigned conventional carry select adder
(CSLA) based multiplier. Here the two unsigned 32-
bit multipliers multiplies (N*N) and gives the product
term as 64-bit (2N) output [1], [8]. To model and
simulate the multiplier design a VHDL, Very high
speed integrated circuit Hardware Description
Language was used [2], [3].
Hence design of area and power-efficient high-
speed data path logic systems are one of the most
substantial areas of research in VLSI system design.
Our main interest must be on design of a better
architecture of basic building block i.e. adder [1]. So,
we need Digital Signal Processing (DSP) style system
for area efficient, less delay and low power
consumption [6]. Our basic building block must
dominate in Digital Signal Processing (DSP)
application, VLSI architecture and where ever reduced
delay is needed is needed.
2. CARRY SELECT ADDER
A conventional carry select adder (CSLA) is an RCA–
RCA configuration which has two units: SCG (The
sum and carry generator unit) and SCS (The sum and
carry selection unit) [1], [4] and [8].In Sum Carry
Generation unit (SCG), a pair of sum bits and output-
carry bits corresponding to the anticipated input-carry
(Cin =0 and Cin=1) are generated [7]. In Sum Carry
2. International Journal of Research in Advent Technology, Vol.3, No.7, July 2015
E-ISSN: 2321-9637
32
Selection unit (SCS) we compute these alternative
results in parallel and subsequently selecting one out
of each pair for final-sum and final-output-carry with
single or multiple stages of hierarchical techniques.
The correct computation is chosen when Cin is
delivered, with the help of a multiplexer to get the
desired output [7], [4]. The structure of conventional
CSLA is shown in Fig. 1.
Fig.1. Conventional carry select adder
In general, we can write the algorithm as:
If Carry in =1, then the sum and carry out are given
by,
Sum (i) =a (i) xor b (i) xor '1' (1)
Carry (i+1) = (a (i) and b (i)) or (b (i) or a (i)) (2)
If Carry in =0, then the sum and carry out are given
by,
Sum (i) = a (i) xor b (i) (3)
Carry (i+1) = a (i) and b (i) (4)
The sum function:
Si= CiSi
0
+ CiSi
1
(5)
The carry function:
Ci+1= CiCi+1
0
+ CiCi+1
1
(6)
The carry select adder is used in many digital
computational systems to reduce the problem of
propagation delay [7], [9]. The speed is improved with
this technique by saving the time used for computation
[4]. The conventional carry select adder (CSLA) is not
efficient in the case of area because it uses multiple
pairs of Ripple Carry Adders (RCA) to generate
partial sum and carry by considering carry input Cin =0
and Cin =1 separately. The SCG unit consumes most
of the logic resources of CSLA and significantly
contributes to the critical path [4], [8].
3. PROPOSED MODIFIED CSLA USING
COMMON BOOLEAN LOGIC
To remove the duplicate adder cells in the
conventional CSLA, an area efficient CSLA is
proposed by sharing Common Boolean Logic (CBL)
term in Sum Carry Generation unit [9]. The main idea
of this work is to use CBL term instead of RCA with
carry Cin =1, in order to reduce the area and power of
conventional CSLA. Thus, modified CSLA (MCSLA)
is designed such that it occupies less area and has low
power consumption than conventional CSLA. The
structure of Proposed MCSLA is shown in Fig. 2.
Fig.2. Proposed modified carry select adder using
CBL term.
To share the Common Boolean Logic term, we
only need to implement an XOR gate and one INV
gate to generate the summation pair. And to generate
the carry pair, we need to implement one OR gate and
one AND gate. In this way, the summation and carry
circuits can be kept parallel.
Fig.3. Internal structure of the proposed modified
carry select adder constructed by sharing the common
boolean logic term.
3. International Journal of Research in Advent Technology, Vol.3, No.7, July 2015
E-ISSN: 2321-9637
33
In general, we can write the algorithm as:
If Carry in =1, then the sum and carry out are given
by,
Sum (i) =a (i) xor b (i). (7)
Carry (i+1) = a (i) or b (i) (8)
If Carry in =0, then the sum and carry out are given
by,
Sum (i) = (a (i) xor b (i))' (9)
Carry (i+1) = a (i) and b (i) (10)
The sum function:
Si= CiSi
0
+ CiSi
1
(11)
The carry function:
Ci+1= CiCi+1
0
+ CiCi+1
1
(12)
TABLE I: Truth Table of single bit full adder, where
the upper half part is the case of Cin=0 and the lower
half part is the case of Cin=1
While analyzing the truth table of single bit full
adder, result shows that the output of summation
signal as carry-in signal is logic “0” is inverse signal
of itself as carry-in signal is logic “1” [1].The speed is
improved with this technique by saving the time used
for computation. The area occupied and power
required for this design is less when compared to
conventional CSLA because CBL term is used instead
of an RCA for Cin =1, to generate partial sum and
carry [1].
4. UNSIGNED MULTIPLIER
The multiplier is one of the hardware key blocks in
Digital signal processing techniques [6]. The
multiplier involves generation of partial products, one
for each digit in the multiplier as in Fig.4.These partial
products are then summed to produce the final
product. The N-bit multiplier multiplies two N-bit
values and gives the final product term as a 2N-bit
value [2], [8], [9]. A Partial Schematic of 32-bit
Unsigned Multiplier is shown in Fig.4.
Fig.4. A partial schematic of unsigned multiplier
We use the following algorithm to implement the
multiplication operation for unsigned data [10].
5. MULTIPLICATION ALGORITHM
Let the product register size be 64 bits and the
multiplicand register size is 32 bits. Store the
multiplier in the least significant half of the product
register. Clear the most significant half of the product
register [2], [8], [10].
Repeat the following steps for 32 times:
1. If the least significant bit (LSB) of the
product register is “1” then add the
multiplicand to the most significant (MSB)
half of the product register.
2. Shift the content of the product register one
bit to the right (ignore the shifted-out bit).
3. Shift-in the carry bit into the most significant
bit of the product register.
4. International Journal of Research in Advent Technology, Vol.3, No.7, July 2015
E-ISSN: 2321-9637
34
The flow chart for the multiplication algorithm is
shown in Fig.5.
Fig.5. Flow chart of multiplication algorithm
The block diagram for n-bit Multiplier using the
multiplication algorithm [8], [9], [10] is shown in
Fig.6.
Fig.6. Multiplier block diagram for two n-bit
values
6. VHDL SIMULATION RESULTS
The VHDL model for both the 32-bit unsigned
multipliers has been simulated using Modelsim and
synthesized using Xilinx and presented in this section
[9], [10].
6.1. 32-bit unsigned CSLA multiplier
6.1.1. Schematic
Fig.7. Schematic of 32-bit unsigned CSLA
multiplier
6.1.2. Simulation result
Fig.8. Simulation result of 32-bit unsigned CSLA
multiplier
6.2. 32-bit unsigned MCSLA multiplier
6.2.1. Schematic
Fig.12. Schematic of 32-bit unsigned MCSLA
multiplier