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1. 1
ASYNCHRONOUS DATA TRANSACTIONS ON SoC USING FIFO
BETWEEN ADVANCED EXTENSIBLE INTERFACE 4.0 AND ADVANCED
PERIPHERAL BUS 4.0
A VIJAY KUMAR*
, T VINAYSIMHA REDDY**
,M SANTHOSHI***.
*
ECE DEPARTMENT, MRCET, INDIA.
**
ECE DEPARMENT, MRCET, INDIA.
***
ECE DEPARMENT, CVRCC, INDIA.
ABSTRACT : Recently, VLSI technology has improved
significantly and more transistors can be integrated into a chip.
This makes the ideal of system-on-a-chip (SoC) more of an
achievable goal than an abstract dream. The on-chip-bus (OCB)
which connects silicon intellectual property (SIP) in a system-on-
a-chip (SoC) plays a key role in affecting the system
performance. Advanced Microcontroller Bus Architecture
(AMBA) bus protocol has been proposed by ARM community to
justify the uneven demand of integrity. Recently, a new
generation of packet-based OCB protocol called Advance
extensible Interface 4.0 (AXI4.0) has been proposed. AMBA
AXI4.0 protocol system supports 16 masters and 16 slaves
interfacing. It supports for removal of locked transactions. . This
paper presents a project aimed to do data transactions on SoC
to low speed APB4.0 from the AXI4.0 using asynchronous
FIFO.A asynchronous FIFO has been considered to avoid the
complex hand shaking mechanism. By setting write pointer, read
pointer, empty flags & full flags for the read operation and write
operation the data will be transmitted between them. This paper
modelled in a Verilog hardware description language (HDL) and
simulation results for read and write operation of data and
address are shown in ISE simulator.
.Keywords - AMBA Bus Protocol, APB 4.0, AXI4.0,
Asynchronous FIFO, FPGA Vertex 3, SoC , VerilogHDL, and
ISE Simulator.
1.INTRODUCTION
Recently due to the miniaturization of semiconductor process
technology and computation for survival in the current market
conditions constant customization is required. VLSI technology
has improved significantly and more transistors can be integrated
into a chip. This makes the ideal of system-on-a-chip (SoC) It
may consists all intellectual property blocks on a single chip
substrate. IP is an inevitable choice with size constraint. A SoC
platform usually consists of various design components
dedicated to specified application domains SoC buses are used to
interconnect an Intellectual Property (IP) core to the other
intellectual property core. They are reside in Field Programmable
Gate Array (FPGA). The AMBA (Advanced Microcontroller Bus
Architecture) on-chip interconnect system is an established open
specification that details a strategy on the interconnection and
management of functional blocks that makes up a SoC. AMBA
was introduced in the year 1996 by ARM limited.
AMBA has four generations of buses. The details of the
generations and their interfaces are as given below:
 AMBA specification
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)
 AMBA 2.0
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB2 or APB)
 AMBA 3.0
Advanced eXtensible Interface ( AXI v1.0)
Advanced High-performance Bus Lite
(AHB-Lite v1.0)
Advanced Peripheral Bus (APB3 v1.0)
Advanced Trace Bus (ATB v1.0)
 AMBA 4.0
AXI Coherency Extensions (ACE)
AXI Coherency Extensions Lite (ACE-Lite)
Advanced eXtensible Interface 4 (AXI4)
Advanced eXtensible Interface 4 Lite (AXI4Lite)
Advanced eXtensible Interface 4 Stream (AXI4-Stream v1.0)
Advanced Trace Bus (ATB v1.1)
Advanced Peripheral Bus (APB4 v2.0)
AMBA defines both a bus specification and a technology-
independent methodology for designing, high-integration
embedded controllers. Advanced eXtensible Interconnect
(AXI4.0) was introduced in AMBA 3.0 as the successor on-chip
bus protocol of the AHB in AMBA 2.0. The AXI4.0 protocol is a
high-performance and high bandwidth bus includes a number of
features that make it suitable for high-speed submicron’s
interconnect.
1.1 AMBA axi4.0 Architecture
AMBA AXI4 supports burst and unaligned data transfers. In
AMBA AXI4.0 system interface 16 masters to slaves. Each
master and slave has their own 4 bit identification tags. .
AMBA AXI4 system c o n s i s t s o f m a s t e r , s l a v e a n d
b u s i n t e r c o n n e c t s . The AXI4.0 consists of five channels
namely write address, write data, read data, read address, an d
wr i t e r e s p on s e chann el s.
The AX I4. 0 protocol supports the following mechanisms:
 Burst and unaligned data transfers and up-dated write
response acknowledgment.
 A burst data bits wide 8, 16, 32, 64, 128, 256,512 or
1024 bits.
 Updated AWCACHE and ARCACHE signalling
details.
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2. 2
The AMBA AXI4.0
specification satisfies four key
requirements:
 To design high speed embedded micro controller
products with one or more CPUs signal processors
 System macro-cells and highly reusable peripheral can
be migrated across a diverse range IC processes and be
appropriate for full-custom ,standard cell and gate array
technologies
 To improve independence of processor ,providing a
development road-map for advanced cached CPU cores
and the development of peripheral libraries
 For success efficient on-chip and off-chip
communication
To encourage modular system design to improve processor
independence, providing a development road- The AMBA 4.0
specification defines five buses/interfaces.
 Advanced eXtensible Interface (AXI)
 •Advanced High-performance Bus (AHB)
 Advanced System Bus (ASB)
 Advanced Peripheral Bus (APB)
 Advanced Trace Bus (ATB)
Fig.1 Block diagram of AMBA AXI4.0 bus interconnect.
Fig.2 Block diagram of AXI 4.0 master
To perform write address and data operation the
transaction is initiated with concatenated input of [awaddr, awid,
awcache, awlock, awprot, awburst]. On the same lines for read
address and data operations the concatenated input is [araddr,
arid, arcache, arlock, arprot, arburst]. The addresses of read
and write operations are validated by VALID signals and sent to
interface unit. The acknowledgement signals of slave will
become incoming signals to master.
Fig.3 Write address and data burst
The write operation process starts when the master sends an
address and control information on the write address channel
as shown in figure.3. The master then sends each item of write
data over the write data channel. The VALID signal is low by
master until the write data available in write data channel .The
WLAST signal goes HIGH for the master last data. Slave
drives a write response signal BRESP[1:0] back to the master
to indicate that the write transaction is complete When the it
has accepted all the data items, . The completion of the
write transaction indicated by this signal. OKAY, EXOKAY,
SLVERR, and DECERR are the allowable responses by the
slave to the master.
Fig.4 Block diagram of AXI4.0 slave
The data transfer occurs on the read data channel when the read
address appears on the address bus hence the data transfer occurs
on the read data channel as shown in figure 5. The VALID signal
LOW by the slave until the read data is present in read data
channel. For the last data transfer of the burst signal, the slave
provides the RLAST signal to show that the last data item is
being moved. The status of the read transfer indicated by the
RRESP[1:0] signal ,OKAY, EXOKAY, SLVERR, and DECERR
are the allowable responses..
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3. 3
Fig.5: Read address and data burst
1. 2 AMBA AXI4.0 Interconnect
The interconnect block consists of decoder and arbiter. When
more than one master initiates a transaction simultaneously,
the priority is given by the arbiter to access the bus. The
address sent by any of the master is decoded by the decoder
and the control goes to one slave out of 16 and also address
goes by one of the salve out of 16. The AMBA AXI4.0
interface decoder is centralized block.
Fig 6: Signals used to design AMBA AXI4.0 modules
1.3 Finite state machine of AXI 4.0
Write and read operations between the channels can be
explained by using below finite state machine.
Fig.7 Finite state machine of axi4.0 read and write operation.
2. PROPOSED WORK
The AXI4.0 to APB4.0 Bridge provides an interface between the
high-performance AXI domain and In this proposed work data
transactions can be done between high speed AXI4.0 bus to low
power APB4.0 bus using asynchronous FIFO.Which act as a
interface between them. Read and write transfers on the AXI4.0
bus are converted into corresponding transfers on the APB4.0.
2.1 Asynchronous FIFO
Asynchronous FIFOs are widely used in the computer
networking industry to receive data at a particular clock and
transmit them at another clock. An asynchronous FIFO has two
different clocks one for read and one for write. There are issues
that arise when passing data over asynchronous clock values.
Data could be over-written and hence lost when the write clock is
faster than the read clock, . In order to overcome these problems,
control signals like write pointer, read pointer, empty and full
flags are required.
Fig.8 Asynchronous FIFO state machine
2.1.1 Functional description of A Asynchronous
FIFO
Functionally the FIFO works as follows: At reset, the write and
read pointers are both at null value. This is the empty condition
of the FIFO, and empty is pulled high (we use the active high
convention) and full is low. At null or empty, read operations are
stopped and so the only write operations are possible in to the
FIFO. Location 0 of the RAM nothing but the array loaded by
Write and increments the write pointer to. This results the empty
flag to go LOW. Consider that there are subsequent cycles only
write to the FIFO and no reads, there will be a certain time when
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4. 4
the write pointer will equal array _size -1. This means that the
last location in the array is the next location that will be written
to. At this condition, the write pointer to become 0 due to write,
and set full. Note that in this condition the write pointer and read
pointers are equal, and not empty or null but the FIFO said to be
full. This implies that the FIFO full/empty decision depends on
the write pointer and read pointers when they will become equal
due to the read or write operation between them but not based on
the pointer values alone. When the pointer equality is a reset or a
read, the FIFO said to be empty; if the cause is a write, the FIFO
said to be full.
Now consider that we begin a multiple reads. The read pointer is
incremented by each read operation till the point where the read
pointer equals array_ size -1. At this point, the data from this
location of RAM or array size is available on the output bus of
FIFO.Succeeding logic reads this data and provides a read signal
(active for one clock). And hence the read pointer to become
equal to the write pointer again (after both pointers have
completed one cycle through the array). However, empty is set
since pointers are equal due to read operation.
Fig.9 Circuit for write and read pointers of FIFO
2.2 AXI4.0 Slave Interface
The AXI4.0 Slave Interface module provides a bi-directional
slave interface to the AXI. The AXI address and data bus widths
are always fixed to 32-bits and 1024bits.When both write and
read transfers are simultaneously requested on AXI4.0, more
priority is given for read request and less priority is given for the
write request. This block also contains the data phase time out
logic for generating OK response on AXI interface when APB4.0
does not respond.
2.3 APB4.0 Master Interface
The APB4.0 module provides the APB master interface on the
APB. This interface can be APB2 or APB3 or APB4, these are
chosen by setting the generic C_M_APB_PROTOCOL. When
C_M_APB_PROTOCOL=apb4. At the APB Interface
M_APB_PSTRB and M_APB_PPROT signals are driven. The
APB address bus and data bus widths are fixed to 32-bits.
2.4 Mechanisms of AXI4.0 & APB4.0
2.4.1 Flow chart representation
A diagram of the sequence of movements or actions of people or
things involved in a complex system or activity. A graphical
representation of a computer program in relation to its sequence
of functions (as distinct from the data it processes).It can be
applicable for all the engineering branches.
The flow of moving data from FIFO between protocols is as
follows
 If the FIFO is empty then empty flag indicates to the
write pointer to write data into the FIFO and then write
pointer incremented.
 If the FIFO is full then full flag indicates to the read
pointer to readout data from the FIFO to the APB
master.
Fig.10 Flowchart of general FIFO
2.4.2 Finite state machine representation of
Asynchronous FIFO
FSM is a mathematical tool used to design system programs and
digital circuits. It is a behaviour model composed of a finite
number of states, transitions among all states, similar to a flow
graph in which one can inspect the way logic runs when certain
conditions are met. It is considered as an abstract machine, which
is in only one state at a time. The current state is a state which is
present at particular time .By initiated a triggering event or
condition, It can change from one state to another state is called a
transition for that state. A finite state machine is a mathematical
abstraction model .According AXI4.0 specification, the read
address channel, write address channel, read data channel and
write data channel are completely independent. A read and a
write requests may be issued simultaneously from AXI4, the
AXI4.0 to APB Bridge of asynchronous will give more priority
to the read request and less priority to the write request. That is,
the write request is initiated on APB4.0 after the read is
requested on APB4.0 when both write and read requests are
valid.
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5. 5
Fig.11 FSM of Asynchronous FIFO
2.5 Advanced Peripheral Bus (APB4.0) Protocol
The Advanced Peripheral Bus (APB) is a part of AMBA
Architecture protocol family. It t is optimized for minimal power
consumption and reduced interface complexity. It defines a low-
cost interface. To enable the integration of APB4.0 peripherals
easily into any design flow all signal transitions are only related
to the rising edge of the clock. Every transfer takes At least two
cycles are required for the every data transfer by APB4.0.The
APB can interface with the AMBA Advanced High-performance
Bus Lite (AHB-Lite) and AMBA AXI4.0 Advanced Extensible
bus.
2.6 Handshake Mechanism of AXI4.0 & APB4.0
In AXI 4.0 specification, VALID and READY signals are
present in each and every channel for hand shaking mechanism.
When the control information or data is available then source
asserts VALID and when destination can accept the control
information or data then it asserts READ signal. When both the
VALID and READY signals are asserted then only transfer takes
place. Note that when source asserts VALID, the corresponding
control information or data must also be available, at the same
time at the positive edge of clock transfer takes place. Therefore,
the source and destination need register inputs to sample the
READY and VALID signals. Therefore source and destination
should use combinational circuit as output. In short, AXI4.0
protocol is suitable input register and combinational output
circuit.
The APB4.0 Bridge buffers address, control and data from
AXI4.0, drives the APB4.0 peripherals and returns data and
response signal to the AXI4.0.By using internal address map it
decodes the address to select the peripheral. The bridge is
designed to operate when the APB4.0 and AXI4.0have
independent clock frequency and phase by using asynchronous
FIFO. For every AXI4.0 channel, invalid commands are not
forwarded and an error response generated. the APB Bridge will
generate DE CERR response through the response channel (read
or write) if peripheral accessed does not exist. And it asserts
PSLVERR if the target peripheral exists, but, it will give a
SLVERR response.
Fig.12 Block diagram of signal connections between AXI4.0 and
APB4.0
3. SIMULATION AND SYNTHESIS RESULT
Fig.13 Channels in AXI 4.0
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6. 6
Fig.14 Burst data transactions between AXI4.0 master and slave
Fig.15 AXI4.0 RTL Schematic view
Fig.16 AXI 4.0 Technology schematic view
Fig.17 Data transaction between AXI4.0 and APB4.0
Fig.18 AXI 4.0 to APB4.0 RTL schematic view
Fig.19 Top module RTL schematic view of AXI4.0 to APB4.0
Fig.20 AXI 4.0 to APB4.0 tech schematic view
3. CONCLUSION
 The implementation asynchronous data transactions on
SoC using FIFO between Advanced eXtensible
Interface and Advanced peripheral Bus is designed
.Verilog HDL has been used for implementing bridge
between them.
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7. 7
 The bridge defines low cost interface optimized for
minimal power consumption and reduced interface
complexity.
4. FEATURES
 32-bit AXI4.0 slave and APB4.0 master interfaces.
 PCLK clock domain completely independent of clock
domain.
 Support up to 16 APB4.0 peripherals
 Burst length is 32 bits
 PREADY signal is supported, which translates to wait
states on AXI.
 An error on any transfer results in SLVERR as the
AXI4.0 read/write response.
5. FUTURE SCOPE
 The design will be extended by developing a total
system around it.
 This work provides an ideal platform for enhancement
or further development of the Bus Bridge Design
between AXI4.0 and APB4.0 protocols.
 When read request and write request are simultaneously
occurs the bridge gives the high priority to read request.
this condition creates the race condition in APB4.0
Bridge.
 For date item from the FIFO and now the read date
FIFO was empty. Again read and write requests are
example FIFO has only one date item to read operation.
If read and write requests are simultaneously occurs the
bridge first execute the read request and it read the
single simultaneously occurs again it execute read
request but there is no data item in read data FIFO so
transaction will fail. This situation is called race
condition.
6. ACKNOWLEDGMENT
I A VIJAY KUMAR would like to thank Assistant Prof T.
Vinaysimha Reddy, who had been guiding through out to
complete the work effectively and successfully, and would also
like to thank the Prof.P Sanjeeva Reddy HOD, ECE Department
and other Professors for extending their help & support in giving
technical ideas about the paper and motivating to complete the
work effectively & successfully.
7. REFERENCES
[1] ARM, AMBA Specifications (Rev2.0). [Online]. Available
at http://www.arm.com, 1999
[2] ARM, AMBA AXI Protocol Specification (Rev 2.0),
Available at http://www.arm.com, March 2010
[3] Shaila S Math, Manjula R B, “Survey of system on chip
buses based on industry standards”, Conference on
Evolutionary Trends in Information Technology(CETIT),
Bekgaum,Karnataka, India, pp. 52, May 2011
[4] Design and Implementation of APB Bridge based on
AMBA 4.0 (IEEE 2011), ARM Limited.
[5] http://www.arm.com/products/system-ip/amba/ambaopen-
specifications.php
[6] ARM, "AMBA Protocol Specification 4.0",
www.arm.com, 2010 ARM,AMBA Specification
[7] LogiCORE IP AXI to APB Bridge (v1.00a) DS788 June
22, 2011 Product Specification.
[8] Simulation and Synthesis Techniques for Asynchronous
FIFO Design Clifford E.Cummings, Sunburst
Design, Inc. SNUG San Jose 2002 Rev 1.2.,FIFO
Architecture, Functions, and Applications SCAA042A
November 1999.
[9] Lahir, K., Raghunathan A., Lakshminarayana G.,
“LOTTERYBUS: a new high-performance
communication architecture for system-on- chip deisgns,”
in Proceedings of Design Automation
Conference, 2001.
[10] Ying-Ze Liao, "System Design and Implementation of AXI
Bus", National Chiao Tung University,
October 2007.
AUTHOR BIOGRAPHY
A VIJAY KUMAR received B. Tech degree in Electronics and
Communication Engineering from JNTU affiliated college in
2009 and Pursuing M. Tech in VLSI & Embedded systems from
JNTU affiliated college.
T VINAYSIMHA REDDY received M.Tech in VLSI System
Design from JNTU affiliated college in 2010 from JNTU
affiliated college. And his interested areas are in Embedded
systems and VLSI Design .Now he is working as an Asst. Prof.
in JNTU affiliated college, Hyderabad, INDIA.
M. Santhoshi received M.Tech in VLSI System Design from
JNTU affiliated college in 2012 from JNTU affiliated college.
And her interested areas are in Image and video processing .Now
she is working as an Asst. Prof. in JNTU affiliated college,
Hyderabad, INDIA.
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