This document discusses 2.5D and 3D chip stacking technologies and the supply chain integration for their development. It outlines applications for 2.5D stacking of logic and memory chips as well as 3D stacking using through-silicon vias. The ecosystem workflow for 2.5D stacking is described, involving various partners from foundries to outsourced assembly and test houses. Finally, the document emphasizes that foundry development of through-silicon via processes has demonstrated key process issues can be identified and resolved, while ecosystem focus going forward includes product reliability assessment and collaboration on tools for 3D design.

1. 2.5D/3D Chip Stacking Supply
Chain Integration
Kurt Huang, Ph.D.
Director, Corporate Marketing, UMC
ChipEx, 2013

2. Outline
 2.5D/3D Applications
 Ecosystem Work Flow
 Summary
P. 2

3. 2.5D/3D Applications

4. 2.5D Si Interposer Stacking
 Logic/logic: FPGA, networking infrastructure
 Logic/memory: Gaming, HPC

5. 3D Logic/Memory Stacking
- Via-Middle TSV 28nm Logic + Memory Cube
 Mobile WideIO, Computing WideIO, HMC

6. Never-Enough Memory Bandwidth
- Mobile AP Driving Wide IO Memory
Dimensioning use case:
 3D video streaming playback to external display via wireless
+ on-line 3D gaming local

7. Keeping Power Under Hood
•LPDDR3 @800Mhz
dual-channel
•LPDDR3 @800Mhz

8. Real Value Drives Adoption
Motivations:
 Higher BW, lower W/BW, smaller form-factor
Opportunity of return on 3D IC investment:
 Chip process node optimization
 Homogeneous partition
 Cross-node combinations
 BOM cost optimization
 Less demanding substrate/PCB,
lighter cooling assembly, ...
 Ultimately: better product, better margin
Xilinx Virtex 7
Micron HMC

9. Application Examples

10. Market Segment Overview
 High performance driving
2.5DIC
 Mobile AP driving 3DIC
 SoC + Mobile Memory
 Next wave:
heterogeneous 3DIC
 Logic + Memory +
Analog/RF
 Ecosystem more
complex
 Expect driving force
emerges after 3DIC
matures

11. Ecosystem Work Flow

12. Example 2.5D Stacking Flow

13. Various Work Models
 Service scopes distinguished by MEOL inclusion
 Consult your foundry/OSAT
 Work flow optimization may depend on BOM cost,
stack recipe and test strategy

14. Foundry TSV Design Collaterals
 Consider TSV a passive device with rule decks/models
 Typical foundry engagement applies under ecosystem work flow
(UMC 2.5D Si interposer documents)

15. Innovations by Open Eco-System
 Wafer thinning and handling
 Thermal/stress
consideration
 Testability
 Reliability
 3D EDA tool
 Seamless business model
 Cost
 …

16. Evolution Of the Supply Chain
 Technology exploration
 Feasibility study
 Interface definition
 Handover criteria
 Model convergence
 Flow standarization
 Cost down
 Service differentiation
 Further innovation

17. UMC Ecosystem Effort
1Q1
2
2Q1
2
1Q1
3
2Q1
3

18. Summary

19. Summary
 Foundry TSV process demonstrated
 Applicable to both 2.5D/3D
 Leverage existing CMOS process technology
 Key process issues identified & conquered
 Ecosystem work flow
 Typical foundry/OSAT engagement flow applies for both
2.5D/3D, among other models
 Foundry TSV next step: ecosystem focus
 Product level reliability assessment
 3D package level reliability demonstrated for open
ecosystem model
 Potential EDA collaboration for emerging 3D tools

20. BTW, Dreams Do Come True!

21. Thank you for your attention!
Contact: kurt_huang@umc.com